diff options
| -rw-r--r-- | usrp2/timing/time_64bit.v | 6 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 6 |
2 files changed, 10 insertions, 2 deletions
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index a03f437e8..33eb2b25a 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -7,7 +7,8 @@ module time_64bit input set_stb, input [7:0] set_addr, input [31:0] set_data, input pps, output [63:0] vita_time, output pps_int, - input exp_time_in, output exp_time_out + input exp_time_in, output exp_time_out, + output [31:0] debug ); localparam NEXT_SECS = 0; @@ -137,5 +138,8 @@ module time_64bit assign mimo_secs = vita_time_rcvd[63:32]; assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay}; assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC); + + assign debug = { { 24'b0} , + { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} }; endmodule // time_64bit diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index c2d473650..30b47b818 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -720,9 +720,13 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // VITA Timing + wire [31:0] debug_sync; + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins |