16 files changed, 248 insertions, 101 deletions
diff --git a/fpga/usrp1/toplevel/usrp_std/usrp_std.v b/fpga/usrp1/toplevel/usrp_std/usrp_std.v
index 8b29a9c21..83a89cb81 100644
--- a/fpga/usrp1/toplevel/usrp_std/usrp_std.v
+++ b/fpga/usrp1/toplevel/usrp_std/usrp_std.v
@@ -28,8 +28,8 @@
 // Uncomment the following to include optional circuitry
 
 `include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../../../firmware/fx2/common/fpga_regs_common.v"
+`include "../../../../firmware/fx2/common/fpga_regs_standard.v"
 
 module usrp_std
 (output MYSTERY_SIGNAL,
diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt
index 552fe492c..6b342c2d3 100644
--- a/host/CMakeLists.txt
+++ b/host/CMakeLists.txt
@@ -102,6 +102,8 @@ ENDIF(WIN32)
 ########################################################################
 # Setup Boost
 ########################################################################
+MESSAGE(STATUS "")
+MESSAGE(STATUS "Configuring Boost C++ Libraries...")
 SET(BOOST_REQUIRED_COMPONENTS
     date_time
     filesystem
@@ -131,6 +133,10 @@ FIND_PACKAGE(Boost 1.36 COMPONENTS ${BOOST_REQUIRED_COMPONENTS})
 INCLUDE_DIRECTORIES(${Boost_INCLUDE_DIRS})
 LINK_DIRECTORIES(${Boost_LIBRARY_DIRS})
 
+MESSAGE(STATUS "Boost include directories: ${Boost_INCLUDE_DIRS}")
+MESSAGE(STATUS "Boost library directories: ${Boost_LIBRARY_DIRS}")
+MESSAGE(STATUS "Boost libraries: ${Boost_LIBRARIES}")
+
 ########################################################################
 # Check Python Modules
 ########################################################################
diff --git a/host/Modules/UHDPackage.cmake b/host/Modules/UHDPackage.cmake
index bf31df3b3..1988c7f11 100644
--- a/host/Modules/UHDPackage.cmake
+++ b/host/Modules/UHDPackage.cmake
@@ -140,4 +140,9 @@ SET(CPACK_DEBIAN_PACKAGE_RECOMMENDS "python, python-tk")
 SET(CPACK_RPM_PACKAGE_REQUIRES "boost-devel, libusb1")
 
 ########################################################################
+# Setup CPack NSIS
+########################################################################
+SET(CPACK_NSIS_MODIFY_PATH ON)
+
+########################################################################
 INCLUDE(CPack) #include after setting vars
diff --git a/host/Modules/UHDPython.cmake b/host/Modules/UHDPython.cmake
index 90a778609..fdcdccb4b 100644
--- a/host/Modules/UHDPython.cmake
+++ b/host/Modules/UHDPython.cmake
@@ -15,9 +15,14 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
+IF(NOT DEFINED INCLUDED_UHD_PYTHON_CMAKE)
+SET(INCLUDED_UHD_PYTHON_CMAKE TRUE)
+
 ########################################################################
 # Setup Python
 ########################################################################
+MESSAGE(STATUS "")
+MESSAGE(STATUS "Configuring the python interpreter...")
 #this allows the user to override PYTHON_EXECUTABLE
 IF(PYTHON_EXECUTABLE)
 
@@ -42,6 +47,9 @@ ENDIF(PYTHON_EXECUTABLE)
 #make the path to the executable appear in the cmake gui
 SET(PYTHON_EXECUTABLE ${PYTHON_EXECUTABLE} CACHE FILEPATH "python interpreter")
 
+MESSAGE(STATUS "Python interpreter: ${PYTHON_EXECUTABLE}")
+MESSAGE(STATUS "Override with: -DPYTHON_EXECUTABLE=<path-to-python>")
+
 IF(NOT PYTHONINTERP_FOUND)
     MESSAGE(FATAL_ERROR "Error: Python interpretor required by the build system.")
 ENDIF(NOT PYTHONINTERP_FOUND)
@@ -53,17 +61,26 @@ MACRO(PYTHON_CHECK_MODULE desc mod cmd have)
         COMMAND ${PYTHON_EXECUTABLE} -c "
 #########################################
 try: import ${mod}
-except: exit(-1)
+except: exit(1)
 try: assert ${cmd}
-except: exit(-1)
+except: exit(2)
+exit(0)
 #########################################"
         RESULT_VARIABLE ${have}
     )
     IF(${have} EQUAL 0)
         MESSAGE(STATUS "Python checking for ${desc} - found")
         SET(${have} TRUE)
-    ELSE(${have} EQUAL 0)
-        MESSAGE(STATUS "Python checking for ${desc} - not found")
+    ELSEIF(${have} EQUAL 1)
+        MESSAGE(STATUS "Python checking for ${desc} - \"import ${mod}\" failed")
+        SET(${have} FALSE)
+    ELSEIF(${have} EQUAL 2)
+        MESSAGE(STATUS "Python checking for ${desc} - \"assert ${cmd}\" failed")
         SET(${have} FALSE)
-    ENDIF(${have} EQUAL 0)
+    ELSE()
+        MESSAGE(STATUS "Python checking for ${desc} - unknown error")
+        SET(${have} FALSE)
+    ENDIF()
 ENDMACRO(PYTHON_CHECK_MODULE)
+
+ENDIF(NOT DEFINED INCLUDED_UHD_PYTHON_CMAKE)
diff --git a/host/Modules/UHDVersion.cmake b/host/Modules/UHDVersion.cmake
index eb25db488..86d3133a8 100644
--- a/host/Modules/UHDVersion.cmake
+++ b/host/Modules/UHDVersion.cmake
@@ -42,34 +42,18 @@ ENDIF()
 
 IF(UHD_BUILD_INFO_DISCOVERY)
 
-    #grab the git log entry for the current head
-    EXECUTE_PROCESS(
-        WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
-        COMMAND ${GIT_EXECUTABLE} log HEAD~..HEAD --date=raw -n1
-        OUTPUT_VARIABLE _git_log OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
-
-    #extract the timestamp from the git log entry
-    EXECUTE_PROCESS(
-        WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
-        COMMAND ${PYTHON_EXECUTABLE} -c "import re; print re.match('^.*Date:\\s*(\\d*).*$', ''' ${_git_log} ''', re.MULTILINE | re.DOTALL).groups()[0]"
-        OUTPUT_VARIABLE _git_timestamp OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
-
-    #format the timestamp into YYYY-MM-DD-HH-MM-SS
-    EXECUTE_PROCESS(
-        COMMAND ${PYTHON_EXECUTABLE} -c "import time; print time.strftime('%Y%m%d%H%M%S', time.gmtime(${_git_timestamp}))"
-        OUTPUT_VARIABLE _git_date OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
-
     #grab the git ref id for the current head
     EXECUTE_PROCESS(
         WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
         COMMAND ${GIT_EXECUTABLE} rev-parse --short HEAD
         OUTPUT_VARIABLE _git_rev OUTPUT_STRIP_TRAILING_WHITESPACE
+        RESULT_VARIABLE _git_rev_result
     )
 
-    SET(UHD_BUILD_INFO ${_git_rev})
+    #only set the build info on success
+    IF(_git_rev_result EQUAL 0)
+        SET(UHD_BUILD_INFO ${_git_rev})
+    ENDIF()
 ENDIF(UHD_BUILD_INFO_DISCOVERY)
 
 ########################################################################
diff --git a/host/docs/dboards.rst b/host/docs/dboards.rst
index 419456df2..373189441 100644
--- a/host/docs/dboards.rst
+++ b/host/docs/dboards.rst
@@ -27,12 +27,14 @@ Though the magic of aliasing, you can down-convert signals
 greater than the Nyquist rate of the ADC.
 
 BasicRX Bandwidth (Hz): 
-    For Real-Mode (A or B subdevice): 250M
-    For Complex (AB or BA subdevice): 500M
+
+* For Real-Mode (A or B subdevice): 250M
+* For Complex (AB or BA subdevice): 500M
 
 LFRX Bandwidth (Hz):
-    For Real-Mode (A or B subdevice): 33M
-    For Complex (AB or BA subdevice): 66M
+
+* For Real-Mode (A or B subdevice): 33M
+* For Complex (AB or BA subdevice): 66M
 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 Basic TX and and LFTX
@@ -49,31 +51,67 @@ Though the magic of aliasing, you can up-convert signals
 greater than the Nyquist rate of the DAC.
 
 BasicTX Bandwidth (Hz): 250M
-    For Real-Mode (A or B subdevice): 250M
-    For Complex (AB or BA subdevice): 500M
+
+* For Real-Mode (A or B subdevice): 250M
+* For Complex (AB or BA subdevice): 500M
 
 LFTX Bandwidth (Hz): 33M
-    For Real-Mode (A or B subdevice): 33M
-    For Complex (AB or BA subdevice): 66M
+
+* For Real-Mode (A or B subdevice): 33M
+* For Complex (AB or BA subdevice): 66M
 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 DBSRX
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
-The DBSRX board has 1 quadrature subdevice.
+The DBSRX board has 1 quadrature subdevice.  
+It defaults to direct conversion, but can use a low IF through lo_offset in uhd::tune_request_t
 
 Receive Antennas: **J3**
 
 The board has no user selectable antenna setting
 
-Receive Gains: 
-    **GC1**, Range: 0-56dB
-    **GC2**, Range: 0-24dB
+Receive Gains:
+
+* **GC1**, Range: 0-56dB
+* **GC2**, Range: 0-24dB
 
 Bandwidth (Hz): 8M-66M
 
+Sensors:
+
+* **lo_locked**: boolean for LO lock state
+
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+DBSRX2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The DBSRX2 board has 1 quadrature subdevice.
+It defaults to direct conversion, but can use a low IF through lo_offset in uhd::tune_request_t
+
+Receive Antennas: **J3**
+
+The board has no user selectable antenna setting
+
+Receive Gains:
+
+* **GC1**, Range: 0-73dB
+* **BBG**, Range: 0-15dB
+
+Bandwidth (Hz): 8M-80M
+
+Sensors:
+
+* **lo_locked**: boolean for LO lock state
+
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 RFX Series
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The RFX Series boards have 2 quadrature subdevices, one transmit, one receive.
+Transmit defaults to low IF and Receive defaults to direct conversion.
+The IF can be adjusted through lo_offset in uhd::tune_request_t
+
+The RFX Series boards have independent receive and transmit LO's and synthesizers 
+allowing full-duplex operation on different transmit and receive frequencies.
+
 Transmit Antennas: **TX/RX**
 
 Receive Antennas: **TX/RX** or **RX2**
@@ -85,12 +123,21 @@ the receive antenna will always be set to RX2, regardless of the settings.
 Receive Gains: **PGA0**, Range: 0-70dB (except RFX400 range is 0-45dB)
 
 Bandwidths (Hz):
- * **RX**: 40M
- * **TX**: 40M
+
+* **RX**: 40M
+* **TX**: 40M
+
+Sensors:
+
+* **lo_locked**: boolean for LO lock state
 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 XCVR 2450
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The XCVR2450 has 2 quadrature subdevices, one transmit, one receive.
+Transmit and Receive default to direct conversion but
+can be used in low IF mode through lo_offset in uhd::tune_request_t
+
 The XCVR2450 has a non-contiguous tuning range consisting of a 
 high band (4.9-6.0GHz) and a low band (2.4-2.5GHz).
 
@@ -106,20 +153,35 @@ The XCVR2450 does not support full-duplex mode, attempting to operate
 in full-duplex will result in transmit-only operation.
 
 Transmit Gains:
- * **VGA**, Range: 0-30dB
- * **BB**, Range: 0-5dB
+
+* **VGA**, Range: 0-30dB
+* **BB**, Range: 0-5dB
 
 Receive Gains:
- * **LNA**, Range: 0-30.5dB
- * **VGA**, Range: 0-62dB
+
+* **LNA**, Range: 0-30.5dB
+* **VGA**, Range: 0-62dB
 
 Bandwidths (Hz):
- * **RX**: 15M, 19M, 28M, 36M; (each +-0, 5, or 10%)
- * **TX**: 24M, 36M, 48M
+
+* **RX**: 15M, 19M, 28M, 36M; (each +-0, 5, or 10%)
+* **TX**: 24M, 36M, 48M
+
+Sensors:
+
+* **lo_locked**: boolean for LO lock state
+* **rssi**:      float for rssi in dBm
 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 WBX Series
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The WBX Series boards have 2 quadrature subdevices, one transmit, one receive.
+Transmit and Receive default to direct conversion but
+can be used in low IF mode through lo_offset in uhd::tune_request_t
+
+The WBX Series boards have independent receive and transmit LO's and synthesizers 
+allowing full-duplex operation on different transmit and receive frequencies.
+
 Transmit Antennas: **TX/RX**
 
 Receive Antennas: **TX/RX** or **RX2**
@@ -133,17 +195,26 @@ Transmit Gains: **PGA0**, Range: 0-25dB
 Receive Gains: **PGA0**, Range: 0-31.5dB
 
 Bandwidths (Hz):
- * **RX**: 40M
- * **TX**: 40M
+
+* **RX**: 40M
+* **TX**: 40M
+
+Sensors:
+
+* **lo_locked**: boolean for LO lock state
 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 TVRX
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The TVRX board has 1 real-mode subdevice.
+It is operated at a low IF.
+
 Receive Antennas: RX
 
 Receive Gains:
- * **RF**, Range: -13.3-50.3dB (frequency-dependent)
- * **IF**, Range: -1.5-32.5dB
+
+* **RF**, Range: -13.3-50.3dB (frequency-dependent)
+* **IF**, Range: -1.5-32.5dB
 
 Bandwidth: 6MHz
 
diff --git a/host/docs/usrp_e1xx.rst b/host/docs/usrp_e1xx.rst
index fb5848bad..2818a0a65 100644
--- a/host/docs/usrp_e1xx.rst
+++ b/host/docs/usrp_e1xx.rst
@@ -63,3 +63,41 @@ Run the following commands to restore the clock generator to a usable state:
 
     cd <install-path>/share/uhd/usrp_e_utilities
     ./usrp-e-utility --fpga=../images/usrp_e100_pt_fpga.bin --reclk
+
+
+------------------------------------------------------------------------
+Clock Synchronization
+------------------------------------------------------------------------
+
+
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Ref Clock - 10MHz
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The E1xx has a 10MHz TCXO which can be used to discipline the flexible clocking by 
+selecting REF_INT for the clock_config_t.
+
+Alternately, an external 10MHz reference clock can be supplied by soldering a connector.
+
+* Connector J10 (REF_IN) needs MCX connector WM5541-ND or similar
+* Square wave will offer the best phase noise performance, but sinusoid is acceptable
+* Power level: 0 to 15dBm
+* Select REF_SMA in clock_config_t
+
+
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+PPS - Pulse Per Second
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+An exteral PPS signal for timestamp synchronization can be supplied by soldering a connector.
+
+* Connector J13 (PPS) needs MCX connector WM5541-ND or similar
+* Requires a square wave signal
+* Amplitude: 3.3 to 5Vpp
+
+Test the PPS input with the following app:
+
+* <args> are device address arguments (optional if only one USRP is on your machine)
+
+::
+
+    cd <install-path>/share/uhd/examples
+    ./test_pps_input --args=<args>
diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt
index 8ca7c7dca..618e33608 100644
--- a/host/lib/CMakeLists.txt
+++ b/host/lib/CMakeLists.txt
@@ -81,19 +81,9 @@ INCLUDE_SUBDIRECTORY(utils)
 ########################################################################
 # Setup compiled-in constants for data directories
 ########################################################################
-FILE(TO_NATIVE_PATH ${CMAKE_INSTALL_PREFIX}/${PKG_DATA_DIR} LOCAL_PKG_DATA_DIR)
-STRING(REPLACE "\\" "\\\\" LOCAL_PKG_DATA_DIR ${LOCAL_PKG_DATA_DIR})
-MESSAGE(STATUS "Local package data directory: ${LOCAL_PKG_DATA_DIR}")
-
-IF(UNIX)
-    #on unix systems, installers will use this directory for the package data
-    FILE(TO_NATIVE_PATH /usr/${PKG_DATA_DIR} INSTALLER_PKG_DATA_DIR)
-ELSE()
-    #for the NSIS installer, this will be the default path for package data
-    FILE(TO_NATIVE_PATH "${CMAKE_INSTALL_PREFIX}/${PKG_DATA_DIR}" INSTALLER_PKG_DATA_DIR)
-ENDIF()
-STRING(REPLACE "\\" "\\\\" INSTALLER_PKG_DATA_DIR ${INSTALLER_PKG_DATA_DIR})
-MESSAGE(STATUS "Installer package data directory: ${INSTALLER_PKG_DATA_DIR}")
+FILE(TO_NATIVE_PATH ${CMAKE_INSTALL_PREFIX}/${PKG_DATA_DIR} UHD_PKG_DATA_PATH)
+STRING(REPLACE "\\" "\\\\" UHD_PKG_DATA_PATH ${UHD_PKG_DATA_PATH})
+MESSAGE(STATUS "Full package data directory: ${UHD_PKG_DATA_PATH}")
 
 CONFIGURE_FILE(
     ${CMAKE_CURRENT_SOURCE_DIR}/constants.hpp.in
diff --git a/host/lib/constants.hpp.in b/host/lib/constants.hpp.in
index d62dda1cb..2e0495b12 100644
--- a/host/lib/constants.hpp.in
+++ b/host/lib/constants.hpp.in
@@ -20,7 +20,6 @@
 
 //these should be pre-processor macros to avoid static initialization issues
 #define UHD_VERSION_STRING "@UHD_VERSION@-@UHD_BUILD_INFO@"
-#define LOCAL_PKG_DATA_DIR "@LOCAL_PKG_DATA_DIR@"
-#define INSTALLER_PKG_DATA_DIR "@INSTALLER_PKG_DATA_DIR@"
+#define UHD_PKG_DATA_PATH "@UHD_PKG_DATA_PATH@"
 
 #endif /* INCLUDED_LIBUHD_CONSTANTS_HPP */
diff --git a/host/lib/usrp/dboard/db_rfx.cpp b/host/lib/usrp/dboard/db_rfx.cpp
index 725b5cc03..f938c749a 100644
--- a/host/lib/usrp/dboard/db_rfx.cpp
+++ b/host/lib/usrp/dboard/db_rfx.cpp
@@ -312,7 +312,8 @@ double rfx_xcvr::set_lo_freq(
         (8, adf4360_regs_t::BAND_SELECT_CLOCK_DIV_8)
     ;
 
-    double actual_freq=0, ref_freq = this->get_iface()->get_clock_rate(unit);
+    std::vector<double> clock_rates = this->get_iface()->get_clock_rates(unit);
+    double actual_freq = 0, ref_freq = 0;
     int R=0, BS=0, P=0, B=0, A=0;
 
     /*
@@ -325,27 +326,31 @@ double rfx_xcvr::set_lo_freq(
      * fvco = [P*B + A] * fref/R
      * fvco*R/fref = P*B + A = N
      */
-    for(R = 2; R <= 32; R+=2){
-        BOOST_FOREACH(BS, bandsel_to_enum.keys()){
-            if (ref_freq/R/BS > 1e6) continue; //constraint on band select clock
-            BOOST_FOREACH(P, prescaler_to_enum.keys()){
-                //calculate B and A from N
-                double N = target_freq*R/ref_freq;
-                B = int(std::floor(N/P));
-                A = boost::math::iround(N - P*B);
-                if (B < A or B > 8191 or B < 3 or A > 31) continue; //constraints on A, B
-                //calculate the actual frequency
-                actual_freq = double(P*B + A)*ref_freq/R;
-                if (actual_freq/P > 300e6) continue; //constraint on prescaler output
-                //constraints met: exit loop
-                goto done_loop;
+    for(R = 1; R <= 32; R+=((R==1)?1:2)){
+        BOOST_FOREACH(ref_freq, uhd::reversed(uhd::sorted(clock_rates))){
+            BOOST_FOREACH(BS, bandsel_to_enum.keys()){
+                if (ref_freq/R/BS > 1e6) continue; //constraint on band select clock
+                BOOST_FOREACH(P, prescaler_to_enum.keys()){
+                    //calculate B and A from N
+                    double N = target_freq*R/ref_freq;
+                    B = int(std::floor(N/P));
+                    A = boost::math::iround(N - P*B);
+                    if (B < A or B > 8191 or B < 3 or A > 31) continue; //constraints on A, B
+                    //calculate the actual frequency
+                    actual_freq = double(P*B + A)*ref_freq/R;
+                    if (actual_freq/P > 300e6) continue; //constraint on prescaler output
+                    //constraints met: exit loop
+                    goto done_loop;
+                }
             }
         }
     } done_loop:
 
     if (rfx_debug) std::cerr << boost::format(
-        "RFX tune: R=%d, BS=%d, P=%d, B=%d, A=%d, DIV2=%d"
-    ) % R % BS % P % B % A % int(_div2[unit] && (!is_rx_rfx400)) << std::endl;
+        "RFX tune: R=%d, BS=%d, P=%d, B=%d, A=%d, DIV2=%d, ref=%fMHz"
+    ) % R % BS % P % B % A % int(_div2[unit] && (!is_rx_rfx400)) % (ref_freq/1e6) << std::endl;
+
+    this->get_iface()->set_clock_rate(unit, ref_freq);
 
     //load the register values
     adf4360_regs_t regs;
diff --git a/host/lib/usrp/dboard/db_xcvr2450.cpp b/host/lib/usrp/dboard/db_xcvr2450.cpp
index 9d25b30a5..70b0bbabd 100644
--- a/host/lib/usrp/dboard/db_xcvr2450.cpp
+++ b/host/lib/usrp/dboard/db_xcvr2450.cpp
@@ -152,12 +152,21 @@ private:
      * \return the rssi in dB
      */
     double get_rssi(void){
+        //*FIXME* RSSI depends on LNA Gain Setting (datasheet pg 16 top middle chart)
+        double max_power;
+        switch(_max2829_regs.rx_lna_gain){
+        case 0:
+        case 1: max_power = 0;    break;
+        case 2: max_power = -15;   break;
+        case 3: max_power = -30.5; break;
+        }
+
         //constants for the rssi calculation
         static const double min_v = 0.5, max_v = 2.5;
         static const double rssi_dyn_range = 60;
         //calculate the rssi from the voltage
         double voltage = this->get_iface()->read_aux_adc(dboard_iface::UNIT_RX, dboard_iface::AUX_ADC_B);
-        return rssi_dyn_range*(voltage - min_v)/(max_v - min_v);
+        return max_power - rssi_dyn_range*(voltage - min_v)/(max_v - min_v);
     }
 };
 
@@ -621,7 +630,7 @@ void xcvr2450::rx_get(const wax::obj &key_, wax::obj &val){
         if (key.name == "lo_locked")
             val = sensor_value_t("LO", this->get_locked(), "locked", "unlocked");
         else if (key.name == "rssi")
-            val = sensor_value_t("RSSI", this->get_rssi(), "dB");
+            val = sensor_value_t("RSSI", this->get_rssi(), "dBm");
         else
             UHD_THROW_INVALID_CODE_PATH();
         return;
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
index b0bf20b67..1ac2b804c 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
@@ -287,6 +287,9 @@ public:
         if (_out_rate == rate) return;
         if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate);
         else                 set_clock_settings_with_internal_vco(rate);
+        //clock rate changed! update dboard clocks and FPGA ticks per second
+        set_rx_dboard_clock_rate(rate);
+        set_tx_dboard_clock_rate(rate);
         _iface->poke32(UE_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate()));
     }
 
@@ -328,6 +331,7 @@ public:
 
     void set_rx_dboard_clock_rate(double rate){
         assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate");
+        _rx_clock_rate = rate;
         size_t divider = size_t(this->_chan_rate/rate);
         //set the divider registers
         set_clock_divider(divider,
@@ -340,6 +344,10 @@ public:
         this->latch_regs();
     }
 
+    double get_rx_clock_rate(void){
+        return _rx_clock_rate;
+    }
+
     /***********************************************************************
      * TX Dboard Clock Control (output 6, divider 2)
      **********************************************************************/
@@ -358,6 +366,7 @@ public:
 
     void set_tx_dboard_clock_rate(double rate){
         assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate");
+        _tx_clock_rate = rate;
         size_t divider = size_t(this->_chan_rate/rate);
         //set the divider registers
         set_clock_divider(divider,
@@ -369,7 +378,11 @@ public:
         this->send_reg(0x197);
         this->latch_regs();
     }
-    
+
+    double get_tx_clock_rate(void){
+        return _tx_clock_rate;
+    }
+
     /***********************************************************************
      * Clock reference control
      **********************************************************************/
@@ -401,6 +414,7 @@ private:
     ad9522_regs_t _ad9522_regs;
     double _out_rate; //rate at the fpga and codec
     double _chan_rate; //rate before final dividers
+    double _rx_clock_rate, _tx_clock_rate;
 
     void latch_regs(void){
         _ad9522_regs.io_update = 1;
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
index 623fbc73b..507f914f3 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
@@ -79,6 +79,18 @@ public:
     virtual void set_tx_dboard_clock_rate(double rate) = 0;
 
     /*!
+     * Get the current rx dboard clock rate.
+     * \return the clock rate in Hz
+     */
+    virtual double get_rx_clock_rate(void) = 0;
+
+    /*!
+     * Get the current tx dboard clock rate.
+     * \return the clock rate in Hz
+     */
+    virtual double get_tx_clock_rate(void) = 0;
+
+    /*!
      * Enable/disable the rx dboard clock.
      * \param enb true to enable
      */
diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/usrp_e100/dboard_iface.cpp
index 4ee354486..61b5a1c92 100644
--- a/host/lib/usrp/usrp_e100/dboard_iface.cpp
+++ b/host/lib/usrp/usrp_e100/dboard_iface.cpp
@@ -97,7 +97,6 @@ private:
     usrp_e100_iface::sptr _iface;
     usrp_e100_clock_ctrl::sptr _clock;
     usrp_e100_codec_ctrl::sptr _codec;
-    uhd::dict<unit_t, double> _clock_rates;
 };
 
 /***********************************************************************
@@ -115,7 +114,6 @@ dboard_iface::sptr make_usrp_e100_dboard_iface(
  * Clock Rates
  **********************************************************************/
 void usrp_e100_dboard_iface::set_clock_rate(unit_t unit, double rate){
-    _clock_rates[unit] = rate;
     switch(unit){
     case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate);
     case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate);
@@ -131,7 +129,11 @@ std::vector<double> usrp_e100_dboard_iface::get_clock_rates(unit_t unit){
 }
 
 double usrp_e100_dboard_iface::get_clock_rate(unit_t unit){
-    return _clock_rates[unit];
+    switch(unit){
+    case UNIT_RX: return _clock->get_rx_clock_rate();
+    case UNIT_TX: return _clock->get_tx_clock_rate();
+    }
+    UHD_THROW_INVALID_CODE_PATH();
 }
 
 void usrp_e100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){
diff --git a/host/lib/utils/paths.cpp b/host/lib/utils/paths.cpp
index 329695873..0ddc80d6e 100644
--- a/host/lib/utils/paths.cpp
+++ b/host/lib/utils/paths.cpp
@@ -76,16 +76,12 @@ static std::vector<fs::path> get_env_paths(const std::string &var_name){
  **********************************************************************/
 std::vector<fs::path> get_image_paths(void){
     std::vector<fs::path> paths = get_env_paths("UHD_IMAGE_PATH");
-    paths.push_back(fs::path(LOCAL_PKG_DATA_DIR) / "images");
-    if (not std::string(INSTALLER_PKG_DATA_DIR).empty())
-        paths.push_back(fs::path(INSTALLER_PKG_DATA_DIR) / "images");
+    paths.push_back(fs::path(UHD_PKG_DATA_PATH) / "images");
     return paths;
 }
 
 std::vector<fs::path> get_module_paths(void){
     std::vector<fs::path> paths = get_env_paths("UHD_MODULE_PATH");
-    paths.push_back(fs::path(LOCAL_PKG_DATA_DIR) / "modules");
-    if (not std::string(INSTALLER_PKG_DATA_DIR).empty())
-        paths.push_back(fs::path(INSTALLER_PKG_DATA_DIR) / "modules");
+    paths.push_back(fs::path(UHD_PKG_DATA_PATH) / "modules");
     return paths;
 }
diff --git a/host/lib/utils/thread_priority.cpp b/host/lib/utils/thread_priority.cpp
index bd34055e8..a63bdf5ce 100644
--- a/host/lib/utils/thread_priority.cpp
+++ b/host/lib/utils/thread_priority.cpp
@@ -27,18 +27,17 @@ bool uhd::set_thread_priority_safe(float priority, bool realtime){
         return true;
     }catch(const std::exception &e){
         uhd::warning::post(str(boost::format(
+            "Unable to set the thread priority. Performance may be negatively affected.\n"
+            "Please see the general application notes in the manual for instructions.\n"
             "%s\n"
-            "Failed to set thread priority %d (%s):\n"
-            "Performance may be negatively affected.\n"
-            "See the general application notes.\n"
-        ) % e.what() % priority % (realtime?"realtime":"")));
+        ) % e.what()));
         return false;
     }
 }
 
 static void check_priority_range(float priority){
     if (priority > +1.0 or priority < -1.0)
-        throw std::range_error("priority out of range [-1.0, +1.0]");
+        throw uhd::value_error("priority out of range [-1.0, +1.0]");
 }
 
 /***********************************************************************