diff options
| -rw-r--r-- | usrp2/top/safe_u1e/.gitignore | 2 | ||||
| -rw-r--r-- | usrp2/top/safe_u1e/Makefile | 2 | ||||
| -rw-r--r-- | usrp2/top/safe_u1e/safe_u1e.ucf | 228 | ||||
| -rw-r--r-- | usrp2/top/safe_u1e/safe_u1e.v | 350 |
4 files changed, 237 insertions, 345 deletions
diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore new file mode 100644 index 000000000..bdc5af040 --- /dev/null +++ b/usrp2/top/safe_u1e/.gitignore @@ -0,0 +1,2 @@ +*~ +build diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile index 8fe77d554..664835187 100644 --- a/usrp2/top/safe_u1e/Makefile +++ b/usrp2/top/safe_u1e/Makefile @@ -175,7 +175,7 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ top/u2_core/u2_core.v \ -top/safe_u1e/u1e.ucf \ +top/safe_u1e/safe_u1e.ucf \ top/safe_u1e/safe_u1e.v ################################################## diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf new file mode 100644 index 000000000..83dbeca54 --- /dev/null +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -0,0 +1,228 @@ +#NET "EM_CLK" LOC = "F11" ; +#NET "overo_gpio23" LOC = "B3" ; +#NET "overo_gpio22" LOC = "A3" ; +#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio14" LOC = "C4" ; +#NET "overo_gpio176" LOC = "B4" ; +#NET "overo_gpio64" LOC = "A4" ; +#NET "overo_gpio65" LOC = "F8" ; +#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio145" LOC = "C7" ; +#NET "overo_gpio163" LOC = "D7" ; +#NET "overo_gpio146" LOC = "A6" ; +#NET "overo_gpio144" LOC = "A5" ; +#NET "overo_gpio147" LOC = "B6" ; +#NET "overo_gpio128" LOC = "G8" ; +#NET "overo_gpio0" LOC = "F9" ; +#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; +#NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NWP" LOC = "F13" ; +#NET "EM_NBE1" LOC = "D14" ; +#NET "EM_NBE0" LOC = "A13" ; +#NET "EM_NWE" LOC = "B13" ; +#NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_D15" LOC = "D13" ; +#NET "EM_D14" LOC = "D15" ; +#NET "EM_D13" LOC = "C16" ; +#NET "EM_D12" LOC = "B20" ; +#NET "EM_D11" LOC = "A19" ; +#NET "EM_D10" LOC = "A17" ; +#NET "EM_D9" LOC = "E15" ; +#NET "EM_D8" LOC = "F15" ; +#NET "EM_D7" LOC = "E16" ; +#NET "EM_D6" LOC = "F16" ; +#NET "EM_D5" LOC = "B17" ; +#NET "EM_D4" LOC = "C17" ; +#NET "EM_D3" LOC = "B19" ; +#NET "EM_D2" LOC = "D19" ; +#NET "EM_D1" LOC = "C19" ; +#NET "EM_D0" LOC = "A20" ; +#NET "SYSEN" LOC = "C11" ; +#NET "EM_NCS6" LOC = "E17" ; +#NET "EM_NCS5" LOC = "E10" ; +#NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; +#NET "EM_A10" LOC = "C14" ; +#NET "EM_A9" LOC = "C10" ; +#NET "EM_A8" LOC = "C5" ; +#NET "EM_A7" LOC = "A18" ; +#NET "EM_A6" LOC = "A15" ; +#NET "EM_A5" LOC = "A12" ; +#NET "EM_A4" LOC = "A10" ; +#NET "EM_A3" LOC = "E7" ; +#NET "EM_A2" LOC = "A7" ; +#NET "EM_A1" LOC = "C15" ; +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; +#NET "cgen_miso" LOC = "U2" ; +#NET "cgen_mosi" LOC = "V1" ; +#NET "cgen_sclk" LOC = "R5" ; +#NET "cgen_sen_b" LOC = "T1" ; +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; +#NET "debug_00" LOC = "P6" ; +#NET "debug_01" LOC = "R6" ; +#NET "debug_02" LOC = "P1" ; +#NET "debug_03" LOC = "P2" ; +#NET "debug_04" LOC = "N6" ; +#NET "debug_05" LOC = "N5" ; +#NET "debug_06" LOC = "N1" ; +#NET "debug_07" LOC = "K2" ; +#NET "debug_08" LOC = "K3" ; +#NET "debug_09" LOC = "K6" ; +#NET "debug_10" LOC = "L5" ; +#NET "debug_11" LOC = "H2" ; +#NET "debug_12" LOC = "K4" ; +#NET "debug_13" LOC = "K5" ; +#NET "debug_14" LOC = "G1" ; +#NET "debug_15" LOC = "H1" ; +#NET "debug_16" LOC = "H5" ; +#NET "debug_17" LOC = "H6" ; +#NET "debug_18" LOC = "E3" ; +#NET "debug_19" LOC = "E4" ; +#NET "debug_20" LOC = "G5" ; +#NET "debug_21" LOC = "G6" ; +#NET "debug_22" LOC = "F2" ; +#NET "debug_23" LOC = "F1" ; +#NET "debug_24" LOC = "H3" ; +#NET "debug_25" LOC = "H4" ; +#NET "debug_26" LOC = "F4" ; +#NET "debug_27" LOC = "F5" ; +#NET "debug_28" LOC = "C2" ; +#NET "debug_29" LOC = "C1" ; +#NET "debug_30" LOC = "F3" ; +#NET "debug_31" LOC = "G3" ; +#NET "debug_pb2" LOC = "Y2" ; +#NET "debug_pb1" LOC = "AA1" ; +#NET "debug_pb0" LOC = "N3" ; +#NET "dip_sw_7" LOC = "T3" ; +#NET "dip_sw_6" LOC = "U3" ; +#NET "dip_sw_5" LOC = "M3" ; +#NET "dip_sw_4" LOC = "N4" ; +#NET "dip_sw_3" LOC = "J3" ; +#NET "dip_sw_2" LOC = "J4" ; +#NET "dip_sw_1" LOC = "J6" ; +#NET "dip_sw_0" LOC = "J7" ; +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; +#NET "debug_clk0" LOC = "L6" ; +#NET "debug_clk1" LOC = "M5" ; +#NET "unnamed_net37" LOC = "B1" ; +#NET "unnamed_net36" LOC = "B22" ; +#NET "unnamed_net35" LOC = "D2" ; +#NET "unnamed_net34" LOC = "A21" ; +#NET "GND" LOC = "V19" ; +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "unnamed_net45" LOC = "F7" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; +#NET "unnamed_net44" LOC = "V6" ; +#NET "unnamed_net43" LOC = "AA3" ; +#NET "unnamed_net42" LOC = "AB3" ; +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +#NET "reset_codec" LOC = "D22" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; +#NET "RXSYNC" LOC = "F22" ; +#NET "DB11" LOC = "E22" ; +#NET "DB10" LOC = "J19" ; +#NET "DB09" LOC = "H20" ; +#NET "DB08" LOC = "G19" ; +#NET "DB07" LOC = "F20" ; +#NET "DB06" LOC = "K16" ; +#NET "DB05" LOC = "J17" ; +#NET "DB04" LOC = "H22" ; +#NET "DB03" LOC = "G22" ; +#NET "DB02" LOC = "H17" ; +#NET "DB01" LOC = "H18" ; +#NET "DB00" LOC = "K20" ; +#NET "DA11" LOC = "J20" ; +#NET "DA10" LOC = "K19" ; +#NET "DA09" LOC = "K18" ; +#NET "DA08" LOC = "L22" ; +#NET "DA07" LOC = "K22" ; +#NET "DA06" LOC = "N22" ; +#NET "DA05" LOC = "M22" ; +#NET "DA04" LOC = "N20" ; +#NET "DA03" LOC = "N19" ; +#NET "DA02" LOC = "R22" ; +#NET "DA01" LOC = "P22" ; +#NET "DA00" LOC = "N17" ; +#NET "TX13" LOC = "P19" ; +#NET "TX12" LOC = "R18" ; +#NET "TX11" LOC = "U20" ; +#NET "TX10" LOC = "T20" ; +#NET "TX09" LOC = "R19" ; +#NET "TX08" LOC = "R20" ; +#NET "TX07" LOC = "W22" ; +#NET "TX06" LOC = "Y22" ; +#NET "TX05" LOC = "T18" ; +#NET "TX04" LOC = "T17" ; +#NET "TX03" LOC = "W19" ; +#NET "TX02" LOC = "V20" ; +#NET "TX01" LOC = "Y21" ; +#NET "TX00" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; +#NET "PPS_IN" LOC = "M17" ; +#NET "io_tx_00" LOC = "AB20" ; +#NET "io_tx_01" LOC = "Y17" ; +#NET "io_tx_02" LOC = "Y16" ; +#NET "io_tx_03" LOC = "U16" ; +#NET "io_tx_04" LOC = "V16" ; +#NET "io_tx_05" LOC = "AB19" ; +#NET "io_tx_06" LOC = "AA19" ; +#NET "io_tx_07" LOC = "U14" ; +#NET "io_tx_08" LOC = "U15" ; +#NET "io_tx_09" LOC = "AB17" ; +#NET "io_tx_10" LOC = "AB18" ; +#NET "io_tx_11" LOC = "Y13" ; +#NET "io_tx_12" LOC = "W14" ; +#NET "io_tx_13" LOC = "U13" ; +#NET "io_tx_14" LOC = "AA15" ; +#NET "io_tx_15" LOC = "AB14" ; +#NET "io_rx_00" LOC = "Y8" ; +#NET "io_rx_01" LOC = "Y9" ; +#NET "io_rx_02" LOC = "V7" ; +#NET "io_rx_03" LOC = "U8" ; +#NET "io_rx_04" LOC = "V10" ; +#NET "io_rx_05" LOC = "U9" ; +#NET "io_rx_06" LOC = "AB7" ; +#NET "io_rx_07" LOC = "AA8" ; +#NET "io_rx_08" LOC = "W8" ; +#NET "io_rx_09" LOC = "V8" ; +#NET "io_rx_10" LOC = "AB5" ; +#NET "io_rx_11" LOC = "AB6" ; +#NET "io_rx_12" LOC = "AB4" ; +#NET "io_rx_13" LOC = "AA4" ; +#NET "io_rx_14" LOC = "W5" ; +#NET "io_rx_15" LOC = "Y4" ; +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; +NET "debug_led<2>" LOC = "T5" ; +NET "debug_led<1>" LOC = "R2" ; +NET "debug_led<0>" LOC = "R1" ; diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index c880a9e55..79aaac6cd 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -4,131 +4,14 @@ module safe_u1e ( input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - //input ADC_clkout_p, //input ADC_clkout_n, - //input ADCA_12_p, //input ADCA_12_n, - //input ADCA_10_p, //input ADCA_10_n, - //input ADCA_8_p, //input ADCA_8_n, - //input ADCA_6_p, //input ADCA_6_n, - //input ADCA_4_p, //input ADCA_4_n, - //input ADCA_2_p, //input ADCA_2_n, - //input ADCA_0_p, //input ADCA_0_n, - //input ADCB_12_p, //input ADCB_12_n, - //input ADCB_10_p, //input ADCB_10_n, - //input ADCB_8_p, //input ADCB_8_n, - //input ADCB_6_p, //input ADCB_6_n, - //input ADCB_4_p, //input ADCB_4_n, - //input ADCB_2_p, //input ADCB_2_n, - //input ADCB_0_p, //input ADCB_0_n, - - // DAC - //output [15:0] DACA, - //output [15:0] DACB, - //input DAC_LOCK, // unused for now - - // DB IO Pins - //inout [15:0] io_tx, - //inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - //input FPGA_RESET, - //output [1:0] debug_clk, - //output [31:0] debug, - //output [3:1] TXD, //input [3:1] RXD, // UARTs - ////input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - //output [1:0] clk_en, - //output [1:0] clk_sel, - //input CLK_FUNC, // FIXME is an //input to control the 9510 - //input CLK_STATUS, - - //inout SCL, //inout SDA, // I2C - - // PPS - //input PPS_IN, //input PPS2_IN, - - // SPI - //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, - //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, - //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, - //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, - //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, - //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, - //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, - //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, - //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, - - // GigE PHY - //input CLK_TO_MAC, - - //output reg [7:0] GMII_TXD, - //output reg GMII_TX_EN, - //output reg GMII_TX_ER, - //output GMII_GTX_CLK, - //input GMII_TX_CLK, // 100mbps clk - - //input GMII_RX_CLK, - //input [7:0] GMII_RXD, - //input GMII_RX_DV, - //input GMII_RX_ER, - //input GMII_COL, - //input GMII_CRS, - - //input PHY_INTn, // open drain - //inout MDIO, - //output MDC, - //output PHY_RESETn, - output ETH_LED - - //input POR, - - // Expansion - //input exp_time_in_p, //input exp_time_in_n, // Diff - //output exp_time_out_p, //output exp_time_out_n, // Diff - //input exp_user_in_p, //input exp_user_in_n, // Diff - //output exp_user_out_p, //output exp_user_out_n, // Diff - - // SERDES - //output ser_enable, - //output ser_prbsen, - //output ser_loopen, - //output ser_rx_en, - - //output ser_tx_clk, - //output reg [15:0] ser_t, - //output reg ser_tklsb, - //output reg ser_tkmsb, - - //input ser_rx_clk, - //input [15:0] ser_r, - //input ser_rklsb, - //input ser_rkmsb, - - // SRAM - //inout [35:0] RAM_D, - //output [20:0] RAM_A, - //output [3:0] RAM_BWn, - //output RAM_ZZ, - //output RAM_LDn, - //output RAM_OEn, - //output RAM_WEn, - //output RAM_CENn, - //output RAM_CLK, - - // SPI Flash - //output flash_cs, - //output flash_clk, - //output flash_mosi, - //input flash_miso + output [2:0] debug_led ); // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + wire clk_fpga; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; reg [31:0] ctr; @@ -136,227 +19,6 @@ module safe_u1e always @(posedge clk_fpga) ctr <= ctr + 1; - assign {leds,ETH_LED} = ~ctr[29:24]; - - -/* - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire dcm_rst = 0; - - wire [13:0] adc_a, adc_b; - - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a,adc_b})); - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; + assign debug_led = ctr[27:25]; - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - u2_core u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_time_in), - .exp_pps_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (DACA[15:0]), - .dac_b (DACB[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); -*/ endmodule // safe_u2plus |