diff options
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 5 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_deframer.v | 11 | 
2 files changed, 11 insertions, 5 deletions
| diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index bcdbea820..662cdca62 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -26,16 +26,17 @@ module vita_tx_chain     wire 		error;     wire [31:0] 		error_code; +   wire 		clear_seqnum;     assign underrun = error;     assign message = error_code;     setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid       (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), -      .in(set_data),.out(streamid),.changed()); +      .in(set_data),.out(streamid),.changed(clear_seqnum));     vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer -     (.clk(clk), .reset(reset), .clear(clear_vita), +     (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum),        .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),        .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),        .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 58878790d..f9cd7d00d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -2,7 +2,7 @@  module vita_tx_deframer    #(parameter BASE=0,      parameter MAXCHAN=1) -   (input clk, input reset, input clear, +   (input clk, input reset, input clear, input clear_seqnum,      input set_stb, input [7:0] set_addr, input [31:0] set_data,      // To FIFO interface of Buffer Pool @@ -69,13 +69,19 @@ module vita_tx_deframer     wire        fifo_space;     always @(posedge clk) +     if(reset | clear_seqnum) +       seqnum_reg <= 4'hF; +     else +       if((vita_state==VITA_HEADER) & src_rdy_i) +	 seqnum_reg <= seqnum; +    +   always @(posedge clk)       if(reset | clear)         begin  	  vita_state 		<= VITA_HEADER;  	  {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg}   	    <= 0;  	  seqnum_err <= 0; -	  seqnum_reg <= 0;         end       else          if((vita_state == VITA_STORE) & fifo_space) @@ -107,7 +113,6 @@ module vita_tx_deframer  		  vita_state <= VITA_TICS;  		else  		  vita_state <= VITA_PAYLOAD; -		seqnum_reg <= seqnum;  		seqnum_err <= ~(seqnum == next_seqnum);  	     end // case: VITA_HEADER  	   VITA_STREAMID : | 
