diff options
| -rw-r--r-- | fpga/usrp3/lib/fifo/axi_packet_gate.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/fifo/axi_packet_gate.v b/fpga/usrp3/lib/fifo/axi_packet_gate.v index 771fb2200..c0037e80f 100644 --- a/fpga/usrp3/lib/fifo/axi_packet_gate.v +++ b/fpga/usrp3/lib/fifo/axi_packet_gate.v @@ -70,7 +70,7 @@ module axi_packet_gate #( .clka (clk), .ena(1'b1), .wea(wr_en), .addra(wr_addr), .dia(wr_data), .doa(), .clkb (clk), .enb(rd_en), .web(1'b0), - .addrb(rd_addr), .dib({WIDTH{1'b0}}), .dob(rd_data) + .addrb(rd_addr), .dib({WIDTH+1{1'b0}}), .dob(rd_data) ); // FIFO empty/full logic. The condition for both |