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-rw-r--r--host/lib/usrp/dboard/rhodium/rhodium_radio_ctrl_init.cpp9
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/adc_rh.py2
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/rh_periphs.py6
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/rhodium.py9
4 files changed, 14 insertions, 12 deletions
diff --git a/host/lib/usrp/dboard/rhodium/rhodium_radio_ctrl_init.cpp b/host/lib/usrp/dboard/rhodium/rhodium_radio_ctrl_init.cpp
index a4b2cd17a..9cf7c57e6 100644
--- a/host/lib/usrp/dboard/rhodium/rhodium_radio_ctrl_init.cpp
+++ b/host/lib/usrp/dboard/rhodium/rhodium_radio_ctrl_init.cpp
@@ -39,6 +39,7 @@ namespace {
constexpr char RHODIUM_DEFAULT_RX_ANTENNA[] = "RX2";
constexpr char RHODIUM_DEFAULT_TX_ANTENNA[] = "TX/RX";
constexpr double RHODIUM_DEFAULT_BANDWIDTH = 250e6; // Hz
+ constexpr auto RHODIUM_DEFAULT_MASH_ORDER = lmx2592_iface::mash_order_t::THIRD;
//! Rhodium gain profile options
const std::vector<std::string> RHODIUM_GP_OPTIONS = {
@@ -193,7 +194,7 @@ void rhodium_radio_ctrl_impl::_init_peripherals()
UHD_LOG_TRACE(unique_id(), "Writing initial TX LO state...");
_tx_lo->set_reference_frequency(RHODIUM_LO1_REF_FREQ);
- _tx_lo->set_mash_order(lmx2592_iface::mash_order_t::THIRD);
+ _tx_lo->set_mash_order(RHODIUM_DEFAULT_MASH_ORDER);
UHD_LOG_TRACE(unique_id(), "Initializing RX LO...");
_rx_lo = lmx2592_iface::make(
@@ -202,7 +203,7 @@ void rhodium_radio_ctrl_impl::_init_peripherals()
UHD_LOG_TRACE(unique_id(), "Writing initial RX LO state...");
_rx_lo->set_reference_frequency(RHODIUM_LO1_REF_FREQ);
- _rx_lo->set_mash_order(lmx2592_iface::mash_order_t::THIRD);
+ _rx_lo->set_mash_order(RHODIUM_DEFAULT_MASH_ORDER);
UHD_LOG_TRACE(unique_id(), "Initializing GPIOs...");
_gpio =
@@ -357,7 +358,7 @@ void rhodium_radio_ctrl_impl::_init_frontend_subtree(
})
;
subtree->create<meta_range_t>(tx_fe_path / "bandwidth" / "range")
- .set(meta_range_t(0.0, 0.0, 0.0)) // FIXME
+ .set(meta_range_t(RHODIUM_DEFAULT_BANDWIDTH, RHODIUM_DEFAULT_BANDWIDTH))
.add_coerced_subscriber([](const meta_range_t &){
throw uhd::runtime_error(
"Attempting to update bandwidth range!");
@@ -373,7 +374,7 @@ void rhodium_radio_ctrl_impl::_init_frontend_subtree(
})
;
subtree->create<meta_range_t>(rx_fe_path / "bandwidth" / "range")
- .set(meta_range_t(0.0, 0.0, 0.0)) // FIXME
+ .set(meta_range_t(RHODIUM_DEFAULT_BANDWIDTH, RHODIUM_DEFAULT_BANDWIDTH))
.add_coerced_subscriber([](const meta_range_t &){
throw uhd::runtime_error(
"Attempting to update bandwidth range!");
diff --git a/mpm/python/usrp_mpm/dboard_manager/adc_rh.py b/mpm/python/usrp_mpm/dboard_manager/adc_rh.py
index 2befa011f..4ddc65350 100644
--- a/mpm/python/usrp_mpm/dboard_manager/adc_rh.py
+++ b/mpm/python/usrp_mpm/dboard_manager/adc_rh.py
@@ -99,7 +99,7 @@ class AD9695Rh(object):
self.log.trace("Clock status readback: 0x{:X}".format(clock_status))
if clock_status != 0x01:
self.log.error("Input clock not detected")
- raise RuntimeError("Input clock not detected for ADC")
+ raise RuntimeError("Input clock not detected for ADC")
self.log.trace("ADC Configuration.")
self.pokes8((
diff --git a/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py b/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py
index 2d631e509..7df734f06 100644
--- a/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py
+++ b/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py
@@ -91,8 +91,8 @@ class FPGAtoLoDist(object):
raise RuntimeError('LO distribution board revision did not match: Expected: {0} Actual: {1}'.format(self.EXPECTED_BOARD_REV, board_rev))
self._gpios.set(self.pins.index('P6_8V_EN'), 1)
if not poll_with_timeout(
- lambda: bool(self._gpios.get(self.pins.index('P6_8V_PG'))),
- self.POWER_ON_TIMEOUT,
+ lambda: bool(self._gpios.get(self.pins.index('P6_8V_PG'))),
+ self.POWER_ON_TIMEOUT,
self.POWER_ON_POLL_INTERVAL):
self._gpios.set(self.pins.index('P6_8V_EN'), 0)
raise RuntimeError('Power on failure for LO Distribution board')
@@ -201,8 +201,6 @@ class RhCPLD(object):
"""
return (self.peek16(self.REG_DAC_ALARM) & 0x0001)
- # TODO: add more control/status functionality to this class?
-
class DboardClockControl(object):
"""
diff --git a/mpm/python/usrp_mpm/dboard_manager/rhodium.py b/mpm/python/usrp_mpm/dboard_manager/rhodium.py
index 743cf5668..9b9086c20 100644
--- a/mpm/python/usrp_mpm/dboard_manager/rhodium.py
+++ b/mpm/python/usrp_mpm/dboard_manager/rhodium.py
@@ -297,7 +297,6 @@ class Rhodium(BfrfsEEPROM, DboardManagerBase):
self.log.trace("Selected EEPROM offset: %d", user_eeprom_offset)
user_eeprom_data = open(eeprom_path, 'rb').read()[user_eeprom_offset:]
self.log.trace("Total EEPROM size is: %d bytes", len(user_eeprom_data))
- # FIXME verify EEPROM sectors
return BufferFS(
user_eeprom_data,
max_size=eeprom_info.get('max_size'),
@@ -411,6 +410,10 @@ class Rhodium(BfrfsEEPROM, DboardManagerBase):
self._lo_dist.set(pin_info[0], pin_val)
def is_lo_dist_present(self):
+ """
+ Returns true if this daughterboard has a LO distribution board
+ attached and initialized, otherwise false.
+ """
return self._lo_dist is not None
##########################################################################
@@ -500,14 +503,14 @@ class Rhodium(BfrfsEEPROM, DboardManagerBase):
self.log.info("Re-initializing daughter board. This may take some time.")
self._reinit(self.master_clock_rate)
self.log.debug("Daughter board re-initialization done.")
-
+
def enable_tx_lowband_lo(self, enable):
"""
Enables or disables the TX lowband LO output from the LMK on the
daughterboard.
"""
self.lmk.enable_tx_lb_lo(enable);
-
+
def enable_rx_lowband_lo(self, enable):
"""
Enables or disables the RX lowband LO output from the LMK on the