diff options
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e31x.py | 2 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e31x_periphs.py | 14 |
2 files changed, 2 insertions, 14 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e31x.py b/mpm/python/usrp_mpm/periph_manager/e31x.py index e8f775537..355945de4 100644 --- a/mpm/python/usrp_mpm/periph_manager/e31x.py +++ b/mpm/python/usrp_mpm/periph_manager/e31x.py @@ -725,7 +725,7 @@ class e31x(ZynqComponents, PeriphManagerBase): @no_rpc def _update_fpga_type(self): """Update the fpga type stored in the updateable components""" - fpga_type = self.mboard_regs_control.get_fpga_type() + fpga_type = "" # FIXME self.log.debug("Updating mboard FPGA type info to {}".format(fpga_type)) self.updateable_components['fpga']['type'] = fpga_type diff --git a/mpm/python/usrp_mpm/periph_manager/e31x_periphs.py b/mpm/python/usrp_mpm/periph_manager/e31x_periphs.py index 33c90ceb7..bb84ebb3e 100644 --- a/mpm/python/usrp_mpm/periph_manager/e31x_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/e31x_periphs.py @@ -129,14 +129,6 @@ class MboardRegsControl(MboardRegsCommon): self.log.trace("Writing MB_CLOCK_CTRL to 0x{:08X}".format(reg_val)) self.poke32(self.MB_CLOCK_CTRL, reg_val) - def get_fpga_type(self): - """ - Reads the type of the FPGA image currently loaded - Returns a string with the type (SG1, SG3) - """ - #TODO: Add SG1 and SG3? - return "" - def get_refclk_lock(self): """ Check the status of the reference clock in FPGA. @@ -145,11 +137,7 @@ class MboardRegsControl(MboardRegsCommon): with self.regs: reg_val = self.peek32(self.MB_CLOCK_CTRL) locked = (reg_val & mask) > 0 - if not locked: - self.log.warning("Reference Clock reporting unlocked. " - "MB_CLOCK_CTRL reg: 0x{:08X}".format(reg_val)) - else: - self.log.trace("Reference Clock locked!") + self.log.trace("Reference Clock %slocked!", "" if locked else "un") return locked def set_channel_mode(self, channel_mode): |