diff options
34 files changed, 741 insertions, 258 deletions
diff --git a/fpga/usrp3/tools/utils/image_package_mapping.py b/fpga/usrp3/tools/utils/image_package_mapping.py index 1f278b4f2..ca0ca0c7d 100644 --- a/fpga/usrp3/tools/utils/image_package_mapping.py +++ b/fpga/usrp3/tools/utils/image_package_mapping.py @@ -86,10 +86,14 @@ PACKAGE_MAPPING = { "x410_cpld": { "type": "x4xx", "package_name": "x4xx_x410_cpld_default-g{}.zip", - "files": ["usrp_x410_cpld.rpd", - "usrp_x410_cpld.rpd.md5", - "usrp_x410_cpld.svf", - "usrp_x410_cpld.svf.md5"] + "files": ["usrp_x410_cpld_10m04.rpd", + "usrp_x410_cpld_10m04.rpd.md5", + "usrp_x410_cpld_10m04.svf", + "usrp_x410_cpld_10m04.svf.md5", + "usrp_x410_cpld_10m08.rpd", + "usrp_x410_cpld_10m08.rpd.md5", + "usrp_x410_cpld_10m08.svf", + "usrp_x410_cpld_10m08.svf.md5"] }, "zbx_cpld": { "type": "x4xx", diff --git a/fpga/usrp3/top/x400/cpld/Makefile b/fpga/usrp3/top/x400/cpld/Makefile index 68c6c8908..56ae3cd82 100644 --- a/fpga/usrp3/top/x400/cpld/Makefile +++ b/fpga/usrp3/top/x400/cpld/Makefile @@ -4,74 +4,94 @@ # SPDX-License-Identifier: LGPL-3.0-or-later # -GIT_HASH = $(shell ../../../tools/scripts/git-hash.sh) - -build: ip - @echo -ne "\n---- Make: Synthesis ...\n\n"; - @quartus_map mb_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)"; - @echo -ne "\n---- Make: Partition Merge ...\n\n"; - @quartus_cdb mb_cpld --merge=on --incremental_compilation_import - @echo -ne "\n\n---- Make: Implementation ...\n\n"; - @quartus_fit mb_cpld; - @echo -ne "\n\n---- Make: Analyzing timing ...\n\n"; - @quartus_sta mb_cpld; - @# grep for unconstrained path warning - @grep "332102" output_files/mb_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# grep for timing closure critical warning - @grep "332148" output_files/mb_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no warnings - @grep -iw "warning" output_files/mb_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no critical warning except "review power analyzer report file" - @grep -i "critical warning" output_files/* | grep -v 16562; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# PS chip select analysis - @quartus_sta -t scripts/ps_cs_analysis.tcl - @echo -ne "\n\n---- Make: Generating bitfile...\n\n"; - @quartus_asm mb_cpld; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 10.0MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/mb_cpld.pof ./output_files/mb_cpld_isp_on.svf -o background_programming=on; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 10.0MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/mb_cpld.pof ./output_files/mb_cpld_isp_off.svf; - @echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n"; - @quartus_cpf -c raw_conversion.cof - @echo -ne "\n\n---- Make: Copy final files...\n\n"; - @mkdir -p build - @cp output_files/mb_cpld.pof build/usrp_x410_cpld.pof - @cp output_files/mb_cpld_isp_off.svf build/usrp_x410_cpld_isp_off.svf - @cp output_files/mb_cpld_isp_on.svf build/usrp_x410_cpld.svf - @cp output_files/mb_cpld_converted_cfm0_auto.rpd build/usrp_x410_cpld.rpd - @echo -ne "\n\n---- Make: MB CPLD ready!\n"; - @echo -ne " Use build/usrp_x410_cpld.pof via JTAG programmer or\n" - @echo -ne " build/usrp_x410_cpld.svf (ISP on) via PS JTAG-engine (background programming) or\n" - @echo -ne " build/usrp_x410_cpld.rpd via reconfig engine or\n" - @echo -ne " build/usrp_x410_cpld_isp_off.svf via JTAG test points (initial programming)\n" - -clean: - @echo -ne "\nCleaning MB CPLD...\n"; - @git clean -Xdf +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP X410 CPLD Help +##------------------- +##Usage: +## make <Targets> <Options> +## +##Output: +## build/<device-id>/usrp_x410_cpld.pof: Bitstream to use with JTAG programmer +## build/<device-id>/usrp_x410_cpld.svf: Bitstream to use with PS JTAG engine (background programming) +## build/<device-id>/usrp_x410_cpld.rpd: Bitstream to use via reconfig engine +## build/<device-id>/usrp_x410_cpld_isp_off.svf: Bitstream to use with JTAG test points (initial programming) + +# Definitions +10M04_ID = "10M04SAU169I7G" +10M08_ID = "10M08SAU169I7G" + +# Target specific variables +X410_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 +X410_CPLD_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 + +TARGET = bin +TOP ?= mb_cpld + +# quartus_build($1=Device, $2=Definitions) +quartus_build = make -f Makefile.cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" POST_STA_TCL="ps_cs_analysis.tcl" + +# quartus_ip($1=Device, $2=Definitions) +quartus_ip = make -f Makefile.cpld.inc quar_ip NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" + +# post_build($1=Artifact Name) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build/; \ + echo "Exporting bitstream files..."; \ + cp build-$@/output_files/$(TOP).pof build/$(1).pof; \ + cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_isp_off.svf; \ + cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1).svf; \ + cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1).rpd; \ + echo -ne "\n\n---- Make: MB CPLD ready!\n"; \ + echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \ + echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \ + echo -ne " build/$(1).rpd via reconfig engine or\n"; \ + echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n"; +else + post_build = @echo "Skipping bitfile export." +endif -QSYS_PATH=$(subst \,/,$(QSYS_ROOTDIR)) +## +##Supported Targets +##----------------- -ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \ - ip/clkctrl/clkctrl/simulation/clkctrl.v +all: X410_CPLD_10M04 X410_CPLD_10M08 ##(Default target) -ip/flash/on_chip_flash/simulation/on_chip_flash.v: - $(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG +##X410_CPLD_10M04: Motherboard CPLD targeted to 10M04SAU169I7G. +X410_CPLD_10M04: + $(call quartus_build,$(10M04_ID),$(DEFS)) + $(call post_build,"usrp_x410_cpld_`echo $(10M04_ID) | cut -c1-5 | tr A-Z a-z`") + +##X410_CPLD_10M08: Motherboard CPLD targeted to 10M08SAU169I7G. +X410_CPLD_10M08: + $(call quartus_build,$(10M08_ID),$(DEFS)) + $(call post_build,"usrp_x410_cpld_`echo $(10M08_ID) | cut -c1-5 | tr A-Z a-z`") + + +X410_CPLD_IP: ##Build IPs only, needed for simulation. + @# Building only X410_CPLD_10M04 IP + $(call quartus_ip,$(10M04_ID),$(DEFS)) + +clean: ##Clean up all target build outputs. + @echo -ne "\nCleaning targets and git repo...\n"; + @rm -rf build-X410_CPLD* + @rm -rf build + @git clean -Xdf + +cleanall: ##Clean up all target and ip build outputs. + @echo -ne "\nCleaning targets, IP, and git repo...\n"; + @rm -rf build-X410_CPLD* + @rm -rf build + @rm -rf build-ip + @git clean -Xdf -ip/clkctrl/clkctrl/simulation/clkctrl.v: - $(QSYS_PATH)/qsys-generate ip/clkctrl/clkctrl.qsys --simulation=VERILOG +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' -all: build +## +##Supported Options +##----------------- +## .PHONY: all build clean ip diff --git a/fpga/usrp3/top/x400/cpld/Makefile.cpld.inc b/fpga/usrp3/top/x400/cpld/Makefile.cpld.inc new file mode 100644 index 000000000..bc3c6c97c --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/Makefile.cpld.inc @@ -0,0 +1,51 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# Project Setup +################################################## +# TOP_MODULE = <Input arg> +# NAME = <Input arg> +# PART_ID = <Input arg> +# ARCH = <Input arg> + +################################################## +# Include other makefiles +################################################## + +PROJECT_DIR = $(abspath .) +BASE_DIR = $(abspath ../..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/quartus_design_builder.mak + +# Include IP directory +include $(IP_DIR)/Makefile.inc + +# Define VERILOG_DEFS for macros definition +VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF) + +bin: .prereqs + $(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),$(POST_TCL_SCRIPT),1) + @\ + pushd $(BUILD_DIR); \ + echo "Converting bitfile to svf format (ISP enabled)..."; \ + quartus_cpf --convert \ + --frequency 10.0MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_on.svf -o background_programming=on; \ + echo "Converting bitfile to svf format (ISP disabled)..."; \ + quartus_cpf --convert \ + --frequency 10.0MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_off.svf; \ + echo "Converting bitfile to rpd format..."; \ + quartus_cpf -c raw_conversion.cof; \ + popd; + +quar_ip: .prereqs ip + @echo "IP Build DONE ..." diff --git a/fpga/usrp3/top/x400/cpld/ip/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/Makefile.inc new file mode 100644 index 000000000..1d238d83c --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/Makefile.inc @@ -0,0 +1,22 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(IP_DIR)/on_chip_flash/Makefile.inc +include $(IP_DIR)/clkctrl/Makefile.inc + +IP_SRCS = \ +$(IP_ON_CHIP_FLASH_SRCS) \ +$(IP_CLKCTRL_SRCS) + + +IP_OUTPUTS = \ +$(IP_ON_CHIP_FLASH_OUTS) \ +$(IP_CLKCTRL_OUTS) + + +ip: $(IP_OUTPUTS) + +.PHONY: ip diff --git a/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore b/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore index 9776d9b81..87dce88a7 100644 --- a/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore +++ b/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore @@ -1,3 +1,3 @@ # generate files clkctrl/ -clkctrl.sopcinfo
\ No newline at end of file +clkctrl.sopcinfo diff --git a/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc new file mode 100644 index 000000000..2015c6976 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_CLKCTRL_SRCS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.qsys + +IP_CLKCTRL_OUTS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.sopcinfo + +$(IP_CLKCTRL_SRCS) $(IP_CLKCTRL_OUTS) : $(IP_DIR)/clkctrl/clkctrl.qsys + $(call BUILD_QUARTUS_IP,clkctrl,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/cpld/ip/flash/.gitignore b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore index 585bc126d..585bc126d 100644 --- a/fpga/usrp3/top/x400/cpld/ip/flash/.gitignore +++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc new file mode 100644 index 000000000..fcd8528e6 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_ON_CHIP_FLASH_SRCS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.qsys + +IP_ON_CHIP_FLASH_OUTS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.sopcinfo + +$(IP_ON_CHIP_FLASH_SRCS) $(IP_ON_CHIP_FLASH_OUTS) : $(IP_DIR)/on_chip_flash/on_chip_flash.qsys + $(call BUILD_QUARTUS_IP,on_chip_flash,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys index 4cbe8726a..4cbe8726a 100644 --- a/fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys +++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys diff --git a/fpga/usrp3/top/x400/cpld/mb_cpld.v b/fpga/usrp3/top/x400/cpld/mb_cpld.v index 4ea5dc574..2e709acd9 100644 --- a/fpga/usrp3/top/x400/cpld/mb_cpld.v +++ b/fpga/usrp3/top/x400/cpld/mb_cpld.v @@ -1025,7 +1025,7 @@ endmodule // </info> // <value name="PS_CPLD_SIGNATURE" integer="0x0A522D27"/> // <value name="PL_CPLD_SIGNATURE" integer="0x3FDC5C47"/> -// <value name="CPLD_REVISION" integer="0x21012015"/> +// <value name="CPLD_REVISION" integer="0x21111614"/> // <value name="OLDEST_CPLD_REVISION" integer="0x20122114"/> // </enumeratedtype> // </group> diff --git a/fpga/usrp3/top/x400/cpld/mb_cpld.qpf b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qpf index 0e34c0ac5..0e34c0ac5 100644 --- a/fpga/usrp3/top/x400/cpld/mb_cpld.qpf +++ b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qpf diff --git a/fpga/usrp3/top/x400/cpld/mb_cpld.qsf b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qsf index 47ab072ce..001391cfc 100644 --- a/fpga/usrp3/top/x400/cpld/mb_cpld.qsf +++ b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qsf @@ -391,41 +391,42 @@ set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" set_global_assignment -name EN_USER_IO_WEAK_PULLUP OFF set_global_assignment -name EN_SPI_IO_WEAK_PULLUP OFF -set_global_assignment -name VHDL_FILE ip/cmi/PcieCmiWrapper.vhd -set_global_assignment -name VHDL_FILE ip/cmi/PcieCmi.vhd -set_global_assignment -name QSYS_FILE ip/clkctrl/clkctrl.qsys -set_global_assignment -name QSYS_FILE ip/flash/on_chip_flash.qsys -set_global_assignment -name SDC_FILE db_spi_shared_constants.sdc -set_global_assignment -name SDC_FILE mb_cpld.sdc -set_global_assignment -name VERILOG_FILE reconfig_engine.v -set_global_assignment -name VERILOG_FILE mb_cpld.v -set_global_assignment -name VERILOG_FILE ctrlport_to_spi.v -set_global_assignment -name VERILOG_FILE ctrlport_to_jtag.v -set_global_assignment -name VERILOG_FILE pl_cpld_regs.v -set_global_assignment -name VERILOG_FILE pwr_supply_clk_gen.v -set_global_assignment -name VERILOG_FILE ps_cpld_regs.v -set_global_assignment -name VERILOG_FILE reset_generator.v -set_global_assignment -name VERILOG_FILE spi_slave_to_ctrlport_master.v -set_global_assignment -name VERILOG_FILE spi_slave.v -set_global_assignment -name QIP_FILE ip/pll/pll.qip -set_global_assignment -name VERILOG_FILE ../../../lib/control/synchronizer_impl.v -set_global_assignment -name VERILOG_FILE ../../../lib/control/synchronizer.v -set_global_assignment -name VERILOG_FILE ../../../lib/rfnoc/utils/ctrlport_splitter.v -set_global_assignment -name VERILOG_FILE ../../../lib/rfnoc/utils/ctrlport_terminator.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_top.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_shift.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_defines.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_clgen.v -set_global_assignment -name VERILOG_FILE ../../../lib/control/pulse_synchronizer.v -set_global_assignment -name VERILOG_FILE ../../../lib/control/handshake.v -set_global_assignment -name VHDL_FILE ../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd -set_global_assignment -name VHDL_FILE ../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd -set_global_assignment -name QIP_FILE ip/oddr/oddr.qip +set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmiWrapper.vhd +set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmi.vhd +set_global_assignment -name QSYS_FILE ../ip/clkctrl/clkctrl.qsys +set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys +set_global_assignment -name SDC_FILE ../db_spi_shared_constants.sdc +set_global_assignment -name SDC_FILE ../mb_cpld.sdc +set_global_assignment -name VERILOG_FILE ../reconfig_engine.v +set_global_assignment -name VERILOG_FILE ../mb_cpld.v +set_global_assignment -name VERILOG_FILE ../ctrlport_to_spi.v +set_global_assignment -name VERILOG_FILE ../ctrlport_to_jtag.v +set_global_assignment -name VERILOG_FILE ../pl_cpld_regs.v +set_global_assignment -name VERILOG_FILE ../pwr_supply_clk_gen.v +set_global_assignment -name VERILOG_FILE ../ps_cpld_regs.v +set_global_assignment -name VERILOG_FILE ../ps_power_regs.v +set_global_assignment -name VERILOG_FILE ../reset_generator.v +set_global_assignment -name VERILOG_FILE ../spi_slave_to_ctrlport_master.v +set_global_assignment -name VERILOG_FILE ../spi_slave.v +set_global_assignment -name QIP_FILE ../ip/pll/pll.qip +set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer_impl.v +set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer.v +set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_splitter.v +set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_terminator.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_top.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_shift.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_defines.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_clgen.v +set_global_assignment -name VERILOG_FILE ../../../../lib/control/pulse_synchronizer.v +set_global_assignment -name VERILOG_FILE ../../../../lib/control/handshake.v +set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd +set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd +set_global_assignment -name QIP_FILE ../ip/oddr/oddr.qip set_global_assignment -name SOURCE_FILE db/mb_cpld.cmp.rdb set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id "PcieCmi:PcieCmix" set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "PcieCmi:PcieCmix" set_global_assignment -name PARTITION_COLOR 52377 -section_id "PcieCmi:PcieCmix" -set_global_assignment -name PARTITION_IMPORT_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" +set_global_assignment -name PARTITION_IMPORT_FILE ../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" set_global_assignment -name PARTITION_LAST_IMPORTED_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix"
\ No newline at end of file diff --git a/fpga/usrp3/top/x400/cpld/scripts/ps_cs_analysis.tcl b/fpga/usrp3/top/x400/cpld/quartus/ps_cs_analysis.tcl index 03ff77d2c..03ff77d2c 100644 --- a/fpga/usrp3/top/x400/cpld/scripts/ps_cs_analysis.tcl +++ b/fpga/usrp3/top/x400/cpld/quartus/ps_cs_analysis.tcl diff --git a/fpga/usrp3/top/x400/cpld/raw_conversion.cof b/fpga/usrp3/top/x400/cpld/quartus/raw_conversion.cof index 87ecb15d8..87ecb15d8 100644 --- a/fpga/usrp3/top/x400/cpld/raw_conversion.cof +++ b/fpga/usrp3/top/x400/cpld/quartus/raw_conversion.cof diff --git a/fpga/usrp3/top/x400/cpld/reconfig_engine.v b/fpga/usrp3/top/x400/cpld/reconfig_engine.v index a7c94b4a2..fc6a4837e 100644 --- a/fpga/usrp3/top/x400/cpld/reconfig_engine.v +++ b/fpga/usrp3/top/x400/cpld/reconfig_engine.v @@ -73,6 +73,29 @@ module reconfig_engine #( `include "regmap/reconfig_regmap_utils.vh" `include "../../../lib/rfnoc/core/ctrlport.vh" + // Check MAX10 variant target (10M04 or 10M08) + `ifdef VARIANT_10M04 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; + localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M04; + localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M04; + localparam CFM0_WP_OFFSET_MSB = 26; // From Max 10 Flash Memory User Guide. + localparam CFM0_WP_OFFSET_LSB = 24; // From Max 10 Flash Memory User Guide. + `elsif VARIANT_10M08 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08; + localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M08; + localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M08; + localparam CFM0_WP_OFFSET_MSB = 27; // From Max 10 Flash Memory User Guide. + localparam CFM0_WP_OFFSET_LSB = 25; // From Max 10 Flash Memory User Guide. + `else + ERROR_MAX10_variant_must_be_defined(); + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; + localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M04; + localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M04; + localparam CFM0_WP_OFFSET_MSB = 26; // From Max 10 Flash Memory User Guide. + localparam CFM0_WP_OFFSET_LSB = 24; // From Max 10 Flash Memory User Guide. + `endif + + //---------------------------------------------------------- // Flash Interface between Registers and State Machine //---------------------------------------------------------- @@ -264,8 +287,7 @@ module reconfig_engine #( localparam CONTROL_REG_ADDR = 1'b1; localparam SECTOR_ERASE_ADDR_MSB = 22; localparam SECTOR_ERASE_ADDR_LSB = 20; - localparam CFM0_WP_OFFSET_MSB = 26; - localparam CFM0_WP_OFFSET_LSB = 24; + // CFM0_WP_OFFSET_MSB and CFM0_WP_OFFSET_LSB are MAX10 variant dependent. localparam ENABLE_WP = MEM_INIT ? 3'b111 : 3'b100; localparam DISABLE_WP = 3'b000; @@ -742,17 +764,26 @@ endmodule // </info> // <enumeratedtype name="FLASH_PRIMARY_IMAGE_ADDR_ENUM" showhexvalue="true"> // <info> -// Those values are the start and end address of the CFM image flash -// sector from Intel's On-Chip Flash IP Generator. Note that the values -// given in the IP generator are byte based where the values of this enum -// are U32 based (divided by 4). +// These values are the start and end address of the CFM image flash +// sector from Intel's On-Chip Flash IP Generator. +// Be aware that three different values exist per each of the two +// supported MAX10 variants: 10M04 and 10M08 +// Note that the values given in the IP generator are byte based where +// the values of this enum are U32 based (divided by 4). // </info> -// <value name="FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT" +// <value name="FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04" // integer="4096"/> -// <value name="FLASH_PRIMARY_IMAGE_START_ADDR" +// <value name="FLASH_PRIMARY_IMAGE_START_ADDR_10M04" // integer="39936"/> -// <value name="FLASH_PRIMARY_IMAGE_END_ADDR" +// <value name="FLASH_PRIMARY_IMAGE_END_ADDR_10M04" // integer="75775"/> +// +// <value name="FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08" +// integer="8192"/> +// <value name="FLASH_PRIMARY_IMAGE_START_ADDR_10M08" +// integer="44032"/> +// <value name="FLASH_PRIMARY_IMAGE_END_ADDR_10M08" +// integer="79871"/> // </enumeratedtype> // <register name="FLASH_STATUS_REG" offset="0x000" size="32" // attributes="Readable"> @@ -948,9 +979,12 @@ endmodule // Defines the sector to be erased. Has to be set latest with the // write access which starts the erase operation by strobing // @.FLASH_ERASE_STB.{br} -// If the flash is configured to support memory initialization (see -// @.FLASH_MEM_INIT_ENABLED flag) the sectors 2 to 4 have to be erased. -// If the flag is not asserted only sector 4 has to be erased. +// With 10M04 variants, if the flash is configured to support memory +// initialization (see @.FLASH_MEM_INIT_ENABLED flag) the sectors 2 +// to 4 have to be erased. If the flag is not asserted only sector 4 +// has to be erased. +// With 10M08 variants, the sectors to be erased are 3 to 5 when +// using memory initialization or only sector 5 otherwise. // </info> // </bitfield> // <bitfield name="CLEAR_FLASH_READ_ERROR_STB" range="8" diff --git a/fpga/usrp3/top/x400/cpld/regmap/constants_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/constants_regmap_utils.vh index 4e5921f4c..a52461e3b 100644 --- a/fpga/usrp3/top/x400/cpld/regmap/constants_regmap_utils.vh +++ b/fpga/usrp3/top/x400/cpld/regmap/constants_regmap_utils.vh @@ -24,5 +24,5 @@ localparam CONSTANTS_ENUM_SIZE = 4; localparam PS_CPLD_SIGNATURE = 'hA522D27; // CONSTANTS_ENUM:PS_CPLD_SIGNATURE localparam OLDEST_CPLD_REVISION = 'h20122114; // CONSTANTS_ENUM:OLDEST_CPLD_REVISION - localparam CPLD_REVISION = 'h21012015; // CONSTANTS_ENUM:CPLD_REVISION + localparam CPLD_REVISION = 'h21111614; // CONSTANTS_ENUM:CPLD_REVISION localparam PL_CPLD_SIGNATURE = 'h3FDC5C47; // CONSTANTS_ENUM:PL_CPLD_SIGNATURE diff --git a/fpga/usrp3/top/x400/cpld/regmap/reconfig_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/reconfig_regmap_utils.vh index 2ddc6a8b9..f1f4e9142 100644 --- a/fpga/usrp3/top/x400/cpld/regmap/reconfig_regmap_utils.vh +++ b/fpga/usrp3/top/x400/cpld/regmap/reconfig_regmap_utils.vh @@ -28,10 +28,13 @@ //=============================================================================== // Enumerated type FLASH_PRIMARY_IMAGE_ADDR_ENUM - localparam FLASH_PRIMARY_IMAGE_ADDR_ENUM_SIZE = 3; - localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = 'h1000; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT - localparam FLASH_PRIMARY_IMAGE_START_ADDR = 'h9C00; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR - localparam FLASH_PRIMARY_IMAGE_END_ADDR = 'h127FF; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_END_ADDR + localparam FLASH_PRIMARY_IMAGE_ADDR_ENUM_SIZE = 6; + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04 = 'h1000; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08 = 'h2000; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_10M04 = 'h9C00; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR_10M04 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_10M08 = 'hAC00; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR_10M08 + localparam FLASH_PRIMARY_IMAGE_END_ADDR_10M04 = 'h127FF; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_END_ADDR_10M04 + localparam FLASH_PRIMARY_IMAGE_END_ADDR_10M08 = 'h137FF; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_END_ADDR_10M08 // FLASH_STATUS_REG Register (from reconfig_engine.v) localparam FLASH_STATUS_REG = 'h0; // Register Offset diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile index 878054bd6..2ab32fb11 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile @@ -4,87 +4,98 @@ # SPDX-License-Identifier: LGPL-3.0-or-later # -GIT_HASH = $(shell ../../../../../tools/scripts/git-hash.sh) - -build: cpld_defaults ip - @echo -ne "\n---- Make: Synthesis ...\n\n"; - @quartus_map zbx_top_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)"; - @echo -ne "\n\n---- Make: Implementation ...\n\n"; - @quartus_fit zbx_top_cpld; - @echo -ne "\n\n---- Make: Analyzing timing ...\n\n"; - @quartus_sta zbx_top_cpld; - @# grep for unconstrained path warning - @grep "332102" output_files/zbx_top_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# grep for timing closure critical warning - @grep "332148" output_files/zbx_top_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no warnings - @grep -iw "warning" output_files/zbx_top_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no critical warning except "review power analyzer report file" - @grep -i "critical warning" output_files/* | grep -v 16562; \ - if [ $$? -eq 0 ]; then false; else true; fi - @echo -ne "\n\n---- Make: Generating bitfile...\n\n"; - @quartus_asm zbx_top_cpld; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 12.5MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_on.svf -o background_programming=on; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 12.5MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_off.svf; - @echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n"; - @quartus_cpf -c raw_conversion.cof - @echo -ne "\n\n---- Make: Copy final files...\n\n"; - @mkdir -p build - @cp output_files/zbx_top_cpld.pof build/usrp_zbx_cpld.pof - @cp output_files/zbx_top_cpld_isp_off.svf build/usrp_zbx_cpld.svf - @cp output_files/zbx_top_cpld_isp_on.svf build/usrp_zbx_cpld_isp_on.svf - @cp output_files/zbx_top_cpld_converted_cfm0_auto.rpd build/usrp_zbx_cpld.rpd - @echo -ne "\n\n---- Make: ZBX CPLD ready!\n"; - @echo -ne " Use build/usrp_zbx_cpld.pof via JTAG programmer or\n" - @echo -ne " build/usrp_zbx_cpld.svf (ISP off) via MB CPLD JTAG engine or\n" - @echo -ne " build/usrp_zbx_cpld.rpd via reconfig engine or\n" - @echo -ne " build/usrp_zbx_cpld_isp_on.rpd via MB CPLD JTAG engine.\n" - -clean: - @echo -ne "\nCleaning ZBX CPLD...\n"; - @git clean -Xdf +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP ZBX CPLD Help +##------------------- +##Usage: +## make <Targets> <Options> +## +##Output: +## build/<device-id>/usrp_zbx_cpld.pof: Bitstream to use with JTAG programmer +## build/<device-id>/usrp_zbx_cpld.svf: Bitstream to use with PS JTAG engine (background programming) +## build/<device-id>/usrp_zbx_cpld.rpd: Bitstream to use via reconfig engine +## build/<device-id>/usrp_zbx_cpld_isp_off.svf: Bitstream to use with JTAG test points (initial programming) -QSYS_PATH=$(subst \,/,$(QUARTUS_ROOTDIR))/sopc_builder/bin +# Definitions +10M04_ID = "10M04SAU324I7G" -ROOT_DIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST)))) +# Target specific variables +ZBX_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 -REGS_PY_FILE=$(ROOT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py -REGS_PY_MODULE=register_endpoints/memory_init_files/zbx_cpld_regs_t.py +# Using one of the files as a dependency (all files are generated at the same time) +INIT_FILES := register_endpoints/memory_init_files/rx0_path_defaults.hex -$(REGS_PY_MODULE): $(REGS_PY_FILE) - @python3 $(REGS_PY_FILE) $(REGS_PY_MODULE) +TARGET = bin +TOP ?= zbx_top_cpld -# Using one of the files as a dependency (all files are generated at the same time) -INIT_FILES := $(ROOT_DIR)/register_endpoints/memory_init_files/rx0_path_defaults.hex +# pre_build() +pre_build = @\ + mkdir -p build-$@/register_endpoints/memory_init_files/; \ + cp -rf register_endpoints/memory_init_files/*.hex build-$@/register_endpoints/memory_init_files/ + +# quartus_build($1=Device, $2=Definitions) +quartus_build = make -f Makefile.zbx_cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" POST_STA_TCL="ps_cs_analysis.tcl" + +# quartus_ip($1=Device, $2=Definitions) +quartus_ip = make -f Makefile.zbx_cpld.inc quar_ip NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" + +# post_build($1=Artifact Name) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build/; \ + echo "Exporting bitstream files..."; \ + cp build-$@/output_files/$(TOP).pof build/$(1).pof; \ + cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_isp_off.svf; \ + cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1).svf; \ + cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1).rpd; \ + echo -ne "\n\n---- Make: MB CPLD ready!\n"; \ + echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \ + echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \ + echo -ne " build/$(1).rpd via reconfig engine or\n"; \ + echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n"; +else + post_build = @echo "Skipping bitfile export." +endif -$(INIT_FILES): register_endpoints/memory_init_files/gen_defaults.py $(REGS_PY_MODULE) - @python3 $(ROOT_DIR)/register_endpoints/memory_init_files/gen_defaults.py +## +##Supported Targets +##----------------- -cpld_defaults: $(INIT_FILES) +all: ZBX_CPLD_10M04 ##(Default target) -ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \ - ip/osc/osc/simulation/osc.v - @make -C ../../../cpld ip +##ZBX_CPLD_10M04: ZBX CPLD targeted to 10M04SAU169I7G. +ZBX_CPLD_10M04: $(INIT_FILES) + $(call pre_build) + $(call quartus_build,$(10M04_ID),$(DEFS)) + $(call post_build,"usrp_zbx_cpld") -ip/flash/on_chip_flash/simulation/on_chip_flash.v: - $(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG +ZBX_CPLD_IP: ##Build IPs only, needed for simulation. + @# Building only ZBX_CPLD_10M04 IP + $(call quartus_ip,$(10M04_ID),$(DEFS)) + +$(INIT_FILES): + make -f Makefile.zbx_cpld.inc cpld_defaults + +clean: ##Clean up all target build outputs. + @echo -ne "\nCleaning targets and git repo...\n"; + @rm -rf build-ZBX_CPLD* + @rm -rf build + @git clean -Xdf + +cleanall: ##Clean up all target and ip build outputs. + @echo -ne "\nCleaning targets, IP, and git repo...\n"; + @rm -rf build-ZBX_CPLD* + @rm -rf build + @rm -rf build-ip + @git clean -Xdf -ip/osc/osc/simulation/osc.v: - $(QSYS_PATH)/qsys-generate ip/osc/osc.qsys --simulation=VERILOG +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' -all: build +## +##Supported Options +##----------------- +## .PHONY: all build clean ip diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc new file mode 100644 index 000000000..7b47f61cd --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc @@ -0,0 +1,68 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# Project Setup +################################################## +# TOP_MODULE = <Input arg> +# NAME = <Input arg> +# PART_ID = <Input arg> +# ARCH = <Input arg> + +################################################## +# Include other makefiles +################################################## + +PROJECT_DIR = $(abspath .) +BASE_DIR = $(abspath ../../../../) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/quartus_design_builder.mak + +# Include IP directory +include $(IP_DIR)/Makefile.inc + +# Define VERILOG_DEFS for macros definition +VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF) + +# Memory initialization files (CPLD default values) +REGS_PY_FILE=$(PROJECT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py +INIT_FILES_DIR=$(PROJECT_DIR)/register_endpoints/memory_init_files/ +REGS_PY_MODULE=$(INIT_FILES_DIR)/zbx_cpld_regs_t.py + +$(REGS_PY_MODULE): $(REGS_PY_FILE) + @python3 $(REGS_PY_FILE) $(REGS_PY_MODULE) + +# Using one of the files as a dependency (all files are generated at the same time) +INIT_FILES := $(INIT_FILES_DIR)/rx0_path_defaults.hex + +$(INIT_FILES): $(REGS_PY_MODULE) $(INIT_FILES_DIR)/gen_defaults.py + @python3 $(INIT_FILES_DIR)/gen_defaults.py + +cpld_defaults: .prereqs $(INIT_FILES) + @echo "Initialization files DONE ..." + +bin: .prereqs + $(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),$(POST_TCL_SCRIPT),0) + @\ + pushd $(BUILD_DIR); \ + echo "Converting bitfile to svf format (ISP enabled)..."; \ + quartus_cpf --convert \ + --frequency 12.5MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_on.svf -o background_programming=on; \ + echo "Converting bitfile to svf format (ISP disabled)..."; \ + quartus_cpf --convert \ + --frequency 12.5MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_off.svf; \ + echo "Converting bitfile to rpd format..."; \ + quartus_cpf -c raw_conversion.cof; \ + popd; + +quar_ip: .prereqs ip + @echo "IP Build DONE ..." diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm index 97bd80ee4..3d8f4475c 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/doc/ZBX_CPLD_right.htm @@ -1486,9 +1486,9 @@ This enum is used to create the constants held in the basic registers in both ve <tr valign="top"> - <td class='value'>553848841</td> + <td class='value'>554767892</td> - <td class='l'>0x21031009</td> + <td class='l'>0x21111614</td> <td class="l" style="text-align: left;"> <p class="name"><a name='BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES|CPLD_REVISION'></a>CPLD_REVISION</p> @@ -6914,10 +6914,12 @@ Offers ability to enable or disable the PLL reference clock. <a name="RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM"></a> <h3 class="enum">FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration</h3> -Those values are the start and end address of the CFM image flash - sector from Intel's On-Chip Flash IP Generator. Note that the values - given in the IP generator are byte based where the values of this enum - are U32 based (divided by 4). +These values are the start and end address of the CFM image flash + sector from Intel's On-Chip Flash IP Generator. + Be aware that three different values exist per each of the two + supported MAX10 variants: 10M04 and 10M08 + Note that the values given in the IP generator are byte based where + the values of this enum are U32 based (divided by 4). <table class="enum" border="0" cellspacing="0" cellpadding="0"> <tr class="header" valign="center"> @@ -6941,7 +6943,20 @@ Those values are the start and end address of the CFM image flash <td class='l'>0x01000</td> <td class="l" style="text-align: left;"> - <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT</p> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04</p> + +</td> + +</tr> + +<tr valign="top"> + + <td class='value'>8192</td> + + <td class='l'>0x02000</td> + + <td class="l" style="text-align: left;"> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08</p> </td> @@ -6954,7 +6969,20 @@ Those values are the start and end address of the CFM image flash <td class='l'>0x09C00</td> <td class="l" style="text-align: left;"> - <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR'></a>FLASH_PRIMARY_IMAGE_START_ADDR</p> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M04</p> + +</td> + +</tr> + +<tr valign="top"> + + <td class='value'>44032</td> + + <td class='l'>0x0AC00</td> + + <td class="l" style="text-align: left;"> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M08</p> </td> @@ -6967,7 +6995,20 @@ Those values are the start and end address of the CFM image flash <td class='l'>0x127FF</td> <td class="l" style="text-align: left;"> - <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR'></a>FLASH_PRIMARY_IMAGE_END_ADDR</p> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M04</p> + +</td> + +</tr> + +<tr valign="top"> + + <td class='value'>79871</td> + + <td class='l'>0x137FF</td> + + <td class="l" style="text-align: left;"> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M08</p> </td> @@ -7357,9 +7398,12 @@ Total Offset =</td></tr> <p>Defines the sector to be erased. Has to be set latest with the write access which starts the erase operation by strobing <a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB">FLASH_ERASE_STB</a>.<br> - If the flash is configured to support memory initialization (see - <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2 to 4 have to be erased. - If the flag is not asserted only sector 4 has to be erased.</p> + With 10M04 variants, if the flash is configured to support memory + initialization (see <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2 + to 4 have to be erased. If the flag is not asserted only sector 4 + has to be erased. + With 10M08 variants, the sectors to be erased are 3 to 5 when + using memory initialization or only sector 5 otherwise.</p> </td> </tr> diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc new file mode 100644 index 000000000..77d9fce18 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/Makefile.inc @@ -0,0 +1,25 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(IP_DIR)/on_chip_flash/Makefile.inc +include $(IP_DIR)/osc/Makefile.inc +include $(IP_DIR)/clkctrl/Makefile.inc + +IP_SRCS = \ +$(IP_ON_CHIP_FLASH_SRCS) \ +$(IP_OSC_SRCS) \ +$(IP_CLKCTRL_SRCS) + + +IP_OUTPUTS = \ +$(IP_ON_CHIP_FLASH_OUTS) \ +$(IP_OSC_OUTS) \ +$(IP_CLKCTRL_OUTS) + + +ip: $(IP_OUTPUTS) + +.PHONY: ip diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore new file mode 100644 index 000000000..87dce88a7 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore @@ -0,0 +1,3 @@ +# generate files +clkctrl/ +clkctrl.sopcinfo diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc new file mode 100644 index 000000000..2015c6976 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_CLKCTRL_SRCS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.qsys + +IP_CLKCTRL_OUTS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.sopcinfo + +$(IP_CLKCTRL_SRCS) $(IP_CLKCTRL_OUTS) : $(IP_DIR)/clkctrl/clkctrl.qsys + $(call BUILD_QUARTUS_IP,clkctrl,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys new file mode 100644 index 000000000..7a77cfc14 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="$${FILENAME}"> + <component + name="$${FILENAME}" + displayName="$${FILENAME}" + version="1.0" + description="" + tags="INTERNAL_COMPONENT=true" + categories="" /> + <parameter name="bonusData"><![CDATA[bonusData +{ + element altclkctrl_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +]]></parameter> + <parameter name="clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="device" value="10M04SAU324I7G" /> + <parameter name="deviceFamily" value="MAX 10" /> + <parameter name="deviceSpeedGrade" value="7" /> + <parameter name="fabricMode" value="QSYS" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="generationId" value="0" /> + <parameter name="globalResetBus" value="false" /> + <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hideFromIPCatalog" value="true" /> + <parameter name="lockedInterfaceDefinition" value="" /> + <parameter name="maxAdditionalLatency" value="1" /> + <parameter name="projectName" value="" /> + <parameter name="sopcBorderPoints" value="false" /> + <parameter name="systemHash" value="0" /> + <parameter name="testBenchDutName" value="" /> + <parameter name="timeStamp" value="0" /> + <parameter name="useTestBenchNamingPattern" value="false" /> + <instanceScript></instanceScript> + <interface + name="altclkctrl_input" + internal="altclkctrl_0.altclkctrl_input" + type="conduit" + dir="end"> + <port name="inclk" internal="inclk" /> + <port name="ena" internal="ena" /> + </interface> + <interface + name="altclkctrl_output" + internal="altclkctrl_0.altclkctrl_output" + type="conduit" + dir="end"> + <port name="outclk" internal="outclk" /> + </interface> + <module + name="altclkctrl_0" + kind="altclkctrl" + version="18.1" + enabled="1" + autoexport="1"> + <parameter name="CLOCK_TYPE" value="1" /> + <parameter name="DEVICE_FAMILY" value="MAX 10" /> + <parameter name="ENA_REGISTER_MODE" value="1" /> + <parameter name="GUI_USE_ENA" value="true" /> + <parameter name="NUMBER_OF_CLOCKS" value="1" /> + <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" /> + </module> + <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> +</system> diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/.gitignore index 585bc126d..585bc126d 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/.gitignore +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/.gitignore diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc new file mode 100644 index 000000000..fcd8528e6 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_ON_CHIP_FLASH_SRCS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.qsys + +IP_ON_CHIP_FLASH_OUTS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.sopcinfo + +$(IP_ON_CHIP_FLASH_SRCS) $(IP_ON_CHIP_FLASH_OUTS) : $(IP_DIR)/on_chip_flash/on_chip_flash.qsys + $(call BUILD_QUARTUS_IP,on_chip_flash,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/on_chip_flash.qsys index 6598d63cb..6598d63cb 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/flash/on_chip_flash.qsys +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/on_chip_flash/on_chip_flash.qsys diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc new file mode 100644 index 000000000..0793a43b8 --- /dev/null +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/osc/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_OSC_SRCS = \ +$(IP_BUILD_DIR)/osc/osc.qsys + +IP_OSC_OUTS = \ +$(IP_BUILD_DIR)/osc/osc.sopcinfo + +$(IP_OSC_SRCS) $(IP_OSC_OUTS) : $(IP_DIR)/osc/osc.qsys + $(call BUILD_QUARTUS_IP,osc,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/raw_conversion.cof index dc74498aa..dc74498aa 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/raw_conversion.cof +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/raw_conversion.cof diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qpf index 972f9788d..972f9788d 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qpf +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qpf diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf index 141cfa9a4..c164b34e5 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/zbx_top_cpld.qsf +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf @@ -824,49 +824,49 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED # The zbx_top_cpld.v has to stand first as it contains a define statement. -set_global_assignment -name VERILOG_FILE ./zbx_top_cpld.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_decoder.v -set_global_assignment -name SDC_FILE ../../../constraints/timing/shared_constants.sdc -set_global_assignment -name SDC_FILE ../../../cpld/db_spi_shared_constants.sdc -set_global_assignment -name SDC_FILE zbx_top_cpld.sdc -set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer_impl.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/reset_sync.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/rfnoc/utils/ctrlport_splitter.v -set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave.v -set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave_to_ctrlport_master.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/basic_regs.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/power_regs.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/switch_control.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/dsa_control.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/led_control.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_top.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v -set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_shift.v -set_global_assignment -name VERILOG_FILE ./register_endpoints/lo_control.v -set_global_assignment -name VERILOG_FILE ./zbx_cpld_core.v -set_global_assignment -name VERILOG_FILE ../../ctrlport_byte_deserializer.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v -set_global_assignment -name VERILOG_FILE ../../../cpld/reconfig_engine.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_combiner.v -set_global_assignment -name VERILOG_FILE register_endpoints/atr_controller.v -set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../lib/control/ram_2port_impl.vh -set_global_assignment -name VERILOG_FILE ../../../../../lib/control/ram_2port.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/control/handshake.v -set_global_assignment -name VERILOG_FILE ../../../../../lib/control/pulse_synchronizer.v -set_global_assignment -name VERILOG_FILE ./ctrlport_window.v - -set_global_assignment -name QSYS_FILE ip/flash/on_chip_flash.qsys -set_global_assignment -name QSYS_FILE ip/osc/osc.qsys -set_global_assignment -name QSYS_FILE ../../../cpld/ip/clkctrl/clkctrl.qsys -set_global_assignment -name SOURCE_FILE db/zbx_top_cpld.cmp.rdb - -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx1_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx0_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx_dsa_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx1_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx0_path_defaults.hex -set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx_dsa_defaults.hex +set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v +set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc +set_global_assignment -name SDC_FILE ../../../../cpld/db_spi_shared_constants.sdc +set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave_to_ctrlport_master.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/power_regs.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/switch_control.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/dsa_control.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/led_control.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_top.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_shift.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v +set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v +set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/reconfig_engine.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v +set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v +set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v +set_global_assignment -name VERILOG_FILE ../ctrlport_window.v + +set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys +set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys +set_global_assignment -name QSYS_FILE ../../../../cpld/ip/clkctrl/clkctrl.qsys +set_global_assignment -name SOURCE_FILE ../db/zbx_top_cpld.cmp.rdb + +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx1_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx0_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx_dsa_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx1_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx0_path_defaults.hex +set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx_dsa_defaults.hex set_global_assignment -name ENABLE_OCT_DONE OFF set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v index 3c218de17..b208c020b 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v @@ -150,7 +150,7 @@ endmodule // This enum is used to create the constants held in the basic registers in both verilog and vhdl. // </info> // <value name="BOARD_ID_VALUE" integer="0x4002"/> -// <value name="CPLD_REVISION" integer="0x21031009"/> +// <value name="CPLD_REVISION" integer="0x21111614"/> // <value name="OLDEST_CPLD_REVISION" integer="0x20110611"/> // </enumeratedtype> // diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh index 0bbbd704e..dd6e13b8c 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/regmap/basic_regs_regmap_utils.vh @@ -29,7 +29,7 @@ localparam BASIC_REGISTERS_VALUES_SIZE = 3; localparam BOARD_ID_VALUE = 'h4002; // BASIC_REGISTERS_VALUES:BOARD_ID_VALUE localparam OLDEST_CPLD_REVISION = 'h20110611; // BASIC_REGISTERS_VALUES:OLDEST_CPLD_REVISION - localparam CPLD_REVISION = 'h21031009; // BASIC_REGISTERS_VALUES:CPLD_REVISION + localparam CPLD_REVISION = 'h21111614; // BASIC_REGISTERS_VALUES:CPLD_REVISION // SLAVE_SIGNATURE Register (from basic_regs.v) localparam SLAVE_SIGNATURE = 'h0; // Register Offset diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm index 88c73f60c..8280e353b 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm @@ -2338,9 +2338,9 @@ This enumeration is used to create the constants held in the basic registers. <tr valign="top"> - <td class='value'>553721877</td> + <td class='value'>554767892</td> - <td class='l'>0x21012015</td> + <td class='l'>0x21111614</td> <td class="l" style="text-align: left;"> <p class="name"><a name='CONSTANTS_REGMAP|CONSTANTS_ENUM|CPLD_REVISION'></a>CPLD_REVISION</p> @@ -14556,10 +14556,12 @@ RFDC timing control interface. <a name="RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM"></a> <h3 class="enum">FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration</h3> -Those values are the start and end address of the CFM image flash - sector from Intel's On-Chip Flash IP Generator. Note that the values - given in the IP generator are byte based where the values of this enum - are U32 based (divided by 4). +These values are the start and end address of the CFM image flash + sector from Intel's On-Chip Flash IP Generator. + Be aware that three different values exist per each of the two + supported MAX10 variants: 10M04 and 10M08 + Note that the values given in the IP generator are byte based where + the values of this enum are U32 based (divided by 4). <table class="enum" border="0" cellspacing="0" cellpadding="0"> <tr class="header" valign="center"> @@ -14583,7 +14585,20 @@ Those values are the start and end address of the CFM image flash <td class='l'>0x01000</td> <td class="l" style="text-align: left;"> - <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT</p> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04</p> + +</td> + +</tr> + +<tr valign="top"> + + <td class='value'>8192</td> + + <td class='l'>0x02000</td> + + <td class="l" style="text-align: left;"> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08</p> </td> @@ -14596,7 +14611,20 @@ Those values are the start and end address of the CFM image flash <td class='l'>0x09C00</td> <td class="l" style="text-align: left;"> - <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR'></a>FLASH_PRIMARY_IMAGE_START_ADDR</p> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M04</p> + +</td> + +</tr> + +<tr valign="top"> + + <td class='value'>44032</td> + + <td class='l'>0x0AC00</td> + + <td class="l" style="text-align: left;"> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M08</p> </td> @@ -14609,7 +14637,20 @@ Those values are the start and end address of the CFM image flash <td class='l'>0x127FF</td> <td class="l" style="text-align: left;"> - <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR'></a>FLASH_PRIMARY_IMAGE_END_ADDR</p> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M04</p> + +</td> + +</tr> + +<tr valign="top"> + + <td class='value'>79871</td> + + <td class='l'>0x137FF</td> + + <td class="l" style="text-align: left;"> + <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M08</p> </td> @@ -14999,9 +15040,12 @@ Total Offset =</td></tr> <p>Defines the sector to be erased. Has to be set latest with the write access which starts the erase operation by strobing <a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB">FLASH_ERASE_STB</a>.<br> - If the flash is configured to support memory initialization (see - <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2 to 4 have to be erased. - If the flag is not asserted only sector 4 has to be erased.</p> + With 10M04 variants, if the flash is configured to support memory + initialization (see <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2 + to 4 have to be erased. If the flag is not asserted only sector 4 + has to be erased. + With 10M08 variants, the sectors to be erased are 3 to 5 when + using memory initialization or only sector 5 otherwise.</p> </td> </tr> |