diff options
| -rw-r--r-- | fpga/usrp3/top/e320/e320.v | 6 | ||||
| -rw-r--r-- | fpga/usrp3/top/e320/mb_pins.xdc | 7 |
2 files changed, 12 insertions, 1 deletions
diff --git a/fpga/usrp3/top/e320/e320.v b/fpga/usrp3/top/e320/e320.v index 873677c06..501f6a06d 100644 --- a/fpga/usrp3/top/e320/e320.v +++ b/fpga/usrp3/top/e320/e320.v @@ -156,7 +156,8 @@ module e320 ( output wire XCVR_TXNRX, output wire XCVR_ENA_AGC, output wire XCVR_RESET_N, - input wire [7:0] XCVR_CTRL_OUT, + input wire [7:0] XCVR_CTRL_OUT, + output wire [3:0] XCVR_CTRL_IN, // Amplifiers output wire TX_HFAMP1_ENA, @@ -1844,5 +1845,8 @@ module e320 ( .device_id(device_id) ); + // Control pins to AD9361 will lay low for now + assign XCVR_CTRL_IN = 4'h0; + endmodule // e320 `default_nettype wire diff --git a/fpga/usrp3/top/e320/mb_pins.xdc b/fpga/usrp3/top/e320/mb_pins.xdc index 9fa7a5cd0..96160f22f 100644 --- a/fpga/usrp3/top/e320/mb_pins.xdc +++ b/fpga/usrp3/top/e320/mb_pins.xdc @@ -154,6 +154,13 @@ set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_OUT[*]}] set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[6]}] set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[7]}] +# CTRL_IN, Bank 13, 1.8 V +set_property PACKAGE_PIN U24 [get_ports {XCVR_CTRL_IN[0]}] +set_property PACKAGE_PIN V24 [get_ports {XCVR_CTRL_IN[1]}] +set_property PACKAGE_PIN V23 [get_ports {XCVR_CTRL_IN[2]}] +set_property PACKAGE_PIN W24 [get_ports {XCVR_CTRL_IN[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_IN[*]}] + ## RX/TX LEDs, Bank 10, 3.3 V set_property PACKAGE_PIN AG14 [get_ports {RX1_GRN_ENA}] set_property PACKAGE_PIN AG17 [get_ports {RX2_GRN_ENA}] |