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-rw-r--r--fpga/docs/usrp3/sim/running_testbenches.md1
-rw-r--r--fpga/usrp3/tools/make/viv_simulator.mak7
2 files changed, 6 insertions, 2 deletions
diff --git a/fpga/docs/usrp3/sim/running_testbenches.md b/fpga/docs/usrp3/sim/running_testbenches.md
index 2b56af86d..136834bc6 100644
--- a/fpga/docs/usrp3/sim/running_testbenches.md
+++ b/fpga/docs/usrp3/sim/running_testbenches.md
@@ -15,6 +15,7 @@ all supported simulator targets. Currently, the following targets will work:
ipclean: Cleanup all IP intermediate files
clean: Cleanup all simulator intermediate files
cleanall: Cleanup everything!
+ ip: Generate the IP required for this simulation
xsim: Run the simulation using the Xilinx Vivado Simulator
xclean: Cleanup Xilinx Vivado Simulator intermediate files
vsim: Run the simulation using ModelSim simulator via Vivado
diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak
index 66af10fec..eaa23adcc 100644
--- a/fpga/usrp3/tools/make/viv_simulator.mak
+++ b/fpga/usrp3/tools/make/viv_simulator.mak
@@ -86,6 +86,9 @@ SETUP_AND_LAUNCH_MODELSIM = \
.SECONDEXPANSION:
+##ip: Generate the IP required for this simulation
+ip: $(DESIGN_SRCS)
+
##xsim: Run the simulation using the Xilinx Vivado Simulator
xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
$(call SETUP_AND_LAUNCH_SIMULATION,XSim)
@@ -111,7 +114,7 @@ modelsim: .check_tool vlint
# NOTE: VHDL files require a correct compile order. This script compiles files
# in the order they are defined in $(DESIGN_SRC), then $SIM_SRC)
-##vlint: Run ModelSim compiler to lint files.
+##vlint: Run ModelSim compiler to lint files
vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
$(call SETUP_AND_LAUNCH_VLINT)
@@ -127,4 +130,4 @@ clean:: xclean vclean
help::
@grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
-.PHONY: xsim xsim_hls xclean vsim vlint vclean clean help
+.PHONY: ip xsim xsim_hls xclean vsim vlint vclean clean help