diff options
| -rw-r--r-- | CHANGELOG | 208 | ||||
| -rw-r--r-- | images/manifest.txt | 46 |
2 files changed, 225 insertions, 29 deletions
@@ -1,6 +1,193 @@ Change Log for Releases ============================== +## 004.000.000.000 +* b200: + - Enable power calibration API + - Add a prop tree node usb_version +* cal: + - Add utility to update all .fbs files, or check the generated ones + - Add pwr_cal container +* cmake: + - Add ability to pass CXXFLAGS to CMake environment +* docs: + - Update PCIe xport instructions for NI Repos + - n3xx: Include WX in table of N320 images + - Add stream and transport args documentation + - Update Basic/LF dboard references to use new operating mode + - e3xx/n3xx: Add sections on FP-GPIOs and how to drive them + - n3xx: Document eeprom flags + - Add note about DPDK needing to be built as shared libraries + - Change DPDK version to 18.11 and make args use underscores + - Clarifying which devices support DPDK +* dpdk: + - Add new DPDK stack to integrate with I/O services +* e31x: + - Fix filter bank and antenna switching for channel 0 + - Swap out liberio for internal Ethernet +* e320: + - Swap out liberio for internal Ethernet +* examples: + - Add usrp_power_meter example + - Update test_messages example + - Update gpio example + - Add options to benchmark_rate + - Add example out-of-tree module for RFNoC modules + - Remove thread priority elevation +* fpga: + - Replaced RFNoC architecture with new 4.0 version + - Added modelsim make simulation target + - Upgrade to Vivade 2019.1 + - Removed unused coregen files and modules + - Removed fpga submodule and merged into uhd repo + - lib: Change max FFT size to 1024 + - lib: add Intel MAX10 architecture for 2clk FIFO + - rfnoc: Port RFNoC Keep One in N block to new RFNoC architecture + - rfnoc: Port RFNoC Replay block to new RFNoC architecture + - rfnoc: Port Signal Generator RFNoC block to new RFNoC architecture + - Add Switchboard RFNoC block + - Remove liberio + - rfnoc: Port RFNoC Moving Average block to new RFNoC architecture + - rfnoc: Port Log-Power block to new RFNoC architecture + - rfnoc: Port RFNoC Window block to new RFNoC architecture + - lib: Add synthesizable AXI4-Stream SV components + - lib: Add interface and model for AXI4-Lite + - rfnoc: Add support for 512-bit CHDR widths + - rfnoc: Port RFNoC Add/Sub block to new RFNoC architecture + - rfnoc: Port Vector IIR RFNoC block to new RFNoC architecture + - lib: Add AXI-Stream splitter (axis_split) +* lib: + - Add power cal manager + - deps: Add FlatBuffers 1.11.0 header files + - Add DPDK service queue +* mpm: + - Add ability to run scripts to MPM shell + - n3xx: Remove eth1, eth2 from interface list + - Default virtual NIC CHDR IP selection + - Enable internal NIC on the N3xx + - Clean up code, improve Pylint score + - Move common mboard regs code to common location +* mpmd: + - Remove liberio +* multi_usrp: + - Fix connect/disconnect of RFNoC chains + - Various multi_usrp_rfnoc fixes +* n310: + - Fix GPIO registers +* n320: + - Double radio ingress buffer size + - Enable inverse sinc filter for DAC37J82 +* n3xx: + - Swap out liberio for internal Ethernet +* python: + - Add Keep One in N block controller bindings + - Add replay RFNoC block controller bindings + - Add siggen RFNoC block controller bindings + - Add Switchboard block python bindings + - Add moving average RFNoC block controller bindings + - Add bindings for C++ CHDR Parser + - Add window RFNoC block controller bindings + - Add FFT RFNoC block controller bindings + - Add null RFNoC block controller bindings + - Add vector IIR RFNoC block controller bindings + - Add radio RFNoC block controller bindings + - Add FIR filter RFNoC block controller bindings + - Add Fosphor RFNoC block controller bindings + - Add DUC RFNoC block controller bindings + - Add DDC RFNoC block controller bindings + - Added new RFNoC image builder module under the uhd module + - Remove Python2-specific code + - Included complex.h to allow pybind to convert that data type +* rfnoc: + - Add multichannel register interface + - Added support for destruction of streamers + - Add Keep One in N block support + - Port siggen RFNoC block controller support to new RFNoC architecture + - Add Switchboard block support + - Port Moving Average block controller to new RFNoC architecture + - Port Log Power RFNoC block support to new RFNoC architecture + - Port window RFNoC block controller to new RFNoC architecture + - Port Add/Sub RFNoC block support to new RFNoC architecture + - Add USE_MAP prop/action forwarding policy + - Port Split Stream RFNoC block to new RFNoC architecture + - Port Vector IIR RFNoC block support to new RFNoC architecture + - Port RFNoC fosphor block to new RFNoC architecture + - Port FIR filter RFNoC block controller to new RFNoC architecture + - Add multichannel register interface + - Add RFNoC Python API + - Unify endianness of transports + - Add DMA FIFO block controller + - examples: Port examples to new RFNoC + - Implement flushing on overrun + - client_zero can track num SEPs and num ctrl EPs separately + - Add basic round-robin allocation for links + - Add ability to select transport for streamers to user APIs + - Use link_stream_manager's mgmt_portal for all mgmt packets + - graph: Optimize property propagation algorithm + - Port DUC block controller to new RFNoC architecture + - Add MTU tracking + - Implement overrun handling using action API + - Port null block controller to new RFNoC architecture + - Add mb_controller API + - Port radio block controller to new RFNoC architecture + - Port default block controller to new RFNoC architecture + - Port DDC block controller to new RFNoC architecture + - Add rfnoc_graph class + - Add action API + - Refactored CHDR packet interfaces + - Add noc_block_base class +* tests: + - Add unit tests for new RFNoC block controllers + - Fix multi_usrp_test + - Add unit tests for pwr_cal_mgr + - Migrated rfnoc block tests to dedicated subdirectory + - Add more tests for max rate streaming + - Add tests to exercise max streaming rates and report results +* tools: + - Update dissectors for Wireshark major version 3, new CHDR + - Update FPGA functional verification tests for X3x0 mcr's & dpdk +* transport: + - Implement eov indications for Rx and Tx streams + - Implement an I/O service that uses an offload thread + - Implement a single-threaded I/O service +* twinrx: + - Update synthesizer register values for improved rf performance + - Fix increased noise floor + - Remove decimation from frontend +* uhd: + - Disable optimizations for Mac for build speed + - remove liberio + - improved handling of empty serial number hints + - Add discoverable_features API + - Add reference power level API to multi_usrp and radio_control + - Add fuzzy serial number checking + - paths: Harmonize around XDG Base Directory specification + - cal: Use usrp::cal::database instead of CSV files + - cal: Add iq_cal calibration data container class + - cal: Add calibration container class + - cal: Add database class + - Introduce I/O service manager + - Replace usage of boost smart pointers with C++11 counterparts + - add udp boost asio implementation of transport interface + - Add thread affinity utility functions + - types: Extend stream_cmd_t::num_samps to 64 bits +* utils: + - Expose CHDR Parsing API + - Expose CHDR Types in Public API + - Support expressions for num_ports in block defs + - Let uhd_images_downloader also use HTTPS proxies + - Fix FPGA search in rfnoc_image_builder from fpga-src to fpga + - Add convert_cal_data utility + - image_builder: Support parameterized number of ports on blocks +* x300: + - Update frame sizes for 10GbE + - Fix for incorrect PCIe buffer size values + - Change default dboard clock rate from 50 to 100 MHz + - Update maximum bitstream size + - Enable power reference API + - Expand DRAM address space to 1G + - Add front-panel GPIO source control + ## 003.015.000.000 * N320: Fix MCR initialization, fix checks for LO distribution board, reset RX IQ balance on init, replace DRAM FIFO with replay block, @@ -18,7 +205,8 @@ Change Log for Releases capability to flash NI-2974 FPGA, fix clocking code, enable 11.52 MHz and 23.04 MHz system ref rates, improve usage of constrained device args, enable ADC gain through RFNoC API, add mode to set master clock - rate to arbitrary values between 184.32 and 200 MHz + rate to arbitrary values between 184.32 and 200 MHz, fix get_tx_gain() + to make RX/TX gain functions symmetric * E320: Fix time source clobbering ref source, add support for RevE, fix reporting of FPGA version hash, fix SFP link up status, fix missing ce_clk driver @@ -31,7 +219,7 @@ Change Log for Releases * SBX: Only update ATRs when lock state changes * TwinRX: add LO charge pump properties, increase default charge pump value on LO1, add low spur tuning mode, fix duplicate write to N value - in DDC + in DDC, add TwinRX support to phase alignment script * RFNoC/device3: Read command FIFO size from device instead of hardcoding values, fix multidevice graph connections, ENABLE_RFNOC now defaults to ON, search all nodes for tick rate, add update_graph() @@ -58,7 +246,8 @@ Change Log for Releases channels on E310), wait for DPDK links to come up before proceeding, relax failure handling when updating components (fixes spurious errors when updating FPGA images over SFP), fix issue where RPC - initialization would hang on failure + initialization would hang on failure, fixed cmake macros for enabling + modules * FPGA: Use new device-tree overlay syntax, upgraded to Vivado 2018.3, broke various paths with critical timing, allow SystemVerilog source files, improve viv_modify_bd and viv_modify_tcl_bd, fix resets on 2clk @@ -68,10 +257,14 @@ Change Log for Releases includes, demote various log messages, fix logging colours, fix deadlock on Windows machines * Examples: Fix benchmark_rate INIT_DELAY, fix memory leak in - tx_samples_c + tx_samples_c, fix replay example for replay_chan > 1, improve + benchmark_rate output to not interleave * Tests: Make the Python interpreter for devtests a parameter, add unit tests to MPM -* Utilities: Fix converter benchmark for Py3k and scaling issue +* Utilities: Fix converter benchmark for Py3k and scaling issue, use + runtime library path lookup instead of hardcoded paths, improvements + to images downloader (support UHD_IMAGES_URL; check conditions before + writing, use HTTPS instead of HTTP to avoid redirect) * Tools: Fix kitchen_sink * Docs: Various fixes, fix Doxygen warnings, fix links to KB * C API: Add uhd_get_abi_string, uhd_get_version_string @@ -82,7 +275,10 @@ Change Log for Releases versions, add MPM unit testing, fix missing BIGOBJ for MSVC, add our own UHDBoost.cmake to better find Boost across versions and systems * Formatting: Apply clang-format to all files, break after template<> - +* AD9361: Fix mask for product ID check +* Debian: Update control file to rely on Python3 versions of deps +* Octoclock: Clear OctoClock packets and initialize version/seq num + before transmission ## 003.014.001.000 N320: Terminate the DAC when not transmitting diff --git a/images/manifest.txt b/images/manifest.txt index e1a0842fc..9e75020b9 100644 --- a/images/manifest.txt +++ b/images/manifest.txt @@ -1,47 +1,47 @@ # UHD Image Manifest File # Target hash url SHA256 # X300-Series -x3xx_x310_fpga_default fpga-c4d7e8b x3xx/fpga-c4d7e8b/x3xx_x310_fpga_default-gc4d7e8b.zip aba54418fc0e31f02cf5e084e6e77f57ae1c7233c98e76dead87d14e3052de32 -x3xx_x300_fpga_default fpga-c4d7e8b x3xx/fpga-c4d7e8b/x3xx_x300_fpga_default-gc4d7e8b.zip 978510b8ebc17e31953606d666f79dcb3d39bdc0a9721131c807b7fb97b0d35e +x3xx_x310_fpga_default uhd-f2ec5c9 x3xx/uhd-f2ec5c9/x3xx_x310_fpga_default-gf2ec5c9.zip 12879096939c1f6b5217d2e8773eb19bc1cfa88bb5e5595449992334e5fa7def +x3xx_x300_fpga_default uhd-f2ec5c9 x3xx/uhd-f2ec5c9/x3xx_x300_fpga_default-gf2ec5c9.zip aedd1993b9b4cf10e92781c5904b7a225b01c71406921d19892914afe9cbe453 # Example daughterboard targets (none currently exist) #x3xx_twinrx_cpld_default example_target #dboard_ubx_cpld_default example_target # E-Series -e3xx_e310_sg1_fpga_default fpga-c4d7e8b e3xx/fpga-c4d7e8b/e3xx_e310_sg1_fpga_default-gc4d7e8b.zip 123a94d92a471f0d2fb38e05ed2946f71cddb098bc519471a2ec92e78c570d12 -e3xx_e310_sg3_fpga_default fpga-c4d7e8b e3xx/fpga-c4d7e8b/e3xx_e310_sg3_fpga_default-gc4d7e8b.zip 06b269c96bfa04e3e032005bcc9089053535232fd051003e8e335fbd741883d9 -e3xx_e320_fpga_default fpga-c4d7e8b e3xx/fpga-c4d7e8b/e3xx_e320_fpga_default-gc4d7e8b.zip 085cb48fc96e3bd33507e5f34981fccb15536cf01442522d0db6154b7e119d04 +e3xx_e310_sg1_fpga_default uhd-f2ec5c9 e3xx/uhd-f2ec5c9/e3xx_e310_sg1_fpga_default-gf2ec5c9.zip 44a8a551976f1758f93917382d8748356317549a7320c466182a76cc8180853b +e3xx_e310_sg3_fpga_default uhd-f2ec5c9 e3xx/uhd-f2ec5c9/e3xx_e310_sg3_fpga_default-gf2ec5c9.zip e45bd82a9bca59bcf3c4de4610f6f926d60deee2a7e70b17ef2f326905bf2ca6 +e3xx_e320_fpga_default uhd-f2ec5c9 e3xx/uhd-f2ec5c9/e3xx_e320_fpga_default-gf2ec5c9.zip 0aa1bcd4100ca3e0b81f49bdcb9938aca69136362afc9f205cab600424281464 # E310 Filesystems -e3xx_e310_sdk_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e310_sdk_default-v3.15.0.0.zip 0 -e3xx_e310_sg1_mender_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e310_sg1_mender_default-v3.15.0.0.zip 0 -e3xx_e310_sg1_sdimg_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e310_sg1_sdimg_default-v3.15.0.0.zip 0 -e3xx_e310_sg3_mender_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e310_sg3_mender_default-v3.15.0.0.zip 0 -e3xx_e310_sg3_sdimg_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e310_sg3_sdimg_default-v3.15.0.0.zip 0 +e3xx_e310_sdk_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e310_sdk_default-v4.0.0.0-rc1.zip 0 +e3xx_e310_sg1_mender_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e310_sg1_mender_default-v4.0.0.0-rc1.zip 0 +e3xx_e310_sg1_sdimg_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e310_sg1_sdimg_default-v4.0.0.0-rc1.zip 0 +e3xx_e310_sg3_mender_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e310_sg3_mender_default-v4.0.0.0-rc1.zip 0 +e3xx_e310_sg3_sdimg_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e310_sg3_sdimg_default-v4.0.0.0-rc1.zip 0 # E320 Filesystems, etc -e3xx_e320_sdk_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e320_sdk_default-v3.15.0.0.zip 0 -e3xx_e320_mender_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e320_mender_default-v3.15.0.0.zip 0 -e3xx_e320_sdimg_default meta-ettus-v3.15.0.0 e3xx/meta-ettus-v3.15.0.0/e3xx_e320_sdimg_default-v3.15.0.0.zip 0 +e3xx_e320_sdk_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e320_sdk_default-v4.0.0.0-rc1.zip 0 +e3xx_e320_mender_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e320_mender_default-v4.0.0.0-rc1.zip 0 +e3xx_e320_sdimg_default meta-ettus-v4.0.0.0-rc1 e3xx/meta-ettus-v4.0.0.0-rc1/e3xx_e320_sdimg_default-v4.0.0.0-rc1.zip 0 # N300-Series -n3xx_n310_fpga_default fpga-c4d7e8b n3xx/fpga-c4d7e8b/n3xx_n310_fpga_default-gc4d7e8b.zip c233a1fe9676add5dfc6a7388172d26233104f34dad3adfe35cc366f0ddebf83 -n3xx_n300_fpga_default fpga-c4d7e8b n3xx/fpga-c4d7e8b/n3xx_n300_fpga_default-gc4d7e8b.zip b80b0d6035f74bf04fab7533d62a29604284a50748918b780a27d4de0d82ea7f -n3xx_n320_fpga_default fpga-c4d7e8b n3xx/fpga-c4d7e8b/n3xx_n320_fpga_default-gc4d7e8b.zip 6ea3fc6eb121f7b8a50c03eae0200f4e426e16cf752b143daa942f92b50f124b +n3xx_n310_fpga_default uhd-f2ec5c9 n3xx/uhd-f2ec5c9/n3xx_n310_fpga_default-gf2ec5c9.zip 5dbe544d927cb5de7ac4317953b3b4c7f169bb0df9e9b0094b786db0411f6c4c +n3xx_n300_fpga_default uhd-f2ec5c9 n3xx/uhd-f2ec5c9/n3xx_n300_fpga_default-gf2ec5c9.zip d280f2adf6aae9cf94771ad5f0e37de56e11f4849d23f76246ca6b670c13c9de +n3xx_n320_fpga_default uhd-f2ec5c9 n3xx/uhd-f2ec5c9/n3xx_n320_fpga_default-gf2ec5c9.zip 3025b82c44d15d31ed1c7b602c653a706cd55e25dec155675ec060dfe39ee039 n3xx_n310_cpld_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_cpld_default-g6bea23d.zip ef128dcd265ee8615b673021d4ee84c39357012ffe8b28c8ad7f893f9dcb94cb n3xx_n320_cpld_default fpga-4bc2c6f n3xx/fpga-4bc2c6f/n3xx_n320_cpld_default-g4bc2c6f.zip 6680a9363efc5fa8b5a68beb3dff44f2e314b94e716e3a1751aba0fed1f384da # N3XX Mykonos firmware #n3xx_n310_fw_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_fw_default-g6bea23d.zip 0 # N300-Series Filesystems, etc -n3xx_common_sdk_default meta-ettus-v3.15.0.0 n3xx/meta-ettus-v3.15.0.0/n3xx_common_sdk_default-v3.15.0.0.zip 0 -n3xx_common_mender_default meta-ettus-v3.15.0.0 n3xx/meta-ettus-v3.15.0.0/n3xx_common_mender_default-v3.15.0.0.zip 0 -n3xx_common_sdimg_default meta-ettus-v3.15.0.0 n3xx/meta-ettus-v3.15.0.0/n3xx_common_sdimg_default-v3.15.0.0.zip 0 +n3xx_common_sdk_default meta-ettus-v4.0.0.0-rc1 n3xx/meta-ettus-v4.0.0.0-rc1/n3xx_common_sdk_default-v4.0.0.0-rc1.zip 0 +n3xx_common_mender_default meta-ettus-v4.0.0.0-rc1 n3xx/meta-ettus-v4.0.0.0-rc1/n3xx_common_mender_default-v4.0.0.0-rc1.zip 0 +n3xx_common_sdimg_default meta-ettus-v4.0.0.0-rc1 n3xx/meta-ettus-v4.0.0.0-rc1/n3xx_common_sdimg_default-v4.0.0.0-rc1.zip 0 # B200-Series -b2xx_b200_fpga_default fpga-c4d7e8b b2xx/fpga-c4d7e8b/b2xx_b200_fpga_default-gc4d7e8b.zip 31d382dadd7813b330faebf8190d9d05a574a15c339dc79652af1cf9f458f390 -b2xx_b200mini_fpga_default fpga-dc738a7 b2xx/fpga-dc738a7/b2xx_b200mini_fpga_default-gdc738a7.zip 53428d5a4898b3aae640405c5a6daae04e14ca0890a1059dedd59494f64638a9 -b2xx_b210_fpga_default fpga-c4d7e8b b2xx/fpga-c4d7e8b/b2xx_b210_fpga_default-gc4d7e8b.zip a4316d55e5660b6a853c278f492b3589c08aac620855025beac1f8fd69bc94f2 -b2xx_b205mini_fpga_default fpga-dc738a7 b2xx/fpga-dc738a7/b2xx_b205mini_fpga_default-gdc738a7.zip 2e3597b0cf70bdc3e093951b3bdadb93481555b9cab05947c2c00d5fa9033bff +b2xx_b200_fpga_default uhd-f2ec5c9 b2xx/uhd-f2ec5c9/b2xx_b200_fpga_default-gf2ec5c9.zip 026c3b2613ceabbe7f47e479c2933e41ca054e7b1f85a119d86d97b6df4ca744 +b2xx_b200mini_fpga_default uhd-f2ec5c9 b2xx/uhd-f2ec5c9/b2xx_b200mini_fpga_default-gf2ec5c9.zip 3c122145a5bd23dc50ac35b9d18dfe3f3224eaed4242274765ada89c55838ce4 +b2xx_b210_fpga_default uhd-f2ec5c9 b2xx/uhd-f2ec5c9/b2xx_b210_fpga_default-gf2ec5c9.zip 4eba82a362369cc21ba679a4debdcd6aabbc1ecea295eb4aefd94f2ba5e6ed70 +b2xx_b205mini_fpga_default uhd-f2ec5c9 b2xx/uhd-f2ec5c9/b2xx_b205mini_fpga_default-gf2ec5c9.zip a38fcecabcef43d57e463aa50f0b07ba21d7e9211428fbc5ef47bfeb75542e93 b2xx_common_fw_default uhd-2bdad498 b2xx/uhd-2bdad498/b2xx_common_fw_default-g2bdad498.zip a6a867466448f2f75d9d5d290c57ceb8e1d3219391c9f275824fbeb3e7931732 # USRP2 Devices |