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-rw-r--r--fpga/usrp3/top/n3xx/n3xx_clocking.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp3/top/n3xx/n3xx_clocking.v b/fpga/usrp3/top/n3xx/n3xx_clocking.v
index fc7ecbe49..11738f244 100644
--- a/fpga/usrp3/top/n3xx/n3xx_clocking.v
+++ b/fpga/usrp3/top/n3xx/n3xx_clocking.v
@@ -129,8 +129,8 @@ module n3xx_clocking (
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
- // CLK_OUT1___170.543______0.000______50.0______105.052_____94.905 (meas_clk)
- // CLK_OUT2___305.556______0.000______50.0_______93.867_____94.905 (ddr3_dma_clk)
+ // meas_clk___198.413______0.000______50.0______113.755____141.292
+ // ddr3_dma_clk___303.819______0.000______50.0______105.705____141.292
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)