diff options
| -rw-r--r-- | usrp2/control_lib/ram_2port_mixed_width.v | 127 |
1 files changed, 79 insertions, 48 deletions
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index e10321959..e84b0da02 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -1,54 +1,85 @@ + module ram_2port_mixed_width - #(parameter AWIDTH=9) - (input clk16, - input en16, - input we16, - input [10:0] addr16, - input [15:0] di16, - output [15:0] do16, - - input clk32, - input en32, - input we32, - input [9:0] addr32, - input [31:0] di32, - output [31:0] do32); + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output [15:0] do16, + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output [31:0] do32); + + wire en32a = en32 & ~addr32[9]; + wire en32b = en32 & addr32[9]; + wire en16a = en16 & ~addr16[9]; + wire en16b = en16 & addr16[9]; - RAMB16BWER #(.DATA_WIDTH_A(18), // Valid values are 0, 1, 2, 4, 9, 18, or 36 - .DATA_WIDTH_B(36), // Valid values are 0, 1, 2, 4, 9, 18, or 36 - .DOA_REG(0), // Specifies to enable=1/disable=0 port A output registers - .DOB_REG(0), // Specifies to enable=1/disable=0 port B output registers - .INIT_A(36'h000000000), // Initial values on A output port - .INIT_B(36'h000000000), // Initial values on B output port - .RSTTYPE("SYNC"), // Specifes reset type to be "SYNC" or "ASYNC" - .SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY", - // "GENERATE_X_ONLY" or "NONE" - .SRVAL_A(36'h000000000), // Set/Reset value for A port output - .SRVAL_B(36'h000000000), // Set/Reset value for B port output - .WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" - .WRITE_MODE_B("WRITE_FIRST")) // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" - RAMB16BWER_inst (.DOA(do16), // 32-bit A port data output - .DOB(do32), // 32-bit B port data output - .DOPA(), // 4-bit A port parity data output - .DOPB(), // 4-bit B port parity data output - .ADDRA(addr16), // 14-bit A port address input - .ADDRB(addr32), // 14-bit B port address input - .CLKA(clk16), // 1-bit A port clock input - .CLKB(clk32), // 1-bit B port clock input - .DIA(di16), // 32-bit A port data input - .DIB(di32), // 32-bit B port data input - .DIPA(0), // 4-bit A port parity data input - .DIPB(0), // 4-bit B port parity data input - .ENA(en16), // 1-bit A port enable input - .ENB(en32), // 1-bit B port enable input - .REGCEA(0), // 1-bit A port output register enable input - .REGCEB(0), // 1-bit B port output register enable input - .RSTA(0), // 1-bit A port reset input - .RSTB(0), // 1-bit B port reset input - .WEA({2{we16}}), // 4-bit A port write enable input - .WEB({4{we32}}) // 4-bit B port write enable input - ); + wire [31:0] do32a, do32b; + wire [15:0] do16a, do16b; + + assign do32 = addr32[9] ? do32b : do32a; + assign do16 = addr16[10] ? do16b : do16a; + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output + .DOB(do16a), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32a), // Port A 1-bit RAM Enable Input + .ENB(en16a), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output + .DOB(do16b), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32b), // Port A 1-bit RAM Enable Input + .ENB(en16b), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + endmodule // ram_2port_mixed_width |