diff options
187 files changed, 9549 insertions, 4766 deletions
diff --git a/.gitmodules b/.gitmodules index 473a21289..c85c089b3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,4 +1,4 @@ [submodule "fpga-src"] path = fpga-src url = https://github.com/EttusResearch/fpga.git - branch = maint + branch = master diff --git a/firmware/fx3/b200/b200_gpifconfig.h b/firmware/fx3/b200/b200_gpifconfig.h index 58836fac8..a6a24e0c5 100644..100755 --- a/firmware/fx3/b200/b200_gpifconfig.h +++ b/firmware/fx3/b200/b200_gpifconfig.h @@ -1,10 +1,6 @@ -//
-// Copyright 2013-2014 Ettus Research LLC
-//
-
/*
- * Project Name: b200_v2.cyfx
- * Time : 01/17/2013 12:50:08
+ * Project Name: ssf2-edit.cyfx
+ * Time : 11/17/2014 13:01:01
* Device Type: FX3
* Project Type: GPIF2
*
@@ -13,7 +9,7 @@ *
* This is a generated file and should not be modified
* This file need to be included only once in the firmware
- * This file is generated by Gpif2 designer tool version - 1.0.715.0
+ * This file is generated by Gpif2 designer tool version - 1.0.837.1
*
*/
@@ -25,7 +21,7 @@ /* Summary
Number of states in the state machine
*/
-#define CY_NUMBER_OF_STATES 6
+#define CY_NUMBER_OF_STATES 7
/* Summary
Mapping of user defined state names to state indices
@@ -36,12 +32,13 @@ #define WRITE 3
#define SHORT_PKT 4
#define ZLP 5
+#define DSS_STATE 6
/* Summary
Initial value of early outputs from the state machine.
*/
-#define ALPHA_RESET 0x8
+#define ALPHA_RESET 0xC
/* Summary
@@ -58,26 +55,27 @@ uint16_t CyFxGpifTransition[] = { waveform table.
*/
CyU3PGpifWaveData CyFxGpifWavedata[] = {
- {{0x1E086001,0x000100C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
- {{0x4E080302,0x00000200,0x80000000},{0x00000000,0x00000000,0x00000000}},
- {{0x1E086001,0x000100C4,0x80000000},{0x4E040704,0x20000200,0xC0100000}},
+ {{0x1E086001,0x000302C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
+ {{0x4E080302,0x00000300,0x80000000},{0x1E086006,0x000302C4,0x80000000}},
+ {{0x1E086001,0x000302C4,0x80000000},{0x4E040704,0x20000300,0xC0100000}},
+ {{0x4E080302,0x00000300,0x80000000},{0x1E086001,0x000302C4,0x80000000}},
{{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}},
- {{0x00000000,0x00000000,0x00000000},{0x3E738705,0x00000200,0xC0100000}},
- {{0x00000000,0x00000000,0x00000000},{0x5E002703,0x2001020C,0x80000000}},
- {{0x00000000,0x00000000,0x00000000},{0x4E040704,0x20000200,0xC0100000}}
+ {{0x00000000,0x00000000,0x00000000},{0x3E738705,0x00000300,0xC0100000}},
+ {{0x00000000,0x00000000,0x00000000},{0x5E002703,0x2003030C,0x80000000}},
+ {{0x00000000,0x00000000,0x00000000},{0x4E040704,0x20000300,0xC0100000}}
};
/* Summary
Table that maps state indices to the descriptor table indices.
*/
uint8_t CyFxGpifWavedataPosition[] = {
- 0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
- 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
- 0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
- 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
- 0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
- 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
- 0,6,0,2,0,0
+ 0,1,0,2,0,0,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 0,5,0,2,0,0,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 0,6,0,2,0,0,6,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+ 0,7,0,2,0,0,7
};
/* Summary
@@ -154,12 +152,12 @@ uint32_t CyFxGpifRegValue[] = { 0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */
- 0x00080000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
+ 0x000C0000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */
- 0xFFFFFFF1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */
+ 0xFFFFFFC1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */
};
/* Summary
diff --git a/firmware/fx3/b200/b200_main.c b/firmware/fx3/b200/b200_main.c index cb0172af3..e552d3177 100644 --- a/firmware/fx3/b200/b200_main.c +++ b/firmware/fx3/b200/b200_main.c @@ -1,5 +1,5 @@ // -// Copyright 2013-2014 Ettus Research LLC +// Copyright 2013-2015 Ettus Research LLC // /* This file defines the application that runs on the Cypress FX3 device, and @@ -34,18 +34,19 @@ * Indented features must have the parent feature enabled as well. */ -//#define HAS_HEAP // This requires memory to be set aside for the heap (e.g. required for printing floating-point numbers). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to create one. -//#define ENABLE_MSG // This will cause the compiled code to exceed the default text memory area (SYS_MEM). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to resize the memory map so it will fit. -//#define ENABLE_MANUAL_DMA_XFER -//#define ENABLE_MANUAL_DMA_XFER_FROM_HOST -//#define ENABLE_MANUAL_DMA_XFER_TO_HOST +#define HAS_HEAP // This requires memory to be set aside for the heap (e.g. required for printing floating-point numbers). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to create one. +#define ENABLE_MSG // This will cause the compiled code to exceed the default text memory area (SYS_MEM). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to resize the memory map so it will fit. +#define ENABLE_MANUAL_DMA_XFER // Allows us to set it from the host (using the side channel util), doesn't auto-enable it +//#define ENABLE_P2U_SUSP_EOP +#define ENABLE_MANUAL_DMA_XFER_FROM_HOST +#define ENABLE_MANUAL_DMA_XFER_TO_HOST //#define ENABLE_DMA_BUFFER_PACKET_DEBUG -//#define ENABLE_FPGA_SB // Be careful: this will add an ever-so-slight delay to some operations (e.g. AD3961 tune) +#define ENABLE_FPGA_SB // Be careful: this will add an ever-so-slight delay to some operations (e.g. AD3961 tune) #define ENABLE_RE_ENUM_THREAD #define ENABLE_USB_EVENT_LOGGING //#define PREVENT_LOW_POWER_MODE -//#define ENABLE_INIT_B_WORKAROUND // This should only be enabled if you have a board where the FPGA INIT_B line is broken, but the FPGA is known to work -//#define ENABLE_DONE_WORKAROUND // This should only be enabled if you have a board where the FPGA DONE line is broken, but the FPGA is known to work +/*#define ENABLE_INIT_B_WORKAROUND // This should only be enabled if you have a board where the FPGA INIT_B line is broken, but the FPGA is known to work*/ +/*#define ENABLE_DONE_WORKAROUND // This should only be enabled if you have a board where the FPGA DONE line is broken, but the FPGA is known to work*/ #define WATCHDOG_TIMEOUT 1500 #define CHECK_POWER_STATE_SLEEP_TIME 500 // Should be less than WATCHDOG_TIMEOUT @@ -178,7 +179,7 @@ static uint8_t g_usb_event_log_contiguous_buf[USB_EVENT_LOG_SIZE]; #ifdef ENABLE_FPGA_SB static CyBool_t g_fpga_sb_enabled = CyFalse; -static uint16_t g_fpga_sb_uart_div = 434*2; +//static uint16_t g_fpga_sb_uart_div = 434*2; static uint16_t g_fpga_sb_last_usb_event_log_index = 0; static CyU3PThread thread_fpga_sb_poll; static CyU3PMutex g_suart_lock; @@ -215,7 +216,8 @@ enum ConfigFlags { CF_DMA_BUFFER_SIZE = 1 << 5, CF_DMA_BUFFER_COUNT = 1 << 6, CF_MANUAL_DMA = 1 << 7, - + CF_SB_BAUD_DIV = 1 << 8, + CF_RE_ENUM = 1 << 31 }; @@ -236,7 +238,17 @@ typedef struct ConfigMod { CONFIG config; } CONFIG_MOD, *PCONFIG_MOD; -static CONFIG g_config; +static CONFIG g_config = { + 65, // tx_swing + 0x11, // tx_deemphasis + 0, // disable_usb2 + 1, // enable_as_superspeed + CY_U3P_DS_THREE_QUARTER_STRENGTH, // pport_drive_strength + 64512, // dma_buffer_size 2**16-1, then aligned to next page boundary + 1, // dma_buffer_count + 0, // manual_dma + 434*2 // sb_baud_div +}; static CONFIG_MOD g_config_mod; #define REG_LNK_PHY_ERROR_STATUS 0xE0033044 @@ -251,7 +263,7 @@ enum PhyErrors { PHYERR_PHY_ERROR_EB_UND_EV = 1 << 2, PHYERR_PHY_ERROR_EB_OVR_EV = 1 << 1, PHYERR_PHY_ERROR_DECODE_EV = 1 << 0, - + PHYERR_MAX = PHYERR_PHY_LOCK_EV, PHYERR_MASK = (PHYERR_MAX << 1) - 1 }; @@ -259,7 +271,7 @@ enum PhyErrors { typedef struct USBErrorCounters { int phy_error_count; int link_error_count; - + int PHY_LOCK_EV; int TRAINING_ERROR_EV; int RX_ERROR_CRC32_EV; @@ -281,35 +293,45 @@ typedef struct DMACounters { int ERROR; int PROD_SUSP; int CONS_SUSP; - + int BUFFER_MARKER; int BUFFER_EOP; int BUFFER_ERROR; int BUFFER_OCCUPIED; - + int last_count; int last_size; - + int last_sid; int bad_sid_count; } DMA_COUNTERS, *PDMA_COUNTERS; +typedef struct PIBCounters +{ + int socket_inactive; // CYU3P_PIB_ERR_THR1_SCK_INACTIVE +} PIB_COUNTERS, *PPIB_COUNTERS; + typedef struct Counters { int magic; - + DMA_COUNTERS dma_to_host; DMA_COUNTERS dma_from_host; - + int log_overrun_count; - + int usb_error_update_count; - USB_ERROR_COUNTERS usb_error_counters; - + USB_ERROR_COUNTERS usb_error_counters; + int usb_ep_underrun_count; - + int heap_size; - + int resume_count; + + int state_transition_count; + int invalid_gpif_state; + + PIB_COUNTERS pib_counters[4]; } COUNTERS, *PCOUNTERS; volatile static COUNTERS g_counters; @@ -333,7 +355,7 @@ caddr_t _sbrk(int incr) extern char __heap_end; char *prev_heap_end; - if (heap_end == 0) + if (heap_end == 0) { heap_end = (char *)&__heap_start; } @@ -366,15 +388,15 @@ void msg(const char* str, ...) { va_list args; static char buf[LOG_BUFFER_SIZE]; int idx = 0; - + msg_CHECK_USE_LOCK LOCK(g_log_lock); - + ++log_count; log_count %= 10000; va_start(args, str); - + if (1) { // FIXME: Optional uint32_t time_now = CyU3PGetTime(); idx += sprintf(buf, "%08X %04i ", (uint)time_now, log_count); @@ -382,19 +404,19 @@ void msg(const char* str, ...) { else idx += sprintf(buf, "%04i ", log_count); idx += vsnprintf(buf + idx, LOG_BUFFER_SIZE - idx, str, args); - + va_end(args); - + if ((LOG_BUFFER_SIZE - log_buffer_len) < (idx + 1 + 1)) { msg_CHECK_USE_LOCK LOCK(g_counters_lock); ++g_counters.log_overrun_count; msg_CHECK_USE_LOCK UNLOCK(g_counters_lock); - + goto msg_exit; } - + // Circular buffer if we need it later, but currently won't wrap due to above condition memcpy(log_buffer + log_buffer_len, buf, min(idx + 1, LOG_BUFFER_SIZE - log_buffer_len)); if ((idx + 1) > (LOG_BUFFER_SIZE - log_buffer_len)) @@ -404,7 +426,7 @@ void msg(const char* str, ...) { } else log_buffer[log_buffer_len + idx + 1] = '\0'; - + log_buffer_len += (idx + 1); msg_exit: msg_CHECK_USE_LOCK @@ -437,42 +459,42 @@ void msg_nl(const char* str, ...) */ void log_reset(void) { //LOCK(g_log_lock); - + log_buffer_idx = 0; - log_buffer_len = 0; + log_buffer_len = 0; log_buffer[0] = '\0'; - + //UNLOCK(g_log_lock); } void counters_auto_reset(void) { //LOCK(g_counters_lock); - - g_counters.log_overrun_count = 0; - + + g_counters.log_overrun_count = 0; + //UNLOCK(g_counters_lock); } void counters_dma_reset(void) { LOCK(g_counters_lock); - + LOCK(g_counters_dma_to_host_lock); memset((void*)&g_counters.dma_to_host, 0x00, sizeof(DMA_COUNTERS)); UNLOCK(g_counters_dma_to_host_lock); - + LOCK(g_counters_dma_from_host_lock); memset((void*)&g_counters.dma_from_host, 0x00, sizeof(DMA_COUNTERS)); UNLOCK(g_counters_dma_from_host_lock); - + UNLOCK(g_counters_lock); } void counters_reset_usb_errors(void) { LOCK(g_counters_lock); - + g_counters.usb_error_update_count = 0; memset((void*)&g_counters.usb_error_counters, 0x00, sizeof(g_counters.usb_error_counters)); - + UNLOCK(g_counters_lock); } @@ -485,10 +507,10 @@ void dma_callback ( int from_host) { CyU3PReturnStatus_t status = CY_U3P_SUCCESS; - + PDMA_COUNTERS cnt = (PDMA_COUNTERS)(from_host ? &g_counters.dma_from_host : &g_counters.dma_to_host); CyU3PMutex* lock = (from_host ? &g_counters_dma_from_host_lock : &g_counters_dma_to_host_lock); - + uint16_t buffer_status = (input->buffer_p.status & CY_U3P_DMA_BUFFER_STATUS_MASK); if (buffer_status & CY_U3P_DMA_BUFFER_MARKER) { @@ -513,49 +535,51 @@ void dma_callback ( LOCKP(lock); int prod_cnt = cnt->PROD_EVENT++; UNLOCKP(lock); - - if (cnt->last_count != input->buffer_p.count) - msg("[DMA %05d] buffer.count (%d) != last_count (%d)", prod_cnt, input->buffer_p.count, cnt->last_count); + + //if (cnt->last_count != input->buffer_p.count) + // msg("[DMA%d %05d] buffer.count (%05d) != last_count (%05d)", from_host, prod_cnt, input->buffer_p.count, cnt->last_count); cnt->last_count = input->buffer_p.count; - + if (cnt->last_size != input->buffer_p.size) - msg("[DMA %05d] buffer.size (%d) != last_size (%d)", prod_cnt, input->buffer_p.size, cnt->last_size); + msg("[DMA%d %05d] buffer.size (%05d) != last_size (%05d)", from_host, prod_cnt, input->buffer_p.size, cnt->last_size); cnt->last_size = input->buffer_p.size; - + uint32_t* p32 = input->buffer_p.buffer; uint32_t sid = p32[1]; cnt->last_sid = (int)sid; - if ((sid != 0xa0) && (sid != 0xb0)) + if (((from_host == 0) && ((sid != 0xa0) && (sid != 0xb0))) || + ((from_host == 1) && ((sid != 0x50) && (sid != 0x60)))) { cnt->bad_sid_count++; - msg("[DMA %05d] Bad SID: 0x%08x", prod_cnt, sid); + msg("[DMA%d %05d] Bad SID: 0x%08x", from_host, prod_cnt, sid); } - + uint16_t* p16 = input->buffer_p.buffer; - + if (p32[0] & (((uint32_t)1) << 31)) { - msg("[DMA %05d] Error code: 0x%x (packet len: %d)", prod_cnt, p32[4], p16[0]); // Status - - //msg("[DMA] 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", p32[0], p32[1], p32[2], p32[3], p32[4], p32[5]); + msg("[DMA%d %05d] Error code: 0x%x (packet len: %05d, buffer count: %05d, seq: %04d)", from_host, prod_cnt, p32[4], p16[0], input->buffer_p.count, (p16[1] & 0x0fff)); // Status + + //msg("[DMA%d] 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", from_host, p32[0], p32[1], p32[2], p32[3], p32[4], p32[5]); } else - { + { if (p16[1] & (((uint16_t)1) << 12)) { - msg("[DMA %05d] EOB", prod_cnt); // Comes with one sample + msg("[DMA%d %05d] EOB (packet len: %05d, buffer count: %05d)", from_host, prod_cnt, p16[0], input->buffer_p.count); // Comes with one sample } - + if ((p16[0] != input->buffer_p.count) && - ((p16[0] + 4) != input->buffer_p.count)) + ((p16[0] + 4) != input->buffer_p.count)) // Case of overrun packet length being padded (being rounded up) { - msg("[DMA %05d] Packet len (%d) != buffer count (%d)", prod_cnt, p16[0], input->buffer_p.count); + if (from_host == 0) + msg("[DMA%d %05d] Packet len (%05d) != buffer count (%05d), seq: %04d [0x%04x 0x%04x]", from_host, prod_cnt, p16[0], input->buffer_p.count, (p16[1] & 0x0fff), p16[0], p16[1]); } - - //msg("[DMA] 0x%04x 0x%04x 0x%04x 0x%04x", p16[0], p16[1], p16[2], p16[3]); - + + //msg("[DMA%d] 0x%04x 0x%04x 0x%04x 0x%04x", from_host, p16[0], p16[1], p16[2], p16[3]); + if (p16[1] & (((uint16_t)1) << 12)) - msg("[DMA %05d] 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", prod_cnt, p32[0], p32[1], p32[2], p32[3], p32[4], p32[5]); + msg("[DMA%d %05d] 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", from_host, prod_cnt, p32[0], p32[1], p32[2], p32[3], p32[4], p32[5]); } #endif // ENABLE_DMA_BUFFER_PACKET_DEBUG status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0); @@ -594,7 +618,7 @@ void dma_callback ( LOCKP(lock); cnt->ABORTED++; UNLOCKP(lock); - + msg("! Aborted %i", from_host); } else if (type == CY_U3P_DMA_CB_ERROR) @@ -602,7 +626,7 @@ void dma_callback ( LOCKP(lock); cnt->ERROR++; UNLOCKP(lock); - + msg("! Error %i", from_host); } else if (type == CY_U3P_DMA_CB_PROD_SUSP) @@ -610,7 +634,7 @@ void dma_callback ( LOCKP(lock); cnt->PROD_SUSP++; UNLOCKP(lock); - + msg("! Prod suspend %i", from_host); } else if (type == CY_U3P_DMA_CB_CONS_SUSP) @@ -618,8 +642,10 @@ void dma_callback ( LOCKP(lock); cnt->CONS_SUSP++; UNLOCKP(lock); - - msg("! Cons suspend %i", from_host); + + //msg("! Cons suspend %i", from_host); + + CyU3PDmaChannelResume (chHandle, CyFalse, CyTrue); } } @@ -672,7 +698,7 @@ void gpio_interrupt_callback(uint8_t gpio_id) { * everything will come back up properly. */ void b200_fw_stop(void) { msg("b200_fw_stop"); - + CyU3PEpConfig_t usb_endpoint_config; /* Update the flag. */ @@ -683,14 +709,14 @@ void b200_fw_stop(void) { CyU3PUsbFlushEp(DATA_ENDPOINT_CONSUMER); CyU3PUsbFlushEp(CTRL_ENDPOINT_PRODUCER); CyU3PUsbFlushEp(CTRL_ENDPOINT_CONSUMER); - + /* Reset the DMA channels */ // SDK 1.3 known issue #1 - probably not necessary since Destroy is next, but just in case CyU3PDmaChannelReset(&data_cons_to_prod_chan_handle); CyU3PDmaChannelReset(&data_prod_to_cons_chan_handle); CyU3PDmaChannelReset(&ctrl_cons_to_prod_chan_handle); CyU3PDmaChannelReset(&ctrl_prod_to_cons_chan_handle); - + /* Destroy the DMA channels */ CyU3PDmaChannelDestroy(&data_cons_to_prod_chan_handle); CyU3PDmaChannelDestroy(&data_prod_to_cons_chan_handle); @@ -716,7 +742,7 @@ void reset_gpif(void) { CyU3PGpioSetValue(GPIO_FPGA_RESET, CyTrue); // Bring down GPIF - CyU3PGpifDisable(CyTrue); + CyU3PGpifDisable(/*CyTrue*/CyFalse); /* Reset the DMA channels */ CyU3PDmaChannelReset(&data_cons_to_prod_chan_handle); @@ -725,42 +751,41 @@ void reset_gpif(void) { CyU3PDmaChannelReset(&ctrl_prod_to_cons_chan_handle); /* Reset the DMA transfers */ - CyU3PDmaChannelSetXfer(&data_cons_to_prod_chan_handle, \ - DMA_SIZE_INFINITE); - - CyU3PDmaChannelSetXfer(&data_prod_to_cons_chan_handle, \ - DMA_SIZE_INFINITE); - - CyU3PDmaChannelSetXfer(&ctrl_cons_to_prod_chan_handle, \ - DMA_SIZE_INFINITE); - - CyU3PDmaChannelSetXfer(&ctrl_prod_to_cons_chan_handle, \ - DMA_SIZE_INFINITE); + CyU3PDmaChannelSetXfer(&data_cons_to_prod_chan_handle, DMA_SIZE_INFINITE); + CyU3PDmaChannelSetXfer(&data_prod_to_cons_chan_handle, DMA_SIZE_INFINITE); + CyU3PDmaChannelSetXfer(&ctrl_cons_to_prod_chan_handle, DMA_SIZE_INFINITE); + CyU3PDmaChannelSetXfer(&ctrl_prod_to_cons_chan_handle, DMA_SIZE_INFINITE); /* Flush the USB endpoints */ CyU3PUsbFlushEp(DATA_ENDPOINT_PRODUCER); CyU3PUsbFlushEp(DATA_ENDPOINT_CONSUMER); CyU3PUsbFlushEp(CTRL_ENDPOINT_PRODUCER); CyU3PUsbFlushEp(CTRL_ENDPOINT_CONSUMER); - + /* Load the GPIF configuration for Slave FIFO sync mode. */ - CyU3PGpifLoad(&CyFxGpifConfig); - + //CyU3PGpifLoad(&CyFxGpifConfig); + /* Start the state machine. */ - CyU3PGpifSMStart(RESET, ALPHA_RESET); - + //if (CyU3PGpifSMStart(RESET, ALPHA_RESET) != CY_U3P_SUCCESS) + // msg("! CyU3PGpifSMStart"); + /* Configure the watermarks for the slfifo-write buffers. */ - CyU3PGpifSocketConfigure(0, DATA_TX_PPORT_SOCKET, 5, CyFalse, 1); - CyU3PGpifSocketConfigure(1, DATA_RX_PPORT_SOCKET, 6, CyFalse, 1); - CyU3PGpifSocketConfigure(2, CTRL_COMM_PPORT_SOCKET, 5, CyFalse, 1); - CyU3PGpifSocketConfigure(3, CTRL_RESP_PPORT_SOCKET, 6, CyFalse, 1); - + //CyU3PGpifSocketConfigure(0, DATA_TX_PPORT_SOCKET, 5, CyFalse, 1); + //CyU3PGpifSocketConfigure(1, DATA_RX_PPORT_SOCKET, 6, CyFalse, 1); + //CyU3PGpifSocketConfigure(2, CTRL_COMM_PPORT_SOCKET, 5, CyFalse, 1); + //CyU3PGpifSocketConfigure(3, CTRL_RESP_PPORT_SOCKET, 6, CyFalse, 1); + CyU3PGpioSetValue(GPIO_FPGA_RESET, CyFalse); - + CyU3PThreadSleep(FPGA_RESET_SETTLING_TIME); - + + if (CyU3PGpifSMStart(RESET, ALPHA_RESET) != CY_U3P_SUCCESS) + msg("! CyU3PGpifSMStart"); + + msg("GPIF reset"); + b200_start_fpga_sb_gpio(); - + g_fx3_state = STATE_RUNNING; } @@ -792,11 +817,11 @@ CyU3PReturnStatus_t b200_set_io_matrix(CyBool_t fpga_config_mode) { io_config_matrix.useI2C = CyTrue; io_config_matrix.useI2S = CyFalse; io_config_matrix.useSpi = fpga_config_mode; - + res = CyU3PDeviceConfigureIOMatrix(&io_config_matrix); if (res != CY_U3P_SUCCESS) msg("! ConfigureIOMatrix"); - + return res; } @@ -814,11 +839,11 @@ CyU3PReturnStatus_t b200_gpio_init(CyBool_t set_callback) { gpio_clock_config.simpleDiv = CY_U3P_GPIO_SIMPLE_DIV_BY_2; gpio_clock_config.clkSrc = CY_U3P_SYS_CLK; gpio_clock_config.halfDiv = 0; - + res = CyU3PGpioInit(&gpio_clock_config, (set_callback ? gpio_interrupt_callback : NULL)); if (res != CY_U3P_SUCCESS) msg("! CyU3PGpioInit"); - + return res; } @@ -827,36 +852,36 @@ void sb_write(uint8_t reg, uint32_t val) { #ifdef ENABLE_FPGA_SB const int len = 32; int i; - + if (g_fpga_sb_enabled == CyFalse) return; - + reg += FPGA_SB_UART_ADDR_BASE; - + //CyU3PBusyWait(1); // Can be used after each SetValue to slow down bit changes - + // START CyU3PGpioSetValue(GPIO_FPGA_SB_SCL, 1); // Should already be 1 CyU3PGpioSetValue(GPIO_FPGA_SB_SDA, 0); - + // ADDR[8] for (i = 7; i >= 0; i--) { uint8_t bit = ((reg & (0x1 << i)) ? 0x01 : 0x00); CyU3PGpioSetValue(GPIO_FPGA_SB_SCL, 0); CyU3PGpioSetValue(GPIO_FPGA_SB_SDA, bit); - + CyU3PGpioSetValue(GPIO_FPGA_SB_SCL, 1); // FPGA reads bit } - + // DATA[32] for (i = (len-1); i >= 0; i--) { uint8_t bit = ((val & (0x1 << i)) ? 0x01 : 0x00); CyU3PGpioSetValue(GPIO_FPGA_SB_SCL, 0); CyU3PGpioSetValue(GPIO_FPGA_SB_SDA, bit); - + CyU3PGpioSetValue(GPIO_FPGA_SB_SCL, 1); // FPGA reads bit } - + // STOP CyU3PGpioSetValue(GPIO_FPGA_SB_SDA, 0); CyU3PGpioSetValue(GPIO_FPGA_SB_SCL, 0); @@ -888,10 +913,10 @@ void b200_enable_fpga_sb_gpio(CyBool_t enable) { #ifdef ENABLE_FPGA_SB CyU3PGpioSimpleConfig_t gpio_config; CyU3PReturnStatus_t res; - + if (enable == CyFalse) { g_fpga_sb_enabled = CyFalse; - + return; } @@ -900,7 +925,7 @@ void b200_enable_fpga_sb_gpio(CyBool_t enable) { gpio_config.driveHighEn = CyTrue; gpio_config.inputEn = CyFalse; gpio_config.intrMode = CY_U3P_GPIO_NO_INTR; - + res = CyU3PGpioSetSimpleConfig(GPIO_FPGA_SB_SCL, &gpio_config); if (res != CY_U3P_SUCCESS) { msg("! GpioSetSimpleConfig GPIO_FPGA_SB_SCL"); @@ -912,9 +937,9 @@ void b200_enable_fpga_sb_gpio(CyBool_t enable) { CyU3PGpioSetValue(GPIO_FPGA_SB_SCL, 1); CyU3PGpioSetValue(GPIO_FPGA_SB_SDA, 1); - + g_fpga_sb_enabled = CyTrue; - + msg("Debug SB OK"); #endif // ENABLE_FPGA_SB } @@ -923,10 +948,10 @@ void b200_enable_fpga_sb_gpio(CyBool_t enable) { void b200_start_fpga_sb_gpio(void) { #ifdef ENABLE_FPGA_SB LOCK(g_suart_lock); - sb_write(SUART_CLKDIV, g_fpga_sb_uart_div); // 16-bit reg, master clock = 100 MHz (434*2x = 230400/2) + sb_write(SUART_CLKDIV, /*g_fpga_sb_uart_div*/g_config.sb_baud_div); // 16-bit reg, master clock = 100 MHz (434*2x = 230400/2) _sb_write_string("\r\n B2x0 FPGA reset\r\n"); UNLOCK(g_suart_lock); - + msg("Compat: %d.%d", FX3_COMPAT_MAJOR, FX3_COMPAT_MINOR); msg("FX3 SDK: %d.%d.%d (build %d)", CYFX_VERSION_MAJOR, CYFX_VERSION_MINOR, CYFX_VERSION_PATCH, CYFX_VERSION_BUILD); #endif // ENABLE_FPGA_SB @@ -940,15 +965,15 @@ void b200_start_fpga_sb_gpio(void) { * application thread will re-configure some of the pins. */ void b200_gpios_pre_fpga_config(void) { CyU3PGpioSimpleConfig_t gpio_config; - + //b200_enable_fpga_sb_gpio(CyFalse); - + //CyU3PGpioDeInit(); - + b200_set_io_matrix(CyTrue); - + //b200_gpio_init(CyTrue); // This now done once during startup - + //////////////////////////////////// /* GPIO[0:32] must be set with the DeviceOverride function, instead of the @@ -989,24 +1014,24 @@ void b200_gpios_pre_fpga_config(void) { /* Initialize GPIO output values. */ CyU3PGpioSetValue(GPIO_FPGA_RESET, 0); CyU3PGpioSetValue(GPIO_PROGRAM_B, 1); - + b200_enable_fpga_sb_gpio(CyTrue); // So SCL/SDA are already high when SB state machine activates } void b200_slfifo_mode_gpio_config(void) { CyU3PGpioSimpleConfig_t gpio_config; - + //b200_enable_fpga_sb_gpio(CyFalse); - + //CyU3PGpioDeInit(); - + b200_set_io_matrix(CyFalse); //b200_gpio_init(CyFalse); // This now done once during startup - + //////////////////////////////////// - + /* GPIO[0:32] must be set with the DeviceOverride function, instead of the * SimpleEn array configuration. */ CyU3PDeviceGpioOverride(GPIO_FPGA_RESET, CyTrue); @@ -1015,7 +1040,7 @@ void b200_slfifo_mode_gpio_config(void) { CyU3PDeviceGpioOverride(GPIO_FX3_CE, CyTrue); CyU3PDeviceGpioOverride(GPIO_FX3_MISO, CyTrue); CyU3PDeviceGpioOverride(GPIO_FX3_MOSI, CyTrue); - + /* Configure GPIOs: * Outputs: * driveLowEn = True @@ -1031,13 +1056,13 @@ void b200_slfifo_mode_gpio_config(void) { gpio_config.driveHighEn = CyTrue; gpio_config.inputEn = CyFalse; gpio_config.intrMode = CY_U3P_GPIO_NO_INTR; - + CyU3PGpioSetSimpleConfig(GPIO_FPGA_RESET, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_SHDN_SW, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_FX3_SCLK, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_FX3_CE, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_FX3_MOSI, &gpio_config); - + /* Reconfigure the GPIO configure struct for inputs that do NOT require * interrupts attached to them. */ gpio_config.outValue = CyFalse; @@ -1045,23 +1070,23 @@ void b200_slfifo_mode_gpio_config(void) { gpio_config.driveLowEn = CyFalse; gpio_config.driveHighEn = CyFalse; gpio_config.intrMode = CY_U3P_GPIO_NO_INTR; - + CyU3PGpioSetSimpleConfig(GPIO_FX3_MISO, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_AUX_PWR_ON, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_PROGRAM_B, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_INIT_B, &gpio_config); CyU3PGpioSetSimpleConfig(GPIO_DONE, &gpio_config); - + /* Initialize GPIO output values. */ CyU3PGpioSetValue(GPIO_FPGA_RESET, 0); CyU3PGpioSetValue(GPIO_SHDN_SW, 1); CyU3PGpioSetValue(GPIO_FX3_SCLK, 0); CyU3PGpioSetValue(GPIO_FX3_CE, 1); CyU3PGpioSetValue(GPIO_FX3_MOSI, 0); - + // Disabled here as only useful once FPGA has been programmed //b200_enable_fpga_sb_gpio(CyTrue); - //b200_start_fpga_sb_gpio(); // Set set up SB USART + //b200_start_fpga_sb_gpio(); // Set up SB USART } @@ -1072,7 +1097,7 @@ void b200_slfifo_mode_gpio_config(void) { * ready to receive data from the host. */ void b200_fw_start(void) { msg("b200_fw_start"); - + CyU3PDmaChannelConfig_t dma_channel_config; CyU3PEpConfig_t usb_endpoint_config; CyU3PUSBSpeed_t usb_speed; @@ -1095,9 +1120,9 @@ void b200_fw_start(void) { data_buffer_size = 512; g_vendor_req_buff_size = USB2_VREQ_BUF_SIZE; // Max 64 num_packets_per_burst = USB2_PACKETS_PER_BURST; // 1 - + data_buffer_size_to_host = data_buffer_size_from_host = data_buffer_size; - + break; case CY_U3P_SUPER_SPEED: @@ -1110,41 +1135,49 @@ void b200_fw_start(void) { msg("LPMDisable OK"); //#endif // PREVENT_LOW_POWER_MODE max_packet_size = 1024; // Per USB3 spec - + // SDK ver: total available buffer memory // 1.2.3: 204KB // 1.3.1: 188KB - + // These options should be ignored - data_buffer_count *MUST* be 1 // They follow is kept for future testing - + // 1K //data_buffer_count = 64; //data_buffer_size = 1024; - + // 4K //data_buffer_count = 8; //data_buffer_size = 4096; - + + // 8K + //data_buffer_count = 4; + //data_buffer_size = 4096*2; + // 16K //data_buffer_count = 2*2; //data_buffer_size = 16384; // Default 16K - + // 32K //data_buffer_count = 2; //data_buffer_size = 16384*2; - - data_buffer_count = 1; - data_buffer_size = ((1 << 16) - 1); - data_buffer_size -= (data_buffer_size % 1024); // Align to 1K boundary - + + //data_buffer_count = 1; + //data_buffer_size = ((1 << 16) - 1); + //data_buffer_size = 16384; + //data_buffer_size -= (data_buffer_size % 1024); // Align to 1K boundary + + data_buffer_count = g_config.dma_buffer_count; + data_buffer_size = g_config.dma_buffer_size; + data_buffer_size_to_host = data_buffer_size; data_buffer_size_from_host = data_buffer_size; - + g_vendor_req_buff_size = USB3_VREQ_BUF_SIZE; // Max 512 - num_packets_per_burst = USB3_PACKETS_PER_BURST; // 16 + num_packets_per_burst = USB3_PACKETS_PER_BURST*1+4*0; // 16 break; - + case CY_U3P_NOT_CONNECTED: msg("! CY_U3P_NOT_CONNECTED"); return; @@ -1152,9 +1185,31 @@ void b200_fw_start(void) { default: return; } - + msg("[DMA] to host: %d, from host: %d, depth: %d, burst size: %d", data_buffer_size_to_host, data_buffer_size_from_host, data_buffer_count, num_packets_per_burst); +#ifdef ENABLE_MANUAL_DMA_XFER + msg("[DMA] Callback enabled"); + +#ifdef ENABLE_P2U_SUSP_EOP + msg("[DMA] P2U_SUSP_EOP enabled"); +#endif // ENABLE_P2U_SUSP_EOP +#ifdef ENABLE_MANUAL_DMA_XFER_FROM_HOST + msg("[DMA] Manual transfers from host"); +#endif // ENABLE_MANUAL_DMA_XFER_FROM_HOST +#ifdef ENABLE_MANUAL_DMA_XFER_TO_HOST + msg("[DMA] Manual transfers to host"); +#endif // ENABLE_MANUAL_DMA_XFER_TO_HOST +#ifdef ENABLE_DMA_BUFFER_PACKET_DEBUG + msg("[DMA] Packet debugging enabled"); +#endif // ENABLE_DMA_BUFFER_PACKET_DEBUG + +#else + msg("[DMA] AUTO transfer mode"); +#endif // ENABLE_MANUAL_DMA_XFER + + msg("[DMA] Transfer override: %s", (g_config.manual_dma ? "manual" : "auto")); + /************************************************************************* * Slave FIFO Data DMA Channel Configuration *************************************************************************/ @@ -1205,6 +1260,8 @@ CY_U3P_DMA_CB_PROD_SUSP | CY_U3P_DMA_CB_CONS_SUSP | #endif // ENABLE_MANUAL_DMA_XFER 0; + //if (g_config.manual_dma == 0) + // dma_channel_config.notification = 0; // Force all off is manual is disabled dma_channel_config.cb = #if defined(ENABLE_MANUAL_DMA_XFER) && defined(ENABLE_MANUAL_DMA_XFER_FROM_HOST) from_host_dma_callback; @@ -1218,16 +1275,16 @@ CY_U3P_DMA_CB_CONS_SUSP | CyU3PDmaChannelCreate (&data_cons_to_prod_chan_handle, #if defined(ENABLE_MANUAL_DMA_XFER) && defined(ENABLE_MANUAL_DMA_XFER_FROM_HOST) - /*CY_U3P_DMA_TYPE_AUTO_SIGNAL*/CY_U3P_DMA_TYPE_MANUAL, + (g_config.manual_dma ? /*CY_U3P_DMA_TYPE_AUTO_SIGNAL*/CY_U3P_DMA_TYPE_MANUAL : CY_U3P_DMA_TYPE_AUTO), #else CY_U3P_DMA_TYPE_AUTO, #endif // ENABLE_MANUAL_DMA_XFER &dma_channel_config); - + // By default these will adopt 'usb_endpoint_config.pcktSize' //CyU3PSetEpPacketSize(DATA_ENDPOINT_PRODUCER, 16384); //CyU3PSetEpPacketSize(DATA_ENDPOINT_CONSUMER, 16384); - + /* Create a DMA AUTO channel for P2U transfer. */ dma_channel_config.size = data_buffer_size_to_host; dma_channel_config.prodSckId = DATA_RX_PPORT_SOCKET; @@ -1244,21 +1301,28 @@ CY_U3P_DMA_CB_ERROR | CY_U3P_DMA_CB_PROD_SUSP | CY_U3P_DMA_CB_CONS_SUSP | #endif // ENABLE_MANUAL_DMA_XFER +#if defined(ENABLE_MANUAL_DMA_XFER) && defined(ENABLE_P2U_SUSP_EOP) +CY_U3P_DMA_CB_CONS_SUSP | // For 'CyU3PDmaChannelSetSuspend' below +#endif // ENABLE_P2U_SUSP_EOP 0; + //if (g_config.manual_dma == 0) + // dma_channel_config.notification = 0; // Force all off is manual is disabled dma_channel_config.cb = -#if defined(ENABLE_MANUAL_DMA_XFER) && defined(ENABLE_MANUAL_DMA_XFER_TO_HOST) +#if defined(ENABLE_MANUAL_DMA_XFER) && (defined(ENABLE_MANUAL_DMA_XFER_TO_HOST) || defined(ENABLE_P2U_SUSP_EOP)) to_host_dma_callback; #else NULL; #endif // ENABLE_MANUAL_DMA_XFER CyU3PDmaChannelCreate (&data_prod_to_cons_chan_handle, #if defined(ENABLE_MANUAL_DMA_XFER) && defined(ENABLE_MANUAL_DMA_XFER_TO_HOST) - /*CY_U3P_DMA_TYPE_AUTO_SIGNAL*/CY_U3P_DMA_TYPE_MANUAL, + (g_config.manual_dma ? /*CY_U3P_DMA_TYPE_AUTO_SIGNAL*/CY_U3P_DMA_TYPE_MANUAL : CY_U3P_DMA_TYPE_AUTO), #else CY_U3P_DMA_TYPE_AUTO, #endif // ENABLE_MANUAL_DMA_XFER &dma_channel_config); - +#ifdef ENABLE_P2U_SUSP_EOP + CyU3PDmaChannelSetSuspend(&data_prod_to_cons_chan_handle, CY_U3P_DMA_SCK_SUSP_NONE, CY_U3P_DMA_SCK_SUSP_EOP); +#endif // ENABLE_P2U_SUSP_EOP /* Flush the Endpoint memory */ CyU3PUsbFlushEp(DATA_ENDPOINT_PRODUCER); CyU3PUsbFlushEp(DATA_ENDPOINT_CONSUMER); @@ -1328,7 +1392,7 @@ CY_U3P_DMA_CB_CONS_SUSP | /* Set DMA channel transfer size. */ CyU3PDmaChannelSetXfer(&ctrl_cons_to_prod_chan_handle, DMA_SIZE_INFINITE); CyU3PDmaChannelSetXfer(&ctrl_prod_to_cons_chan_handle, DMA_SIZE_INFINITE); - + //CyU3PUsbEnableEPPrefetch(); // To address USB_EVENT_EP_UNDERRUN on EP 0x86 (didn't fix it though) /* Update the application status flag. */ @@ -1364,76 +1428,76 @@ void event_usb_callback (CyU3PUsbEventType_t event_type, uint16_t event_data) { b200_fw_stop(); } break; - + case CY_U3P_USB_EVENT_CONNECT: msg("USB_EVENT_CONNECT"); break; - + case CY_U3P_USB_EVENT_SUSPEND: msg("USB_EVENT_SUSPEND"); break; - + case CY_U3P_USB_EVENT_RESUME: // Known issue: this is called repeatedly after a resume //msg("USB_EVENT_RESUME"); g_counters.resume_count++; // Not locked break; - + case CY_U3P_USB_EVENT_SPEED: msg("USB_EVENT_SPEED"); break; - + case CY_U3P_USB_EVENT_SETINTF: msg("USB_EVENT_SETINTF"); break; - + case CY_U3P_USB_EVENT_SET_SEL: msg("USB_EVENT_SET_SEL"); break; - + case CY_U3P_USB_EVENT_SOF_ITP: // CyU3PUsbEnableITPEvent //msg("USB_EVENT_SOF_ITP"); break; - + case CY_U3P_USB_EVENT_EP0_STAT_CPLT: //msg("USB_EVENT_EP0_STAT_CPLT"); // Occurs each time there's a control transfer break; - + case CY_U3P_USB_EVENT_VBUS_VALID: msg("USB_EVENT_VBUS_VALID"); break; - + case CY_U3P_USB_EVENT_VBUS_REMOVED: msg("USB_EVENT_VBUS_REMOVED"); break; - + case CY_U3P_USB_EVENT_HOST_CONNECT: msg("USB_EVENT_HOST_CONNECT"); break; - + case CY_U3P_USB_EVENT_HOST_DISCONNECT: msg("USB_EVENT_HOST_DISCONNECT"); break; - + case CY_U3P_USB_EVENT_OTG_CHANGE: msg("USB_EVENT_OTG_CHANGE"); break; - + case CY_U3P_USB_EVENT_OTG_VBUS_CHG: msg("USB_EVENT_OTG_VBUS_CHG"); break; - + case CY_U3P_USB_EVENT_OTG_SRP: msg("USB_EVENT_OTG_SRP"); break; - + case CY_U3P_USB_EVENT_EP_UNDERRUN: // See SDK 1.3 known issues 17 if this happens (can probably ignore first logged occurence) LOCK(g_counters_lock); ++g_counters.usb_ep_underrun_count; UNLOCK(g_counters_lock); - + msg("! USB_EVENT_EP_UNDERRUN on EP 0x%02x", event_data); break; - + case CY_U3P_USB_EVENT_LNK_RECOVERY: msg("USB_EVENT_LNK_RECOVERY"); break; @@ -1441,16 +1505,16 @@ void event_usb_callback (CyU3PUsbEventType_t event_type, uint16_t event_data) { case CY_U3P_USB_EVENT_USB3_LNKFAIL: msg("USB_EVENT_USB3_LNKFAIL"); break; - + case CY_U3P_USB_EVENT_SS_COMP_ENTRY: msg("USB_EVENT_SS_COMP_ENTRY"); break; - + case CY_U3P_USB_EVENT_SS_COMP_EXIT: msg("USB_EVENT_SS_COMP_EXIT"); break; #endif // (CYFX_VERSION_MAJOR >= 1) && (CYFX_VERSION_MINOR >= 3) - + default: msg("! Unhandled USB event"); break; @@ -1510,7 +1574,7 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { if(wLength > b200_usb_product_desc[0]) { wLength = b200_usb_product_desc[0]; } - + //msg("MS string desc"); CyU3PUsbSendEP0Data(wLength, ((uint8_t *) b200_usb_product_desc)); @@ -1540,7 +1604,7 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { CyU3PUsbStall(wIndex, CyFalse, CyTrue); handled = CyTrue; CyU3PUsbAckSetup(); - + msg("Clear DATA_ENDPOINT_PRODUCER"); } @@ -1553,7 +1617,7 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { CyU3PUsbStall(wIndex, CyFalse, CyTrue); handled = CyTrue; CyU3PUsbAckSetup(); - + msg("Clear DATA_ENDPOINT_CONSUMER"); } @@ -1566,7 +1630,7 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { CyU3PUsbStall(wIndex, CyFalse, CyTrue); handled = CyTrue; CyU3PUsbAckSetup(); - + msg("Clear CTRL_ENDPOINT_PRODUCER"); } @@ -1579,7 +1643,7 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { CyU3PUsbStall(wIndex, CyFalse, CyTrue); handled = CyTrue; CyU3PUsbAckSetup(); - + msg("Clear CTRL_ENDPOINT_CONSUMER"); } } @@ -1595,7 +1659,7 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { switch(bRequest) { case B200_VREQ_BITSTREAM_START: { CyU3PUsbGetEP0Data(1, g_vendor_req_buffer, &read_count); - + g_fpga_programming_write_count = 0; CyU3PEventSet(&g_event_usb_config, EVENT_BITSTREAM_START, \ @@ -1614,12 +1678,12 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { } break; } - + case B200_VREQ_BITSTREAM_DATA_FILL: { CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, &g_vendor_req_read_count); break; } - + case B200_VREQ_BITSTREAM_DATA_COMMIT: { /*CyU3PReturnStatus_t*/int spi_result = -1; if (g_fx3_state == STATE_CONFIGURING_FPGA) { @@ -1670,8 +1734,14 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { case B200_VREQ_GET_LOG: { LOCK(g_log_lock); - - if (log_buffer_idx == 0) + + if (log_buffer_len == 0) { + log_buffer[0] = '\0'; + CyU3PUsbSendEP0Data(1, (uint8_t*)log_buffer); + //CyU3PUsbSendEP0Data(0, NULL); + //CyU3PUsbAckSetup(); + } + else if (log_buffer_idx == 0) CyU3PUsbSendEP0Data(log_buffer_len, (uint8_t*)log_buffer); else { int len1 = min(LOG_BUFFER_SIZE - log_buffer_idx, log_buffer_len); @@ -1681,39 +1751,39 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { memcpy(log_contiguous_buffer + len1, log_buffer, log_buffer_len - len1); CyU3PUsbSendEP0Data(log_buffer_len, (uint8_t*)log_contiguous_buffer); } - + // FIXME: Necessary? Not used in the other ones //CyU3PUsbSendEP0Data(0, NULL); // Send ZLP since previous send has resulted in an integral # of packets - + log_reset(); - + UNLOCK(g_log_lock); - + //log_reset(); - + break; } case B200_VREQ_GET_COUNTERS: { LOCK(g_counters_lock); - + CyU3PUsbSendEP0Data(sizeof(COUNTERS), (uint8_t*)&g_counters); - + counters_auto_reset(); - + UNLOCK(g_counters_lock); - + //counters_auto_reset(); - + break; } - + case B200_VREQ_CLEAR_COUNTERS: { CyU3PUsbAckSetup(); //CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, &read_count); // Dummy - + counters_dma_reset(); - + break; } @@ -1750,14 +1820,14 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { //msg("USB event log [1] %i", (int)len); } } - + //if (len > 0) // Send a ZLP, otherwise it'll timeout CyU3PUsbSendEP0Data(len, g_usb_event_log_contiguous_buf); - + g_last_usb_event_log_index = idx; break; } - + case B200_VREQ_SET_CONFIG: { CyU3PUsbGetEP0Data(sizeof(CONFIG_MOD), (uint8_t*)g_vendor_req_buffer, &read_count); if (read_count == sizeof(CONFIG_MOD)) { @@ -1766,7 +1836,7 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { } break; } - + case B200_VREQ_GET_CONFIG: { CyU3PUsbSendEP0Data(sizeof(g_config), (uint8_t*)&g_config); break; @@ -1780,64 +1850,77 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { for (i = 0; i < read_count; ++i) sb_write(SUART_TXCHAR, g_vendor_req_buffer[i]); UNLOCK(g_suart_lock); - + msg("Wrote %d SB chars", read_count); #else msg("SB is disabled"); #endif // ENABLE_FPGA_SB break; } - + case B200_VREQ_SET_SB_BAUD_DIV: { uint16_t div; CyU3PUsbGetEP0Data(sizeof(div), (uint8_t*)&div, &read_count); - + if (read_count == sizeof(div)) { #ifdef ENABLE_FPGA_SB LOCK(g_suart_lock); sb_write(SUART_CLKDIV, div); UNLOCK(g_suart_lock); msg("SUART_CLKDIV = %d", div); - g_fpga_sb_uart_div = div; // Store for GPIF (FPGA) reset + /*g_fpga_sb_uart_div*/g_config.sb_baud_div = div; // Store for GPIF (FPGA) reset #else msg("SB is disabled"); #endif // ENABLE_FPGA_SB } else msg("! SUART_CLKDIV received %d bytes", read_count); - + break; } - + case B200_VREQ_FLUSH_DATA_EPS: { //msg("Flushing data EPs..."); - - CyU3PUsbAckSetup(); - + + //CyU3PUsbAckSetup(); + + //CyU3PUsbResetEndpointMemories(); + // From host //CyU3PDmaChannelReset(&data_cons_to_prod_chan_handle); //CyU3PUsbFlushEp(DATA_ENDPOINT_PRODUCER); //CyU3PUsbResetEp(DATA_ENDPOINT_PRODUCER); //CyU3PDmaChannelSetXfer(&data_cons_to_prod_chan_handle, DMA_SIZE_INFINITE); - + + //CyU3PDmaSocketDisable(DATA_RX_PPORT_SOCKET); + //CyU3PDmaChannelReset(&data_cons_to_prod_chan_handle); - CyU3PDmaChannelReset(&data_prod_to_cons_chan_handle); + if (CyU3PDmaChannelReset(&data_prod_to_cons_chan_handle) != CY_U3P_SUCCESS) + { + msg("! CyU3PDmaChannelReset"); + } //CyU3PUsbFlushEp(DATA_ENDPOINT_PRODUCER); CyU3PUsbFlushEp(DATA_ENDPOINT_CONSUMER); //CyU3PUsbResetEp(DATA_ENDPOINT_PRODUCER); - CyU3PUsbResetEp(DATA_ENDPOINT_CONSUMER); +// CyU3PUsbResetEp(DATA_ENDPOINT_CONSUMER); + //CyU3PUsbStall(DATA_ENDPOINT_CONSUMER, CyFalse, CyTrue); //CyU3PDmaChannelSetXfer(&data_cons_to_prod_chan_handle, DMA_SIZE_INFINITE); + //CyU3PDmaSocketEnable(DATA_RX_PPORT_SOCKET); CyU3PDmaChannelSetXfer(&data_prod_to_cons_chan_handle, DMA_SIZE_INFINITE); - + + //CyU3PUsbResetEndpointMemories(); + // To host //CyU3PDmaChannelReset(&data_prod_to_cons_chan_handle); //CyU3PUsbFlushEp(DATA_ENDPOINT_CONSUMER); //CyU3PUsbResetEp(DATA_ENDPOINT_CONSUMER); //CyU3PDmaChannelSetXfer(&data_prod_to_cons_chan_handle, DMA_SIZE_INFINITE); - + + CyU3PUsbAckSetup(); + break; } - + case B200_VREQ_EEPROM_WRITE: { i2cAddr = 0xA0 | ((wValue & 0x0007) << 1); CyU3PUsbGetEP0Data(((wLength + 15) & 0xFFF0), g_vendor_req_buffer, NULL); @@ -1941,6 +2024,97 @@ CyBool_t lpm_request_callback(CyU3PUsbLinkPowerMode link_mode) { } +/* Callback function to check for PIB ERROR*/ +void gpif_error_cb(CyU3PPibIntrType cbType, uint16_t cbArg) +{ + if (cbType==CYU3P_PIB_INTR_ERROR) + { + switch (CYU3P_GET_PIB_ERROR_TYPE(cbArg)) + { + case CYU3P_PIB_ERR_NONE: + break; + case CYU3P_PIB_ERR_THR0_WR_OVERRUN: + msg("CYU3P_PIB_ERR_THR0_WR_OVERRUN"); + break; + case CYU3P_PIB_ERR_THR1_WR_OVERRUN: + msg("CYU3P_PIB_ERR_THR1_WR_OVERRUN"); + break; + case CYU3P_PIB_ERR_THR2_WR_OVERRUN: + msg("CYU3P_PIB_ERR_THR2_WR_OVERRUN"); + break; + case CYU3P_PIB_ERR_THR3_WR_OVERRUN: + msg("CYU3P_PIB_ERR_THR3_WR_OVERRUN"); + break; + case CYU3P_PIB_ERR_THR0_RD_UNDERRUN: + msg("CYU3P_PIB_ERR_THR0_RD_UNDERRUN"); + break; + case CYU3P_PIB_ERR_THR1_RD_UNDERRUN: + msg("CYU3P_PIB_ERR_THR1_RD_UNDERRUN"); + break; + case CYU3P_PIB_ERR_THR2_RD_UNDERRUN: + msg("CYU3P_PIB_ERR_THR2_RD_UNDERRUN"); + break; + case CYU3P_PIB_ERR_THR3_RD_UNDERRUN: + msg("CYU3P_PIB_ERR_THR3_RD_UNDERRUN"); + break; + case CYU3P_PIB_ERR_THR0_ADAP_UNDERRUN: + msg("CYU3P_PIB_ERR_THR0_ADAP_UNDERRUN"); + break; + case CYU3P_PIB_ERR_THR1_ADAP_OVERRUN: + msg("CYU3P_PIB_ERR_THR1_ADAP_OVERRUN"); + break; + // FIXME: Other threads + case CYU3P_PIB_ERR_THR1_SCK_INACTIVE: + //msg("CYU3P_PIB_ERR_THR1_SCK_INACTIVE"); + ++g_counters.pib_counters[1].socket_inactive; // UNSYNC'd + break; + default: + msg("Unknown CYU3P_PIB_ERR %i", CYU3P_GET_PIB_ERROR_TYPE(cbArg)); + break; + } + + switch (CYU3P_GET_GPIF_ERROR_TYPE(cbArg)) + { + case CYU3P_GPIF_ERR_NONE: /**< No GPIF state machine errors. */ + //msg("CYU3P_GPIF_ERR_NONE"); + break; + case CYU3P_GPIF_ERR_INADDR_OVERWRITE: /**< Content of INGRESS_ADDR register is overwritten before read. */ + msg("CYU3P_GPIF_ERR_INADDR_OVERWRITE"); + break; + case CYU3P_GPIF_ERR_EGADDR_INVALID: /**< Attempt to read EGRESS_ADDR register before it is written to. */ + msg("CYU3P_GPIF_ERR_EGADDR_INVALID"); + break; + case CYU3P_GPIF_ERR_DATA_READ_ERR: /**< Read from DMA data thread which is not ready. */ + msg("CYU3P_GPIF_ERR_DATA_READ_ERR"); + break; + case CYU3P_GPIF_ERR_DATA_WRITE_ERR: /**< Write to DMA data thread which is not ready. */ + msg("CYU3P_GPIF_ERR_DATA_WRITE_ERR"); + break; + case CYU3P_GPIF_ERR_ADDR_READ_ERR: /**< Read from DMA address thread which is not ready. */ + msg("CYU3P_GPIF_ERR_ADDR_READ_ERR"); + break; + case CYU3P_GPIF_ERR_ADDR_WRITE_ERR: /**< Write to DMA address thread which is not ready. */ + msg("CYU3P_GPIF_ERR_ADDR_WRITE_ERR"); + break; + case CYU3P_GPIF_ERR_INVALID_STATE: /**< GPIF state machine has reached an invalid state. */ + //msg("CYU3P_GPIF_ERR_INVALID_STATE"); + ++g_counters.invalid_gpif_state; // UNSYNC'd + break; + default: + msg("Unknown CYU3P_GPIF_ERR %i", CYU3P_GET_GPIF_ERROR_TYPE(cbArg)); + break; + } + } +} + + +void GpifStateChangeCb(uint8_t stateId) +{ + //msg("%d", stateId); + ++g_counters.state_transition_count; +} + + /*! Initialize and start the GPIF state machine. * * This function starts the GPIF Slave FIFO state machine on the FX3. Because on @@ -1948,7 +2122,7 @@ CyBool_t lpm_request_callback(CyU3PUsbLinkPowerMode link_mode) { * after FPGA configuration is complete. */ void b200_gpif_init(void) { msg("b200_gpif_init"); - + CyU3PPibClock_t pib_clock_config; /* Initialize the p-port block; disable DLL for sync GPIF. */ @@ -1956,19 +2130,34 @@ void b200_gpif_init(void) { pib_clock_config.clkSrc = CY_U3P_SYS_CLK; pib_clock_config.isHalfDiv = CyFalse; pib_clock_config.isDllEnable = CyFalse; - CyU3PPibInit(CyTrue, &pib_clock_config); + if (CyU3PPibInit(CyTrue, &pib_clock_config) != CY_U3P_SUCCESS) + msg("! CyU3PPibInit"); /* Load the GPIF configuration for Slave FIFO sync mode. */ - CyU3PGpifLoad(&CyFxGpifConfig); + if (CyU3PGpifLoad(&CyFxGpifConfig) != CY_U3P_SUCCESS) + msg("! CyU3PGpifLoad"); + + msg("GPIF loaded"); + + //CyU3PGpifRegisterSMIntrCallback(GpifStateChangeCb); /* Start the state machine. */ - CyU3PGpifSMStart(RESET, ALPHA_RESET); + //CyU3PGpifSMStart(RESET, ALPHA_RESET); /* Configure the watermarks for the slfifo-write buffers. */ - CyU3PGpifSocketConfigure(0, DATA_TX_PPORT_SOCKET, 5, CyFalse, 1); - CyU3PGpifSocketConfigure(1, DATA_RX_PPORT_SOCKET, 6, CyFalse, 1); - CyU3PGpifSocketConfigure(2, CTRL_COMM_PPORT_SOCKET, 5, CyFalse, 1); - CyU3PGpifSocketConfigure(3, CTRL_RESP_PPORT_SOCKET, 6, CyFalse, 1); + if (CyU3PGpifSocketConfigure(0, DATA_TX_PPORT_SOCKET, 5, CyFalse, 1) != CY_U3P_SUCCESS) + msg("! CyU3PGpifSocketConfigure 0"); + if (CyU3PGpifSocketConfigure(1, DATA_RX_PPORT_SOCKET, 6, CyFalse, 1) != CY_U3P_SUCCESS) + msg("! CyU3PGpifSocketConfigure 1"); + if (CyU3PGpifSocketConfigure(2, CTRL_COMM_PPORT_SOCKET, 5, CyFalse, 1) != CY_U3P_SUCCESS) + msg("! CyU3PGpifSocketConfigure 2"); + if (CyU3PGpifSocketConfigure(3, CTRL_RESP_PPORT_SOCKET, 6, CyFalse, 1) != CY_U3P_SUCCESS) + msg("! CyU3PGpifSocketConfigure 3"); + + //CyU3PGpifSMStart(RESET, ALPHA_RESET); + + /* Register a callback for notification of PIB interrupts*/ + CyU3PPibRegisterCallback(gpif_error_cb, CYU3P_PIB_INTR_ERROR); } @@ -1979,7 +2168,7 @@ void b200_gpif_init(void) { * 32-bit mode. */ CyU3PReturnStatus_t b200_spi_init(void) { msg("b200_spi_init"); - + CyU3PSpiConfig_t spiConfig; /* Start the SPI module and configure the master. */ @@ -2000,10 +2189,10 @@ CyU3PReturnStatus_t b200_spi_init(void) { spiConfig.wordLen = 8; CyU3PReturnStatus_t res = CyU3PSpiSetConfig(&spiConfig, NULL); - + if (res != CY_U3P_SUCCESS) msg("! CyU3PSpiSetConfig"); - + return res; } @@ -2015,7 +2204,7 @@ CyU3PReturnStatus_t b200_spi_init(void) { */ void b200_usb_init(void) { //msg("b200_usb_init"); - + /* Initialize the I2C interface for the EEPROM of page size 64 bytes. */ CyFxI2cInit(CY_FX_USBI2C_I2C_PAGE_SIZE); @@ -2137,48 +2326,53 @@ void b200_usb_init(void) { CyU3PUsbSetDesc(CY_U3P_USB_SET_STRING_DESCR, 3, (uint8_t *) dev_serial); - + //////////////////////////////////////////////////////// // FIXME: CyU3PUsbSetTxDeemphasis(0x11); <0x1F // Shouldn't need to change this - uint32_t tx_swing = /*65*/45; // 65 & 45 are OK, 120 causes much link recovery. <128. 1.2V is USB3 limit. + const uint32_t tx_swing = g_config.tx_swing/*65*//*45*/; // 65 & 45 are OK, 120 causes much link recovery. <128. 1.2V is USB3 limit. if (CyU3PUsbSetTxSwing(tx_swing) == CY_U3P_SUCCESS) - msg("CyU3PUsbSetTxSwing %d", tx_swing); + msg("CyU3PUsbSetTxSwing: %d", tx_swing); else - msg("! CyU3PUsbSetTxSwing %d", tx_swing); + msg("! CyU3PUsbSetTxSwing: %d", tx_swing); //////////////////////////////////////////////////////// /* Connect the USB pins, and enable SuperSpeed (USB 3.0). */ - CyU3PConnectState(CyTrue, CyTrue); // connect, ssEnable + if (CyU3PConnectState(CyTrue, (g_config.enable_as_superspeed != 0 ? CyTrue : CyFalse)) == CY_U3P_SUCCESS) { // connect, ssEnable + CyU3PUSBSpeed_t usb_speed = CyU3PUsbGetSpeed(); + msg("Link up (speed: USB %d)", (int)usb_speed); // MAGIC: Values happen to map + } + else + msg("! Failed to establish link"); } void b200_restore_gpio_for_fpga_config(void) { CyU3PDeviceGpioRestore(GPIO_FPGA_RESET); CyU3PDeviceGpioRestore(GPIO_DONE); - + CyU3PDeviceGpioRestore(GPIO_FX3_SCLK); CyU3PDeviceGpioRestore(GPIO_FX3_CE); CyU3PDeviceGpioRestore(GPIO_FX3_MISO); CyU3PDeviceGpioRestore(GPIO_FX3_MOSI); - + //CyU3PGpioDeInit(); // Moved to just before init } void thread_fpga_config_entry(uint32_t input) { uint32_t event_flag; - + //msg("thread_fpga_config_entry"); - + for(;;) { - + // Event is set through VREQ if(CyU3PEventGet(&g_event_usb_config, \ (EVENT_FPGA_CONFIG), CYU3P_EVENT_AND_CLEAR, \ &event_flag, CYU3P_WAIT_FOREVER) == CY_U3P_SUCCESS) { - + //uint8_t old_state = g_fx3_state; uint32_t old_fpga_programming_write_count = 0; @@ -2200,7 +2394,7 @@ void thread_fpga_config_entry(uint32_t input) { /* Configure the device GPIOs for FPGA programming. */ b200_gpios_pre_fpga_config(); - + CyU3PSysWatchDogClear(); /* Initialize the SPI module that will be used for FPGA programming. */ @@ -2213,7 +2407,7 @@ void thread_fpga_config_entry(uint32_t input) { /* We can now begin configuring the FPGA. */ g_fx3_state = STATE_FPGA_READY; - + msg("Begin FPGA"); // Event is set through VREQ @@ -2232,7 +2426,7 @@ void thread_fpga_config_entry(uint32_t input) { CyU3PThreadSleep(FPGA_PROGRAMMING_POLL_SLEEP); CyU3PSysWatchDogClear(); } - + if (wait_count >= FPGA_PROGRAMMING_BITSTREAM_START_POLL_COUNT) continue; @@ -2243,7 +2437,7 @@ void thread_fpga_config_entry(uint32_t input) { /* Wait for INIT_B to fall and rise. */ wait_count = 0; - + msg("Wait FPGA"); while(CyU3PEventGet(&g_event_usb_config, \ @@ -2282,9 +2476,9 @@ void thread_fpga_config_entry(uint32_t input) { /* We are ready to accept the FPGA bitstream! */ wait_count = 0; g_fx3_state = STATE_CONFIGURING_FPGA; - + msg("Configuring FPGA"); - + // g_fpga_programming_write_count is zero'd by VREQ triggering EVENT_BITSTREAM_START while(CyU3PEventGet(&g_event_usb_config, \ @@ -2308,7 +2502,7 @@ void thread_fpga_config_entry(uint32_t input) { wait_count = 0; old_fpga_programming_write_count = g_fpga_programming_write_count; } - + CyU3PThreadSleep(FPGA_PROGRAMMING_POLL_SLEEP); CyU3PSysWatchDogClear(); } @@ -2329,42 +2523,42 @@ void thread_fpga_config_entry(uint32_t input) { #endif // ENABLE_DONE_WORKAROUND if (wait_count >= FPGA_PROGRAMMING_DONE_POLL_COUNT) continue; - + msg("FPGA done"); - + /* Tell the host that we are ignoring it for a while. */ g_fx3_state = STATE_BUSY; - + CyU3PSysWatchDogClear(); - + /* Now that the FPGA is configured, we need to tear down the current SPI and * GPIO configs, and re-config for GPIF & bit-banged SPI operation. */ CyU3PSpiDeInit(); b200_restore_gpio_for_fpga_config(); - + CyU3PSysWatchDogClear(); - + /* Load the GPIO configuration for normal SLFIFO use. */ b200_slfifo_mode_gpio_config(); - + /* Tone down the drive strength on the P-port. */ //CyU3PSetPportDriveStrength(CY_U3P_DS_HALF_STRENGTH); - + CyU3PSysWatchDogClear(); - + /* FPGA configuration is complete! Time to get the GPIF state machine * running for Slave FIFO. */ b200_gpif_init(); - + CyU3PThreadSleep(1); b200_start_fpga_sb_gpio(); // Moved here to give SB time to init - + /* RUN, BABY, RUN! */ g_fx3_state = STATE_RUNNING; - + msg("Running"); } - + CyU3PThreadRelinquish(); } } @@ -2403,15 +2597,15 @@ void thread_main_app_entry(uint32_t input) { while((current_state >= CyU3PUsbLPM_U1) \ && (current_state <= CyU3PUsbLPM_U3)) { - + msg("! LPS = %i", current_state); CyU3PUsbSetLinkPowerState(CyU3PUsbLPM_U0); // This will wake up the host if it's trying to sleep CyU3PThreadSleep(1); - + if (CyU3PUsbGetSpeed () != CY_U3P_SUPER_SPEED) break; - + CyU3PUsbGetLinkPowerState (¤t_state); } } @@ -2426,12 +2620,12 @@ static uint32_t g_poll_last_phy_error_status = 0; void update_error_counters(void) { if (CyU3PUsbGetSpeed () != CY_U3P_SUPER_SPEED) return; - + uvint32_t reg = REG_LNK_PHY_ERROR_STATUS; uint32_t val = 0; if (CyU3PReadDeviceRegisters((uvint32_t*)reg, 1, &val) == CY_U3P_SUCCESS) { g_poll_last_phy_error_status |= (val & PHYERR_MASK); - + // Reset after read uint32_t zero = PHYERR_MASK; if (CyU3PWriteDeviceRegisters((uvint32_t*)reg, 1, &zero) != CY_U3P_SUCCESS) @@ -2441,12 +2635,12 @@ void update_error_counters(void) { // FIXME: Log once msg("! Reg read fail"); } - + // Equivalent code: //uint32_t* p = (uint32_t*)REG_LNK_PHY_ERROR_STATUS; //val = (*p); //(*p) = PHYERR_MASK; - + uint16_t phy_error_count = 0, link_error_count = 0; if (CyU3PUsbGetErrorCounts(&phy_error_count, &link_error_count) == CY_U3P_SUCCESS) { // Resets internal counters after call g_poll_last_phy_error_count += phy_error_count; @@ -2456,7 +2650,7 @@ void update_error_counters(void) { // FIXME: Log once msg("! CyU3PUsbGetErrorCounts"); } - + LOCK(g_counters_lock); g_counters.usb_error_update_count++; g_counters.usb_error_counters.phy_error_count += phy_error_count; @@ -2478,50 +2672,153 @@ void update_error_counters(void) { void thread_re_enum_entry(uint32_t input) { uint32_t event_flag; - + //msg("thread_re_enum_entry"); - + int keep_alive = 0; - + while (1) { if (CyU3PEventGet(&g_event_usb_config, \ (EVENT_RE_ENUM), CYU3P_EVENT_AND_CLEAR, \ &event_flag, RE_ENUM_THREAD_SLEEP_TIME) == CY_U3P_SUCCESS) { msg("Re-config"); - + // FIXME: This section is not finished - + // Not locking this since we only expect one write in VREQ and read afterward here - - int re_enum = g_config_mod.flags & (CF_RE_ENUM | CF_TX_SWING | CF_TX_DEEMPHASIS); - + + int re_enum = g_config_mod.flags & (CF_RE_ENUM | CF_TX_SWING | CF_TX_DEEMPHASIS | CF_DISABLE_USB2 | CF_ENABLE_AS_SUPERSPEED); + CyU3PThreadSleep(100); // Wait for EP0 xaction to complete - + //b200_fw_stop(); - + +/* + int tx_swing; // [90] [65] 45 + int tx_deemphasis; // 0x11 + int disable_usb2; // 0 + int enable_as_superspeed; // 1 + int pport_drive_strength; // CY_U3P_DS_THREE_QUARTER_STRENGTH + int dma_buffer_size; // [USB3] (max) + int dma_buffer_count; // [USB3] 1 + int manual_dma; // 0 + int sb_baud_div; // 434*2 +*/ + if (re_enum) { - msg("Link down"); - CyU3PConnectState(CyFalse, CyTrue); + if (CyU3PConnectState(CyFalse, (g_config.enable_as_superspeed != 0 ? CyTrue : CyFalse)) == CY_U3P_SUCCESS) + msg("Link down"); + else + msg("! Failed to bring link down"); } - + if (g_config_mod.flags & CF_TX_DEEMPHASIS) { - //g_config_mod.config.tx_deemphasis - //CyU3PUsbSetTxDeemphasis(0x11); <0x1F +#if (CYFX_VERSION_MAJOR >= 1) && (CYFX_VERSION_MINOR >= 3) + if ((g_config_mod.config.tx_deemphasis < 0x1F) && (CyU3PUsbSetTxDeemphasis(g_config_mod.config.tx_deemphasis) == CY_U3P_SUCCESS)) { + msg("TX deemphasis now: %d (was: %d)", g_config_mod.config.tx_deemphasis, g_config.tx_deemphasis); + g_config.tx_deemphasis = g_config_mod.config.tx_deemphasis; + } + else +#endif // #if (CYFX_VERSION_MAJOR >= 1) && (CYFX_VERSION_MINOR >= 3) + msg("! Failed to set TX deemphasis: %d (still: %d)", g_config_mod.config.tx_deemphasis, g_config.tx_deemphasis); } + if (g_config_mod.flags & CF_TX_SWING) { - //CyU3PUsbSetTxSwing(90); <128 + if ((g_config_mod.config.tx_swing < 128) && (CyU3PUsbSetTxSwing(g_config_mod.config.tx_swing) == CY_U3P_SUCCESS)) { + msg("TX swing now: %d (was: %d)", g_config_mod.config.tx_swing, g_config.tx_swing); + g_config.tx_swing = g_config_mod.config.tx_swing; + } + else + msg("! Failed to set TX swing: %d (still: %d)", g_config_mod.config.tx_swing, g_config.tx_swing); + } + + if (g_config_mod.flags & CF_DISABLE_USB2) { + if (CyU3PUsbControlUsb2Support((g_config_mod.config.disable_usb2 != 0 ? CyTrue : CyFalse)) == CY_U3P_SUCCESS) { + msg("USB 2 support now: %s (was: %d)", (g_config_mod.config.disable_usb2 ? "disabled" : "enabled"), (g_config.disable_usb2 ? "disabled" : "enabled")); + g_config.disable_usb2 = g_config_mod.config.disable_usb2; + } + else + msg("! Failed to change USB 2 support to: %s (still: %s)", (g_config_mod.config.disable_usb2 ? "enabled" : "disabled"), (g_config.disable_usb2 ? "enabled" : "disabled")); + } + + if (g_config_mod.flags & CF_PPORT_DRIVE_STRENGTH) { + // CY_U3P_DS_QUARTER_STRENGTH,CY_U3P_DS_HALF_STRENGTH,CY_U3P_DS_THREE_QUARTER_STRENGTH,CY_U3P_DS_FULL_STRENGTH + if ((g_config_mod.config.pport_drive_strength >= CY_U3P_DS_QUARTER_STRENGTH) && + (g_config_mod.config.pport_drive_strength <= CY_U3P_DS_FULL_STRENGTH) && + (CyU3PSetPportDriveStrength(g_config_mod.config.pport_drive_strength) == CY_U3P_SUCCESS)) { + msg("PPort drive strength now: %d (was: %d)", g_config_mod.config.pport_drive_strength, g_config.pport_drive_strength); + g_config.pport_drive_strength = g_config_mod.config.pport_drive_strength; + } + else + msg("! Failed to set PPort drive strength: %d (still: %d)", g_config_mod.config.pport_drive_strength, g_config.pport_drive_strength); + } + + int reinit_dma = g_config_mod.flags & (CF_MANUAL_DMA | CF_DMA_BUFFER_COUNT | CF_DMA_BUFFER_SIZE); + if (re_enum) + reinit_dma = 0; // Don't need to if re-enumerating + + if (g_config_mod.flags & CF_MANUAL_DMA) { +#ifdef ENABLE_MANUAL_DMA_XFER + msg("DMA transfers will be: %s (was: %s)", (g_config_mod.config.manual_dma ? "manual" : "auto"), (g_config.manual_dma ? "manual" : "auto")); + g_config.manual_dma = g_config_mod.config.manual_dma; +#else + msg("! Manual DMA transfers not compiled into FW"); +#endif // ENABLE_MANUAL_DMA_XFER + } + + if (g_config_mod.flags & CF_DMA_BUFFER_COUNT) { + msg("DMA buffer count will be: %d (was: %d)", g_config_mod.config.dma_buffer_count, g_config.dma_buffer_count); + g_config.dma_buffer_count = g_config_mod.config.dma_buffer_count; + } + + if (g_config_mod.flags & CF_DMA_BUFFER_SIZE) { + msg("DMA buffer size will be: %d (was: %d)", g_config_mod.config.dma_buffer_size, g_config.dma_buffer_size); + g_config.dma_buffer_size = g_config_mod.config.dma_buffer_size; + } + + if (g_config_mod.flags & CF_SB_BAUD_DIV) { +#ifdef ENABLE_FPGA_SB + LOCK(g_suart_lock); + sb_write(SUART_CLKDIV, g_config_mod.config.sb_baud_div); + UNLOCK(g_suart_lock); + msg("SUART_CLKDIV now: %d (was: %d)", g_config_mod.config.sb_baud_div, g_config.sb_baud_div); + g_config.sb_baud_div = g_config_mod.config.sb_baud_div; +#else + msg("! Failed to set SUART_CLKDIV: SB is disabled (still: %d)", g_config.sb_baud_div); +#endif // ENABLE_FPGA_SB } - //CyU3PUsbControlUsb2Support(); - //b200_fw_start() + if (g_config_mod.flags & CF_ENABLE_AS_SUPERSPEED) { + msg("Enable SuperSpeed: %s (was: %s)", (g_config_mod.config.enable_as_superspeed ? "yes" : "no"), (g_config.enable_as_superspeed ? "yes" : "no")); + g_config.enable_as_superspeed = g_config_mod.config.enable_as_superspeed; + } + + if (reinit_dma) { + if (g_app_running) { + msg("Stopping FW..."); + + b200_fw_stop(); + } + + msg("Starting FW..."); + + b200_fw_start(); + } + else // Shouldn't be re-init'ing AND re-enum'ing /* Connect the USB pins, and enable SuperSpeed (USB 3.0). */ if (re_enum) { - msg("Link up"); - CyU3PConnectState(CyTrue, CyTrue); // CHECK: Assuming all other important state will persist + msg("Connecting... (as SuperSpeed: %d)", g_config.enable_as_superspeed); + + if (CyU3PConnectState(CyTrue, (g_config.enable_as_superspeed != 0 ? CyTrue : CyFalse)) == CY_U3P_SUCCESS) { // CHECK: Assuming all other important state will persist + CyU3PUSBSpeed_t usb_speed = CyU3PUsbGetSpeed(); + msg("Link up (speed: USB %d)", (int)usb_speed); // MAGIC: Values happen to map + } + else + msg("! Failed to bring link up"); } - + counters_reset_usb_errors(); } else { @@ -2533,7 +2830,7 @@ void thread_re_enum_entry(uint32_t input) { update_error_counters(); #endif // !ENABLE_FPGA_SB } - + CyU3PThreadRelinquish(); } } @@ -2548,26 +2845,26 @@ void base16_encode(uint8_t v, char out[2], char first) { #ifdef ENABLE_FPGA_SB void thread_fpga_sb_poll_entry(uint32_t input) { //msg("thread_fpga_sb_poll_entry"); - + while (1) { uint16_t i; uint8_t has_change = 0; - + update_error_counters(); - + /*if (g_poll_last_phy_error_count > 0) has_change = 1; if (g_poll_last_link_error_count > 0) has_change = 1;*/ if (g_poll_last_phy_error_status != 0) has_change = 1; - + uint16_t idx = CyU3PUsbGetEventLogIndex(); // Current *write* pointer if (idx > (USB_EVENT_LOG_SIZE-1)) { msg("! USB event log idx = %i", (int)idx); break; } - + uint8_t has_usb_events = 0; // Assuming logging won't wrap around between get calls (i.e. buffer should be long enough) if (g_fpga_sb_last_usb_event_log_index != idx) { @@ -2578,7 +2875,7 @@ void thread_fpga_sb_poll_entry(uint32_t input) { break; } } - + if (has_usb_events == 0) { for (i = 0; i < idx; i++) { if (g_usb_event_log[i] != 0x14 && g_usb_event_log[i] != 0x15 && g_usb_event_log[i] != 0x16) { // CTRL, STATUS, ACKSETUP @@ -2597,15 +2894,15 @@ void thread_fpga_sb_poll_entry(uint32_t input) { } } } - + if (has_change || has_usb_events) { LOCK(g_suart_lock); - + sb_write(SUART_TXCHAR, UPT_USB_EVENTS); - + char out[3]; out[2] = '\0'; - + if (has_usb_events) { if (idx < g_fpga_sb_last_usb_event_log_index) { for (i = g_fpga_sb_last_usb_event_log_index; i < USB_EVENT_LOG_SIZE; i++) { @@ -2614,7 +2911,7 @@ void thread_fpga_sb_poll_entry(uint32_t input) { base16_encode(g_usb_event_log[i], out, 'A'); _sb_write_string(out); } - + for (i = 0; i < idx; i++) { if (g_usb_event_log[i] == 0x14 || g_usb_event_log[i] == 0x15 || g_usb_event_log[i] == 0x16) // CTRL, STATUS, ACKSETUP continue; @@ -2631,10 +2928,10 @@ void thread_fpga_sb_poll_entry(uint32_t input) { } } } - + // USB events: A-P,A-P // PHY error status: a,a-i - + if (g_poll_last_phy_error_status != 0) { uint32_t mask; size_t offset; @@ -2645,32 +2942,32 @@ void thread_fpga_sb_poll_entry(uint32_t input) { } } } - + /*char buf[6]; - + if (g_poll_last_phy_error_count > 0) { sb_write(SUART_TXCHAR, 'b'); snprintf(buf, sizeof(buf)-1, "%d", g_poll_last_phy_error_count); _sb_write_string(buf); } - + if (g_poll_last_link_error_count > 0) { sb_write(SUART_TXCHAR, 'c'); snprintf(buf, sizeof(buf)-1, "%d", g_poll_last_link_error_count); _sb_write_string(buf); }*/ - + _sb_write_string("\r\n"); - + UNLOCK(g_suart_lock); } - + g_poll_last_phy_error_count = 0; g_poll_last_link_error_count = 0; g_poll_last_phy_error_status = 0; - + g_fpga_sb_last_usb_event_log_index = idx; - + CyU3PThreadRelinquish(); } } @@ -2692,10 +2989,10 @@ void CyFxApplicationDefine(void) { #ifdef ENABLE_FPGA_SB void *fpga_sb_poll_thread_ptr; #endif // ENABLE_FPGA_SB - + g_counters.magic = COUNTER_MAGIC; - memset(&g_config, 0xFF, sizeof(g_config)); // Initialise to -1 - + //memset(&g_config, 0xFF, sizeof(g_config)); // Initialise to -1 + CyU3PMutexCreate(&g_log_lock, CYU3P_NO_INHERIT); CyU3PMutexCreate(&g_counters_lock, CYU3P_NO_INHERIT); CyU3PMutexCreate(&g_counters_dma_from_host_lock, CYU3P_NO_INHERIT); @@ -2706,36 +3003,37 @@ void CyFxApplicationDefine(void) { #ifdef ENABLE_USB_EVENT_LOGGING CyU3PUsbInitEventLog(g_usb_event_log, USB_EVENT_LOG_SIZE); #endif // ENABLE_USB_EVENT_LOGGING - + //////////////////////////////////////////////////////// - + /* Tell the host that we are ignoring it for a while. */ g_fx3_state = STATE_BUSY; - + /* Set the FX3 compatibility number. */ compat_num[0] = FX3_COMPAT_MAJOR; compat_num[1] = FX3_COMPAT_MINOR; - + /* Initialize the USB system. */ b200_usb_init(); - + /* Turn on the Watchdog Timer. */ CyU3PSysWatchDogConfigure(CyTrue, WATCHDOG_TIMEOUT); - + /* Go do something. Probably not useful, because you aren't configured. */ g_fx3_state = STATE_UNCONFIGURED; - + //////////////////////////////////////////////////////// - + b200_gpio_init(CyTrue); - + b200_enable_fpga_sb_gpio(CyTrue); - + msg("Compat: %d.%d", FX3_COMPAT_MAJOR, FX3_COMPAT_MINOR); msg("FX3 SDK: %d.%d.%d (build %d)", CYFX_VERSION_MAJOR, CYFX_VERSION_MINOR, CYFX_VERSION_PATCH, CYFX_VERSION_BUILD); - + msg("FW built: %s %s", __TIME__, __DATE__); + //////////////////////////////////////////////////////// - + /* Create the USB event group that we will use to track USB events from the * application thread. */ CyU3PEventCreate(&g_event_usb_config); @@ -2838,14 +3136,14 @@ int main(void) { status = CyU3PDeviceCacheControl(CyTrue, CyFalse, CyFalse); // Icache, Dcache, DMAcache if (status != CY_U3P_SUCCESS) goto handle_fatal_error; - + /* Configure the IO peripherals on the FX3. The gpioSimpleEn arrays are * bitmaps, where each bit represents the GPIO of the matching index - the * second array is index + 32. */ status = b200_set_io_matrix(CyTrue); if(status != CY_U3P_SUCCESS) goto handle_fatal_error; - + /* This function calls starts the RTOS kernel. * * ABANDON ALL HOPE, YE WHO ENTER HERE */ diff --git a/firmware/fx3/b200/b200_main.h b/firmware/fx3/b200/b200_main.h index 61048abc9..9fe8b9511 100644 --- a/firmware/fx3/b200/b200_main.h +++ b/firmware/fx3/b200/b200_main.h @@ -10,7 +10,7 @@ #include "cyu3types.h" #include "cyu3usbconst.h" -#define FX3_COMPAT_MAJOR (uint8_t)(7) +#define FX3_COMPAT_MAJOR (uint8_t)(8) #define FX3_COMPAT_MINOR (uint8_t)(0) /* GPIO Pins */ diff --git a/firmware/fx3/b200/b200_usb_descriptors.c b/firmware/fx3/b200/b200_usb_descriptors.c index 03dbce74a..53979219b 100644 --- a/firmware/fx3/b200/b200_usb_descriptors.c +++ b/firmware/fx3/b200/b200_usb_descriptors.c @@ -1,5 +1,5 @@ // -// Copyright 2013-2014 Ettus Research LLC +// Copyright 2013-2015 Ettus Research LLC // /* Define the USB 2.0 and USB 3.0 enumeration descriptions for the USRP B200 @@ -303,7 +303,7 @@ const uint8_t b200_usb_ss_config_desc[] __attribute__ ((aligned (32))) = 0x6A,0x00, /* Length of this descriptor and all sub descriptors */ 0x05, /* Number of interfaces */ 0x01, /* Configuration number */ - 0x00, /* COnfiguration string index */ + 0x00, /* Configuration string index */ 0x80, /* Config characteristics - D6: Self power; D5: Remote wakeup */ 0x01, /* Lie about the max power consumption (in 8mA unit) : 8mA */ @@ -424,6 +424,102 @@ const uint8_t b200_usb_ss_config_desc[] __attribute__ ((aligned (32))) = }; +const uint8_t b200_usb_ss_config_desc_new[] __attribute__ ((aligned (32))) = +{ + /* Configuration descriptor */ + 0x09, /* Descriptor size */ + CY_U3P_USB_CONFIG_DESCR, /* Configuration descriptor type */ + 0x4F,0x00, /* Length of this descriptor and all sub descriptors */ + 0x02, /* Number of interfaces */ + 0x01, /* Configuration number */ + 0x00, /* COnfiguration string index */ + 0x80, /* Config characteristics - D6: Self power; D5: Remote wakeup */ + 0x01, /* Lie about the max power consumption (in 8mA unit) : 8mA */ + + /* Interface descriptor */ + 0x09, /* Descriptor size */ + CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */ + 0x00, /* Interface number */ + 0x00, /* Alternate setting number */ + 0x00, /* Number of end points */ + 0xFF, /* Interface class */ + 0x00, /* Interface sub class */ + 0x00, /* Interface protocol code */ + 0x02, /* Interface descriptor string index */ + + /* Interface descriptor */ + 0x09, /* Descriptor size */ + CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */ + 0x01, /* Interface number */ + 0x00, /* Alternate setting number */ + 0x04, /* Number of end points */ + 0xFF, /* Interface class */ + 0x00, /* Interface sub class */ + 0x00, /* Interface protocol code */ + 0x02, /* Interface descriptor string index */ + + /* Endpoint descriptor for producer EP */ + 0x07, /* Descriptor size */ + CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */ + DATA_ENDPOINT_PRODUCER, /* Endpoint address and description */ + CY_U3P_USB_EP_BULK, /* Bulk endpoint type */ + 0x00,0x04, /* Max packet size = 1024 bytes */ + 0x00, /* Servicing interval for data transfers : 0 for bulk */ + + /* Super speed endpoint companion descriptor for producer EP */ + 0x06, /* Descriptor size */ + CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */ + (USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */ + 0x00, /* Max streams for bulk EP = 0 (No streams) */ + 0x00,0x00, /* Service interval for the EP : 0 for bulk */ + + /* Endpoint descriptor for consumer EP */ + 0x07, /* Descriptor size */ + CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */ + DATA_ENDPOINT_CONSUMER, /* Endpoint address and description */ + CY_U3P_USB_EP_BULK, /* Bulk endpoint type */ + 0x00,0x04, /* Max packet size = 1024 bytes */ + 0x00, /* Servicing interval for data transfers : 0 for Bulk */ + + /* Super speed endpoint companion descriptor for consumer EP */ + 0x06, /* Descriptor size */ + CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */ + (USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */ + 0x00, /* Max streams for bulk EP = 0 (No streams) */ + 0x00,0x00, /* Service interval for the EP : 0 for bulk */ + + /* Endpoint descriptor for producer EP */ + 0x07, /* Descriptor size */ + CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */ + CTRL_ENDPOINT_PRODUCER, /* Endpoint address and description */ + CY_U3P_USB_EP_BULK, /* Bulk endpoint type */ + 0x00,0x04, /* Max packet size = 1024 bytes */ + 0x00, /* Servicing interval for data transfers : 0 for bulk */ + + /* Super speed endpoint companion descriptor for producer EP */ + 0x06, /* Descriptor size */ + CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */ + (USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */ + 0x00, /* Max streams for bulk EP = 0 (No streams) */ + 0x00,0x00, /* Service interval for the EP : 0 for bulk */ + + /* Endpoint descriptor for consumer EP */ + 0x07, /* Descriptor size */ + CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */ + CTRL_ENDPOINT_CONSUMER, /* Endpoint address and description */ + CY_U3P_USB_EP_BULK, /* Bulk endpoint type */ + 0x00,0x04, /* Max packet size = 1024 bytes */ + 0x00, /* Servicing interval for data transfers : 0 for Bulk */ + + /* Super speed endpoint companion descriptor for consumer EP */ + 0x06, /* Descriptor size */ + CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */ + (USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */ + 0x00, /* Max streams for bulk EP = 0 (No streams) */ + 0x00,0x00 /* Service interval for the EP : 0 for bulk */ +}; + + /* Standard Language ID String Descriptor */ const uint8_t b200_string_lang_id_desc[] __attribute__ ((aligned (32))) = { diff --git a/firmware/octoclock/CMakeLists.txt b/firmware/octoclock/CMakeLists.txt index 80df0e9eb..0f2af35e9 100644 --- a/firmware/octoclock/CMakeLists.txt +++ b/firmware/octoclock/CMakeLists.txt @@ -31,7 +31,7 @@ if(NOT DEFINED PROGRAMMER) endif(NOT DEFINED PROGRAMMER) if(OCTOCLOCK_DEBUG) - message(STATUS "Debug enabled. Interrupts will be disabled.") + message(STATUS "Debug enabled.") add_definitions(-DDEBUG) endif(OCTOCLOCK_DEBUG) diff --git a/firmware/octoclock/bootloader/CMakeLists.txt b/firmware/octoclock/bootloader/CMakeLists.txt index 04bcfc492..7623a8698 100644 --- a/firmware/octoclock/bootloader/CMakeLists.txt +++ b/firmware/octoclock/bootloader/CMakeLists.txt @@ -49,7 +49,7 @@ add_custom_target( add_custom_target( upload_bootloader - ${AVRDUDE} -p atmega128 -c ${PROGRAMMER} -P usb -U efuse:w:0xFF:m -U hfuse:w:0x80:m -U lfuse:w:0xFF:m -U flash:w:octoclock_bootloader.hex:i + ${AVRDUDE} -p atmega128 -c ${PROGRAMMER} -P usb -U efuse:w:0xFF:m -U hfuse:w:0x80:m -U lfuse:w:0xEF:m -U flash:w:octoclock_bootloader.hex:i WORKING_DIRECTORY ${CMAKE_BINARY_DIR} DEPENDS octoclock_bootloader_hex COMMENT "Uploading OctoClock bootloader to device with ${PROGRAMMER}" diff --git a/firmware/octoclock/bootloader/main.c b/firmware/octoclock/bootloader/main.c index 5e2e6f17e..09f740d31 100644 --- a/firmware/octoclock/bootloader/main.c +++ b/firmware/octoclock/bootloader/main.c @@ -23,13 +23,13 @@ #include <avr/eeprom.h> #include <avr/io.h> #include <avr/pgmspace.h> +#include <avr/wdt.h> +#include <avrlibdefs.h> #include <octoclock.h> #include <debug.h> #include <network.h> -#include <util/delay.h> - #include <net/enc28j60.h> #include "octoclock/common.h" @@ -40,10 +40,19 @@ */ #define TIME_PASSED (TCNT1 > (TIMER1_ONE_SECOND*5) || (TIFR & _BV(TOV1))) -//States -static bool received_cmd = false; -static bool done_burning = false; +/* + * States + */ +static bool received_cmd = false; // Received "PREPARE_FW_BURN_CMD" signal +static bool done_burning = false; // Received "FINALIZE_BURNING_CMD" signal +static bool app_checked = false; // Ran validation check on firmware +/* + * After new firmware is burned onto the device, the bootloader calculates its + * CRC and burns it into the EEPROM. When the device boots, this CRC is used + * to validate the firmware before loading it. This struct represents how the + * information is stored in the EEPROM. + */ typedef struct { uint16_t fw_len; uint16_t fw_crc; @@ -51,15 +60,22 @@ typedef struct { static crc_info_t crc_info; +/* + * What actually burns the firmware onto the device. + * + * Source: http://www.atmel.com/webdoc/AVRLibcReferenceManual/group__avr__boot.html + */ static void boot_program_page(uint8_t *buf, uint16_t page){ - uint16_t i; + // Disable interrupts + uint8_t sreg = SREG; + cli(); eeprom_busy_wait(); boot_page_erase(page); boot_spm_busy_wait(); // Wait until the memory is erased. - for(i = 0; i < SPM_PAGESIZE; i += 2){ + for(uint16_t i = 0; i < SPM_PAGESIZE; i += 2){ // Set up little-endian word. uint16_t w = *buf++; w += ((*buf++) << 8); @@ -68,36 +84,31 @@ static void boot_program_page(uint8_t *buf, uint16_t page){ } boot_page_write(page); // Store buffer in flash page. - boot_spm_busy_wait(); // Wait until the memory is written. + boot_spm_busy_wait(); // Wait until the memory is written. // Reenable RWW-section again. We need this if we want to jump back // to the application after bootloading. boot_rww_enable(); + + // Restore interrupt state + SREG = sreg; + sei(); } +/* + * Load firmware at given address into packet to send to host. + */ static void read_firmware(uint16_t addr, octoclock_packet_t *pkt_out){ for(size_t i = 0; i < SPM_PAGESIZE; i++){ pkt_out->data[i] = pgm_read_byte(addr+i); } } -void handle_udp_query_packet( - struct socket_address src, struct socket_address dst, - unsigned char *payload, int payload_len -){ - const octoclock_packet_t *pkt_in = (octoclock_packet_t*)payload; - - //Respond to query packets - if(pkt_in->code == OCTOCLOCK_QUERY_CMD){ - octoclock_packet_t pkt_out; - pkt_out.proto_ver = OCTOCLOCK_BOOTLOADER_PROTO_VER; - pkt_out.sequence = pkt_in->sequence; - pkt_out.code = OCTOCLOCK_QUERY_ACK; - pkt_out.len = 0; - send_udp_pkt(OCTOCLOCK_UDP_CTRL_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); - } -} - +/* + * Calculate the CRC of the current firmware. + * + * Adapted from _crc16_update in <util/crc16.h>. + */ static void calculate_crc(uint16_t *crc, uint16_t len){ *crc = 0xFFFF; @@ -110,6 +121,11 @@ static void calculate_crc(uint16_t *crc, uint16_t len){ } } +/* + * Calculate the CRC of the current firmware. If it matches the + * CRC burned into the EEPROM, the firmware is considered valid, + * and the bootloader can load it. + */ static bool valid_app(){ crc_info_t crc_eeprom_info; eeprom_read_block(&crc_eeprom_info, (void*)OCTOCLOCK_EEPROM_APP_LEN, 4); @@ -118,6 +134,26 @@ static bool valid_app(){ return (crc_info.fw_crc == crc_eeprom_info.fw_crc); } +/* + * UDP handlers + */ +void handle_udp_query_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +){ + const octoclock_packet_t *pkt_in = (octoclock_packet_t*)payload; + + // Respond to uhd::device::find(), identify as bootloader + if(pkt_in->code == OCTOCLOCK_QUERY_CMD){ + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_BOOTLOADER_PROTO_VER; + pkt_out.sequence = pkt_in->sequence; + pkt_out.code = OCTOCLOCK_QUERY_ACK; + pkt_out.len = 0; + send_udp_pkt(OCTOCLOCK_UDP_CTRL_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); + } +} + void handle_udp_fw_packet( struct socket_address src, struct socket_address dst, unsigned char *payload, int payload_len @@ -132,24 +168,27 @@ void handle_udp_fw_packet( case PREPARE_FW_BURN_CMD: received_cmd = true; done_burning = false; + crc_info.fw_crc = pkt_in->crc; crc_info.fw_len = pkt_in->len; pkt_out.code = FW_BURN_READY_ACK; break; + // Burn firmware sent from the host case FILE_TRANSFER_CMD: boot_program_page(pkt_in->data, pkt_in->addr); pkt_out.code = FILE_TRANSFER_ACK; + pkt_out.addr = pkt_in->addr; break; + // Send firmware back to the host for verification case READ_FW_CMD: pkt_out.code = READ_FW_ACK; read_firmware(pkt_in->addr, &pkt_out); break; + // Calculate the CRC of the new firmware and finish case FINALIZE_BURNING_CMD: - //With stuff verified, burn CRC info into EEPROM done_burning = true; - calculate_crc(&(crc_info.fw_crc), crc_info.fw_len); eeprom_write_block(&crc_info, (void*)OCTOCLOCK_EEPROM_APP_LEN, 4); pkt_out.code = FINALIZE_BURNING_ACK; break; @@ -170,11 +209,12 @@ void handle_udp_eeprom_packet( pkt_out.sequence = pkt_in->sequence; pkt_out.len = 0; + // Restore OctoClock's EEPROM to factory state if(pkt_in->proto_ver == OCTOCLOCK_FW_COMPAT_NUM){ switch(pkt_in->code){ case CLEAR_EEPROM_CMD: received_cmd = true; - uint8_t blank_eeprom[103]; + uint8_t blank_eeprom[103]; // 103 is offset of CRC info memset(blank_eeprom, 0xFF, 103); eeprom_write_block(blank_eeprom, 0, 103); pkt_out.code = CLEAR_EEPROM_ACK; @@ -189,28 +229,45 @@ void handle_udp_eeprom_packet( int main(void){ - asm("cli"); + // Disable watchdog timer + wdt_disable(); + + // Give interrupts to bootloader + MCUCR = (1<<IVCE); + MCUCR = (1<<IVSEL); + cli(); - //Initialization + // Atmega128 setup_atmel_io_ports(); + + // Start timer + TIMER1_INIT(); + + // Ethernet stack network_init(); - init_udp_listeners(); register_udp_listener(OCTOCLOCK_UDP_CTRL_PORT, handle_udp_query_packet); register_udp_listener(OCTOCLOCK_UDP_FW_PORT, handle_udp_fw_packet); register_udp_listener(OCTOCLOCK_UDP_EEPROM_PORT, handle_udp_eeprom_packet); - //Turn LED's on to show we're in the bootloader + // Turn LED's on to show we're in the bootloader PORTC |= 0x20; PORTC |= (0x20<<1); PORTC |= (0x20<<2); - TIMER1_INIT(); - bool app_checked = false; - + /* + * This loop determines whether the OctoClock will remain in its bootloader + * state or if it will load the main firmware. After five seconds, it will + * check to see if valid firmware is installed. If so, it will immediately + * load it. Otherwise, it will remain here until firmware is installed. + * + * This process can be stopped by an instruction from the firmware burner + * utility, at which point the OctoClock will remain in bootloader state until + * instructed by the utility to exit the loop and load the new firmware. + */ while(true){ if(done_burning){ if(valid_app()) break; - else done_burning = false; //Burning somehow failed and wasn't caught + else done_burning = false; // Burning somehow failed and wasn't caught } if(!app_checked && !received_cmd && TIME_PASSED){ app_checked = true; @@ -220,16 +277,18 @@ int main(void){ network_check(); } - //Turn LED's off before moving to application + // Turn LED's off before moving to application PORTC &= ~0x20; PORTC &= ~(0x20<<1); PORTC &= ~(0x20<<2); /* - * Whether the bootloader reaches here through five seconds of inactivity - * or after a firmware burn just finished, it can be assumed that the application - * is valid. + * At this point, the bootloader has determined that there is valid + * firmware installed on the device and that it is OK to load it. */ + TIMER1_DISABLE(); + MCUCR = (1<<IVCE); + MCUCR = 0; + cli(); asm("jmp 0000"); - return 0; //Will never get here, but AVR-GCC needs it } diff --git a/firmware/octoclock/include/clkdist.h b/firmware/octoclock/include/clkdist.h index 633df9ddf..357daf37b 100644 --- a/firmware/octoclock/include/clkdist.h +++ b/firmware/octoclock/include/clkdist.h @@ -23,7 +23,7 @@ #include <octoclock.h> typedef enum { - Reg0, Reg1, Reg2, Reg3, Reg4, Reg5, Reg6, Reg7, + Reg0=0, Reg1, Reg2, Reg3, Reg4, Reg5, Reg6, Reg7, Reg8_Status_Control, Read_Command=0xE, RAM_EEPROM_Unlock=0x1F, @@ -46,6 +46,8 @@ void reset_TI_CDCE18005(void); uint32_t get_TI_CDCE18005(CDCE18005 which_register); +void set_TI_CDCE18005(CDCE18005 which_register, uint32_t bits); + bool check_TI_CDCE18005(TI_Input_10_MHz which_input, CDCE18005 which_register); #endif /* _CLKDIST_H_ */ diff --git a/firmware/octoclock/include/debug.h b/firmware/octoclock/include/debug.h index ee0618bc6..1f69896f0 100644 --- a/firmware/octoclock/include/debug.h +++ b/firmware/octoclock/include/debug.h @@ -66,8 +66,8 @@ DEBUG_LOG_HEX(((uint8_t*)&num)[0]); #define DEBUG_LOG_INT(num) DEBUG_LOG_HEX_NNL(((uint8_t*)&num)[3]); \ - DEBUG_LOG_HEX(((uint8_t*)&num)[2]); \ - DEBUG_LOG_HEX(((uint8_t*)&num)[1]); \ + DEBUG_LOG_HEX_NNL(((uint8_t*)&num)[2]); \ + DEBUG_LOG_HEX_NNL(((uint8_t*)&num)[1]); \ DEBUG_LOG_HEX(((uint8_t*)&num)[0]); #else diff --git a/firmware/octoclock/include/gpsdo.h b/firmware/octoclock/include/gpsdo.h index fc7d87324..df0440404 100644 --- a/firmware/octoclock/include/gpsdo.h +++ b/firmware/octoclock/include/gpsdo.h @@ -27,6 +27,4 @@ gpsdo_cache_state_t gpsdo_state; void send_gpsdo_cmd(char* buf, uint8_t size); -void process_gpsdo_output(void); - #endif /* _GPSDO_H_ */ diff --git a/firmware/octoclock/include/net/enc28j60.h b/firmware/octoclock/include/net/enc28j60.h index 463303f3c..dc58b451b 100644 --- a/firmware/octoclock/include/net/enc28j60.h +++ b/firmware/octoclock/include/net/enc28j60.h @@ -1,299 +1,276 @@ -/*! \file enc28j60.h \brief Microchip ENC28J60 Ethernet Interface Driver. */ -//***************************************************************************** -// -// File Name : 'enc28j60.h' -// Title : Microchip ENC28J60 Ethernet Interface Driver -// Author : Pascal Stang (c)2005 -// Created : 9/22/2005 -// Revised : 9/22/2005 -// Version : 0.1 -// Target MCU : Atmel AVR series -// Editor Tabs : 4 -// -/// \ingroup network -/// \defgroup enc28j60 Microchip ENC28J60 Ethernet Interface Driver (enc28j60.c) -/// \code #include "net/enc28j60.h" \endcode -/// \par Overview -/// This driver provides initialization and transmit/receive -/// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. -/// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin -/// chip, using an SPI interface to the host processor. -/// -// -//***************************************************************************** -//@{ +/* + * Copyright 2015 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ -#ifndef ENC28J60_H -#define ENC28J60_H +#ifndef _NET_ENC28J60_H_ +#define _NET_ENC28J60_H_ -#include <avrlibdefs.h> +#include <avr/io.h> -#include "enc28j60conf.h" +#define SPI_DDR DDRB +#define SPI_PORT PORTB +#define SPI_CS 0 +#define SPI_MOSI 2 +#define SPI_MISO 3 +#define SPI_SCK 1 -// ENC28J60 Control Registers -// Control register definitions are a combination of address, -// bank number, and Ethernet/MAC/PHY indicator bits. -// - Register address (bits 0-4) -// - Bank number (bits 5-6) -// - MAC/PHY indicator (bit 7) -#define ADDR_MASK 0x1F -#define BANK_MASK 0x60 -#define SPRD_MASK 0x80 -// All-bank registers -#define EIE 0x1B -#define EIR 0x1C -#define ESTAT 0x1D -#define ECON2 0x1E -#define ECON1 0x1F -// Bank 0 registers -#define ERDPTL (0x00|0x00) -#define ERDPTH (0x01|0x00) -#define EWRPTL (0x02|0x00) -#define EWRPTH (0x03|0x00) -#define ETXSTL (0x04|0x00) -#define ETXSTH (0x05|0x00) -#define ETXNDL (0x06|0x00) -#define ETXNDH (0x07|0x00) -#define ERXSTL (0x08|0x00) -#define ERXSTH (0x09|0x00) -#define ERXNDL (0x0A|0x00) -#define ERXNDH (0x0B|0x00) -#define ERXRDPTL (0x0C|0x00) -#define ERXRDPTH (0x0D|0x00) -#define ERXWRPTL (0x0E|0x00) -#define ERXWRPTH (0x0F|0x00) -#define EDMASTL (0x10|0x00) -#define EDMASTH (0x11|0x00) -#define EDMANDL (0x12|0x00) -#define EDMANDH (0x13|0x00) -#define EDMADSTL (0x14|0x00) -#define EDMADSTH (0x15|0x00) -#define EDMACSL (0x16|0x00) -#define EDMACSH (0x17|0x00) -// Bank 1 registers -#define EHT0 (0x00|0x20) -#define EHT1 (0x01|0x20) -#define EHT2 (0x02|0x20) -#define EHT3 (0x03|0x20) -#define EHT4 (0x04|0x20) -#define EHT5 (0x05|0x20) -#define EHT6 (0x06|0x20) -#define EHT7 (0x07|0x20) -#define EPMM0 (0x08|0x20) -#define EPMM1 (0x09|0x20) -#define EPMM2 (0x0A|0x20) -#define EPMM3 (0x0B|0x20) -#define EPMM4 (0x0C|0x20) -#define EPMM5 (0x0D|0x20) -#define EPMM6 (0x0E|0x20) -#define EPMM7 (0x0F|0x20) -#define EPMCSL (0x10|0x20) -#define EPMCSH (0x11|0x20) -#define EPMOL (0x14|0x20) -#define EPMOH (0x15|0x20) -#define EWOLIE (0x16|0x20) -#define EWOLIR (0x17|0x20) -#define ERXFCON (0x18|0x20) -#define EPKTCNT (0x19|0x20) -// Bank 2 registers -#define MACON1 (0x00|0x40|0x80) -#define MACON2 (0x01|0x40|0x80) -#define MACON3 (0x02|0x40|0x80) -#define MACON4 (0x03|0x40|0x80) -#define MABBIPG (0x04|0x40|0x80) -#define MAIPGL (0x06|0x40|0x80) -#define MAIPGH (0x07|0x40|0x80) -#define MACLCON1 (0x08|0x40|0x80) -#define MACLCON2 (0x09|0x40|0x80) -#define MAMXFLL (0x0A|0x40|0x80) -#define MAMXFLH (0x0B|0x40|0x80) -#define MAPHSUP (0x0D|0x40|0x80) -#define MICON (0x11|0x40|0x80) -#define MICMD (0x12|0x40|0x80) -#define MIREGADR (0x14|0x40|0x80) -#define MIWRL (0x16|0x40|0x80) -#define MIWRH (0x17|0x40|0x80) -#define MIRDL (0x18|0x40|0x80) -#define MIRDH (0x19|0x40|0x80) -// Bank 3 registers -#define MAADR1 (0x00|0x60|0x80) -#define MAADR0 (0x01|0x60|0x80) -#define MAADR3 (0x02|0x60|0x80) -#define MAADR2 (0x03|0x60|0x80) -#define MAADR5 (0x04|0x60|0x80) -#define MAADR4 (0x05|0x60|0x80) -#define EBSTSD (0x06|0x60) -#define EBSTCON (0x07|0x60) -#define EBSTCSL (0x08|0x60) -#define EBSTCSH (0x09|0x60) -#define MISTAT (0x0A|0x60|0x80) -#define EREVID (0x12|0x60) -#define ECOCON (0x15|0x60) -#define EFLOCON (0x17|0x60) -#define EPAUSL (0x18|0x60) -#define EPAUSH (0x19|0x60) -// PHY registers -#define PHCON1 0x00 -#define PHSTAT1 0x01 -#define PHHID1 0x02 -#define PHHID2 0x03 -#define PHCON2 0x10 -#define PHSTAT2 0x11 -#define PHIE 0x12 -#define PHIR 0x13 -#define PHLCON 0x14 +// Register Masks +#define ADDR_MASK 0x1F +#define BANK_MASK 0x60 +#define SPRD_MASK 0x80 -// ENC28J60 EIE Register Bit Definitions -#define EIE_INTIE 0x80 -#define EIE_PKTIE 0x40 -#define EIE_DMAIE 0x20 -#define EIE_LINKIE 0x10 -#define EIE_TXIE 0x08 -#define EIE_WOLIE 0x04 -#define EIE_TXERIE 0x02 -#define EIE_RXERIE 0x01 -// ENC28J60 EIR Register Bit Definitions -#define EIR_PKTIF 0x40 -#define EIR_DMAIF 0x20 -#define EIR_LINKIF 0x10 -#define EIR_TXIF 0x08 -#define EIR_WOLIF 0x04 -#define EIR_TXERIF 0x02 -#define EIR_RXERIF 0x01 -// ENC28J60 ESTAT Register Bit Definitions -#define ESTAT_INT 0x80 -#define ESTAT_LATECOL 0x10 -#define ESTAT_RXBUSY 0x04 -#define ESTAT_TXABRT 0x02 -#define ESTAT_CLKRDY 0x01 -// ENC28J60 ECON2 Register Bit Definitions -#define ECON2_AUTOINC 0x80 -#define ECON2_PKTDEC 0x40 -#define ECON2_PWRSV 0x20 -#define ECON2_VRPS 0x08 -// ENC28J60 ECON1 Register Bit Definitions -#define ECON1_TXRST 0x80 -#define ECON1_RXRST 0x40 -#define ECON1_DMAST 0x20 -#define ECON1_CSUMEN 0x10 -#define ECON1_TXRTS 0x08 -#define ECON1_RXEN 0x04 -#define ECON1_BSEL1 0x02 -#define ECON1_BSEL0 0x01 -// ENC28J60 MACON1 Register Bit Definitions -#define MACON1_LOOPBK 0x10 -#define MACON1_TXPAUS 0x08 -#define MACON1_RXPAUS 0x04 -#define MACON1_PASSALL 0x02 -#define MACON1_MARXEN 0x01 -// ENC28J60 MACON2 Register Bit Definitions -#define MACON2_MARST 0x80 -#define MACON2_RNDRST 0x40 -#define MACON2_MARXRST 0x08 -#define MACON2_RFUNRST 0x04 -#define MACON2_MATXRST 0x02 -#define MACON2_TFUNRST 0x01 -// ENC28J60 MACON3 Register Bit Definitions -#define MACON3_PADCFG2 0x80 -#define MACON3_PADCFG1 0x40 -#define MACON3_PADCFG0 0x20 -#define MACON3_TXCRCEN 0x10 -#define MACON3_PHDRLEN 0x08 -#define MACON3_HFRMLEN 0x04 -#define MACON3_FRMLNEN 0x02 -#define MACON3_FULDPX 0x01 -// ENC28J60 MICMD Register Bit Definitions -#define MICMD_MIISCAN 0x02 -#define MICMD_MIIRD 0x01 -// ENC28J60 MISTAT Register Bit Definitions -#define MISTAT_NVALID 0x04 -#define MISTAT_SCAN 0x02 -#define MISTAT_BUSY 0x01 -// ENC28J60 PHY PHCON1 Register Bit Definitions -#define PHCON1_PRST 0x8000 -#define PHCON1_PLOOPBK 0x4000 -#define PHCON1_PPWRSV 0x0800 -#define PHCON1_PDPXMD 0x0100 -// ENC28J60 PHY PHSTAT1 Register Bit Definitions -#define PHSTAT1_PFDPX 0x1000 -#define PHSTAT1_PHDPX 0x0800 -#define PHSTAT1_LLSTAT 0x0004 -#define PHSTAT1_JBSTAT 0x0002 -// ENC28J60 PHY PHCON2 Register Bit Definitions -#define PHCON2_FRCLINK 0x4000 -#define PHCON2_TXDIS 0x2000 -#define PHCON2_JABBER 0x0400 -#define PHCON2_HDLDIS 0x0100 +// All Banks Registers +#define EIE 0x1B +#define EIR 0x1C +#define ESTAT 0x1D +#define ECON2 0x1E +#define ECON1 0x1F -// ENC28J60 Packet Control Byte Bit Definitions -#define PKTCTRL_PHUGEEN 0x08 -#define PKTCTRL_PPADEN 0x04 -#define PKTCTRL_PCRCEN 0x02 -#define PKTCTRL_POVERRIDE 0x01 +// Bank 0 Registers +#define ERDPTL 0x00 +#define ERDPTH 0x01 +#define EWRPTL 0x02 +#define EWRPTH 0x03 +#define ETXSTL 0x04 +#define ETXSTH 0x05 +#define ETXNDL 0x06 +#define ETXNDH 0x07 +#define ERXSTL 0x08 +#define ERXSTH 0x09 +#define ERXNDL 0x0A +#define ERXNDH 0x0B +#define ERXRDPTL 0x0C +#define ERXRDPTH 0x0D +#define ERXWRPTL 0x0E +#define ERXWRPTH 0x0F +#define EDMASTL 0x10 +#define EDMASTH 0x11 +#define EDMANDL 0x12 +#define EDMANDH 0x13 +#define EDMADSTL 0x14 +#define EDMADSTH 0x15 +#define EDMACSL 0x16 +#define EDMACSH 0x17 -// SPI operation codes -#define ENC28J60_READ_CTRL_REG 0x00 -#define ENC28J60_READ_BUF_MEM 0x3A -#define ENC28J60_WRITE_CTRL_REG 0x40 -#define ENC28J60_WRITE_BUF_MEM 0x7A -#define ENC28J60_BIT_FIELD_SET 0x80 -#define ENC28J60_BIT_FIELD_CLR 0xA0 -#define ENC28J60_SOFT_RESET 0xFF +// Bank 1 Registers +#define EHT0 0x20 +#define EHT1 0x21 +#define EHT2 0x22 +#define EHT3 0x23 +#define EHT4 0x24 +#define EHT5 0x25 +#define EHT6 0x26 +#define EHT7 0x27 +#define EPMM0 0x28 +#define EPMM1 0x29 +#define EPMM2 0x2A +#define EPMM3 0x2B +#define EPMM4 0x2C +#define EPMM5 0x2D +#define EPMM6 0x2E +#define EPMM7 0x2F +#define EPMCSL 0x30 +#define EPMCSH 0x31 +#define EPMOL 0x34 +#define EPMOH 0x35 +#define EWOLIE 0x36 +#define EWOLIR 0x37 +#define ERXFCON 0x38 +#define EPKTCNT 0x39 +// Bank 2 Register +#define MACON1 0xC0 +#define MACON2 0xC1 +#define MACON3 0xC2 +#define MACON4 0xC3 +#define MABBIPG 0xC4 +#define MAIPGL 0xC6 +#define MAIPGH 0xC7 +#define MACLCON1 0xC8 +#define MACLCON2 0xC9 +#define MAMXFLL 0xCA +#define MAMXFLH 0xCB +#define MAPHSUP 0xCD +#define MICON 0xD1 +#define MICMD 0xD2 +#define MIREGADR 0xD4 +#define MIWRL 0xD6 +#define MIWRH 0xD7 +#define MIRDL 0xD8 +#define MIRDH 0xD9 -// buffer boundaries applied to internal 8K ram -// entire available packet buffer space is allocated -#define TXSTART_INIT 0x0000 // start TX buffer at 0 -#define RXSTART_INIT 0x0600 // give TX buffer space for one full ethernet frame (~1500 bytes) -#define RXSTOP_INIT 0x1FFF // receive buffer gets the rest +// Bank 3 Registers +#define MAADR1 0xE0 +#define MAADR0 0xE1 +#define MAADR3 0xE2 +#define MAADR2 0xE3 +#define MAADR5 0xE4 +#define MAADR4 0xE5 +#define EBSTSD 0x66 +#define EBSTCON 0x67 +#define EBSTCSL 0x68 +#define EBSTCSH 0x69 +#define MISTAT 0xEA +#define EREVID 0x72 +#define ECOCON 0x75 +#define EFLOCON 0x77 +#define EPAUSL 0x78 +#define EPAUSH 0x79 -#define MAX_FRAMELEN 1518 // maximum ethernet frame length +// PHY Registers +#define PHCON1 0x00 +#define PHSTAT1 0x01 +#define PHHID1 0x02 +#define PHHID2 0x03 +#define PHCON2 0x10 +#define PHSTAT2 0x11 +#define PHIE 0x12 +#define PHIR 0x13 +#define PHLCON 0x14 -// Ethernet constants -#define ETHERNET_MIN_PACKET_LENGTH 0x3C -//#define ETHERNET_HEADER_LENGTH 0x0E +// ERXFCON bit definitions +#define UCEN 0x80 +#define ANDOR 0x40 +#define CRCEN 0x20 +#define PMEN 0x10 +#define MPEN 0x08 +#define HTEN 0x04 +#define MCEN 0x02 +#define BCEN 0x01 -// setup ports for I/O -//void ax88796SetupPorts(void); +// EIE bit definitions +#define INTIE 0x80 +#define PKTIE 0x40 +#define DMAIE 0x20 +#define LINKIE 0x10 +#define TXIE 0x08 +#define WOLIE 0x04 +#define TXERIE 0x02 +#define RXERIE 0x01 -//! do a ENC28J60 read operation -u08 enc28j60ReadOp(u08 op, u08 address); -//! do a ENC28J60 write operation -void enc28j60WriteOp(u08 op, u08 address, u08 data); -//! read the packet buffer memory -void enc28j60ReadBuffer(u16 len, u08* data); -//! write the packet buffer memory -void enc28j60WriteBuffer(u16 len, u08* data); -//! set the register bank for register at address -void enc28j60SetBank(u08 address); -//! read ax88796 register -u08 enc28j60Read(u08 address); -//! write ax88796 register -void enc28j60Write(u08 address, u08 data); -//! read a PHY register -u16 enc28j60PhyRead(u08 address); -//! write a PHY register -void enc28j60PhyWrite(u08 address, u16 data); +// EIR bit definitions +#define PKTIF 0x40 +#define DMAIF 0x20 +#define LINKIF 0x10 +#define TXIF 0x08 +#define WOLIF 0x04 +#define TXERIF 0x02 +#define RXERIF 0x01 -//! initialize the ethernet interface for transmit/receive -void enc28j60Init(u08* macaddr); +// ESTAT bit definitions +#define INT 0x80 +#define LATECOL 0x10 +#define RXBUSY 0x04 +#define TXABRT 0x02 +#define CLKRDY 0x01 -//! Packet transmit function. -/// Sends a packet on the network. It is assumed that the packet is headed by a valid ethernet header. -/// \param len Length of packet in bytes. -/// \param packet Pointer to packet data. -/// \param len2 Length of the secound packet in bytes, can be 0. -/// \param packet2 Pointer to the secound packet data, can be NULL. -void enc28j60PacketSend(unsigned int len1, unsigned char* packet1, unsigned int len2, unsigned char* packet2); +// ECON2 bit definitions +#define AUTOINC 0x80 +#define PKTDEC 0x40 +#define PWRSV 0x20 +#define VRPS 0x08 -//! Packet receive function. -/// Gets a packet from the network receive buffer, if one is available. -/// The packet will by headed by an ethernet header. -/// \param maxlen The maximum acceptable length of a retrieved packet. -/// \param buf Pointer to buffer. -/// \return Packet length in bytes if a packet was retrieved, zero otherwise. -unsigned int enc28j60PacketReceive(unsigned int maxlen, u08* buf); +// ECON1 bit definitions +#define TXRST 0x80 +#define RXRST 0x40 +#define DMAST 0x20 +#define CSUMEN 0x10 +#define TXRTS 0x08 +#define ENCRXEN 0x04 +#define BSEL1 0x02 +#define BSEL0 0x01 -#endif -//@} +// MACON1 bit definitions +#define LOOPBK 0x10 +#define TXPAUS 0x08 +#define RXPAUS 0x04 +#define PASSALL 0x02 +#define MARXEN 0x01 +// MACON2 bit definitions +#define MARST 0x80 +#define RNDRST 0x40 +#define MARXRST 0x08 +#define RFUNRST 0x04 +#define MATXRST 0x02 +#define TFUNRST 0x01 + +// MACON3 bit definitions +#define PADCFG2 0x80 +#define PADCFG1 0x40 +#define PADCFG0 0x20 +#define TXCRCEN 0x10 +#define PHDRLEN 0x08 +#define HFRMLEN 0x04 +#define FRMLNEN 0x02 +#define FULDPX 0x01 + +// MICMD bit definitions +#define MIISCAN 0x02 +#define MIIRD 0x01 + +// MISTAT bit definitions +#define NVALID 0x04 +#define SCAN 0x02 +#define BUSY 0x01 + +// PHCON1 bit definitions +#define PRST 0x8000 +#define PLOOPBK 0x4000 +#define PPWRSV 0x0800 +#define PDPXMD 0x0100 + +// PHSTAT1 bit definitions +#define PFDPX 0x1000 +#define PHDPX 0x0800 +#define LLSTAT 0x0004 +#define JBSTAT 0x0002 + +// PHCON2 bit definitions +#define FRCLINK 0x4000 +#define TXDIS 0x2000 +#define JABBER 0x0400 +#define HDLDIS 0x0100 + +// Packet Control bit Definitions +#define PHUGEEN 0x08 +#define PPADEN 0x04 +#define PCRCEN 0x02 +#define POVERRIDE 0x01 + +// SPI Instruction Set +#define RCR 0x00 // Read Control Register +#define RBM 0x3A // Read Buffer Memory +#define WCR 0x40 // Write Control Register +#define WBM 0x7A // Write Buffer Memory +#define BFS 0x80 // Bit Field Set +#define BFC 0xA0 // Bit Field Clear +#define SC 0xFF // Soft Reset + +// Buffer +#define RXSTART_INIT 0x0000 +#define RXSTOP_INIT (0x1FFF-0x0600-1) +#define TXSTART_INIT (0x1FFF-0x0600) +#define TXSTOP_INIT 0x1FFF +#define MAX_FRAMELEN 1500 + +void enc28j60_init(uint8_t* mac_addr); + +uint16_t enc28j60_recv(uint8_t* buffer, uint16_t max_len); + +void enc28j60_send(uint8_t* buffer, uint16_t len); + +#endif /* _NET_ENC28J60_H_ */ diff --git a/firmware/octoclock/include/net/enc28j60conf.h b/firmware/octoclock/include/net/enc28j60conf.h deleted file mode 100644 index 0acf5473c..000000000 --- a/firmware/octoclock/include/net/enc28j60conf.h +++ /dev/null @@ -1,49 +0,0 @@ -/*! \file enc28j60conf.h \brief Microchip ENC28J60 Ethernet Interface Driver Configuration. */ -//***************************************************************************** -// -// File Name : 'enc28j60conf.h' -// Title : Microchip ENC28J60 Ethernet Interface Driver Configuration -// Author : Pascal Stang -// Created : 10/5/2004 -// Revised : 8/22/2005 -// Version : 0.1 -// Target MCU : Atmel AVR series -// Editor Tabs : 4 -// -// Description : This driver provides initialization and transmit/receive -// functions for the ENC28J60 10Mb Ethernet Controller and PHY. -// -// This code is distributed under the GNU Public License -// which can be found at http://www.gnu.org/licenses/gpl.txt -// -//***************************************************************************** - -#ifndef ENC28J60CONF_H -#define ENC28J60CONF_H - -#include <stdint.h> -typedef uint8_t u08; -typedef uint16_t u16; -typedef uint32_t u32; - -// ENC28J60 SPI port -#define ENC28J60_SPI_PORT PORTB -#define ENC28J60_SPI_DDR DDRB -#define ENC28J60_SPI_SCK PORTB1 -#define ENC28J60_SPI_MOSI PORTB2 -#define ENC28J60_SPI_MISO PORTB3 -#define ENC28J60_SPI_SS PORTB0 -// ENC28J60 control port -#define ENC28J60_CONTROL_PORT PORTB -#define ENC28J60_CONTROL_DDR DDRB -#define ENC28J60_CONTROL_CS PORTB0 - -// MAC address for this interface -#define ENC28J60_MAC0 '0' -#define ENC28J60_MAC1 'F' -#define ENC28J60_MAC2 'F' -#define ENC28J60_MAC3 'I' -#define ENC28J60_MAC4 'C' -#define ENC28J60_MAC5 'E' - -#endif /* ENC28J60CONF_H */ diff --git a/firmware/octoclock/include/net/eth_mac_addr.h b/firmware/octoclock/include/net/eth_mac_addr.h index 0c790aa4f..78986bf04 100644 --- a/firmware/octoclock/include/net/eth_mac_addr.h +++ b/firmware/octoclock/include/net/eth_mac_addr.h @@ -21,11 +21,8 @@ #include <stdint.h> // Ethernet MAC address - -#pragma pack(push,1) typedef struct { uint8_t addr[6]; -} eth_mac_addr_t; -#pragma pack(pop) +} eth_mac_addr_t __attribute__((aligned(1))); #endif /* INCLUDED_ETH_MAC_ADDR_H */ diff --git a/firmware/octoclock/include/network.h b/firmware/octoclock/include/network.h index 83e398bc5..6d126a197 100644 --- a/firmware/octoclock/include/network.h +++ b/firmware/octoclock/include/network.h @@ -69,17 +69,11 @@ #define _IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (_IPH_TTL(hdr) << 8))) #define _IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) -bool using_network_defaults; +volatile bool using_network_defaults; // Ethernet I/O buffers -uint8_t buf_in[512]; -uint8_t buf_out[512]; - -// Default values loaded if EEPROM is incomplete -static const uint32_t blank_eeprom_ip = _IP(255,255,255,255); -static const uint32_t default_ip = _IP(192,168,10,3); -static const uint32_t default_dr = _IP(192,168,10,1); -static const uint32_t default_netmask = _IP(255,255,255,0); +#define ETH_BUF_SIZE 512 +uint8_t eth_buf[ETH_BUF_SIZE]; typedef void (*udp_receiver_t)(struct socket_address src, struct socket_address dst, unsigned char *payload, int payload_len); diff --git a/firmware/octoclock/include/octoclock.h b/firmware/octoclock/include/octoclock.h index 849ab7f96..34cad1c12 100644 --- a/firmware/octoclock/include/octoclock.h +++ b/firmware/octoclock/include/octoclock.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Ettus Research LLC + * Copyright 2014-2015 Ettus Research LLC * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,26 +24,21 @@ #include <stdint.h> // Define frequency -#define F_CPU 12500000UL +#define F_CPU 7372800UL /* - * Timer 0 (8-bit) - * * Set prescaler to 8 - * * Enable overflow interrupt - * * Set timer to 0 - */ -#define TIMER0_INIT() TCCR0 = (1 << CS01); \ - TIMSK |= (1 << TOIE0); \ - TCNT0 = 0; -/* * Timer 1 (16-bit) * * Set prescaler to 1024 * * Enable overflow interrupt * * Set timer to 0 */ #define TIMER1_INIT() TCCR1B = (1 << CS12) | (1 << CS10); \ - TIMSK |= (1<<TOIE1); \ - TCNT1 = 0; + TIMSK |= (1<<TOIE1); \ + TCNT1 = 0; + +#define TIMER1_DISABLE() TCCR1B = 0; \ + TIMSK = 0; \ + TCNT1 = 0; #define TIMER1_ONE_SECOND ((uint32_t)(12207)) @@ -94,12 +89,6 @@ * Bits_32(10000000,11111111,10101010,01010101) = 2164238933 */ -typedef enum { - Top, - Middle, - Bottom -} LEDs; - void setup_atmel_io_ports(void); #endif /* _OCTOCLOCK_H_ */ diff --git a/firmware/octoclock/include/state.h b/firmware/octoclock/include/state.h index 9734948cf..2170c2638 100644 --- a/firmware/octoclock/include/state.h +++ b/firmware/octoclock/include/state.h @@ -22,23 +22,24 @@ #include <octoclock.h> -// NOT PRESENT unless proven so... -static ref_t global_which_ref = NO_REF; -static bool global_gps_present = false; -static bool global_ext_ref_is_present = false; +// Global state variables +extern volatile bool g_ext_ref_present; +extern volatile bool g_gps_present; +extern volatile switch_pos_t g_switch_pos; +extern volatile ref_t g_ref; -void led(LEDs which, int turn_it_on); +typedef enum { + LED_TOP, // Internal + LED_MIDDLE, // External + LED_BOTTOM // Status +} led_t; -void LEDs_off(void); +void led(led_t which, bool on); -void force_internal(void); +void leds_off(void); void prefer_internal(void); void prefer_external(void); -ref_t which_ref(void); - -switch_pos_t get_switch_pos(void); - #endif /* _STATE_H_ */ diff --git a/firmware/octoclock/include/usart.h b/firmware/octoclock/include/usart.h index 35ee9eb95..203255988 100644 --- a/firmware/octoclock/include/usart.h +++ b/firmware/octoclock/include/usart.h @@ -25,10 +25,6 @@ void usart_init(void); char usart_getc(void); -char usart_getc_noblock(void); - void usart_putc(char ch); -void usart_putc_nowait(char ch); - #endif /* _USART_H_ */ diff --git a/firmware/octoclock/lib/clkdist.c b/firmware/octoclock/lib/clkdist.c index ed29510b6..0468ac38e 100644 --- a/firmware/octoclock/lib/clkdist.c +++ b/firmware/octoclock/lib/clkdist.c @@ -21,6 +21,8 @@ #include <clkdist.h> #include <state.h> +#include <util/delay.h> + #define wait() for(uint16_t u=14000; u; u--) asm("nop"); #define CLK (PA0) // Shift by 0 bits @@ -33,7 +35,7 @@ // Table of 32-bit constants to be written to the TI chip's registers. These are // from the "Special Settings" on Page 35 of the datasheet. // For the GPS's 10 MHz output -static uint32_t table_Pri_Ref[] = { +static const uint32_t table_Pri_Ref[] = { Bits_32(1,01010100,0,0), // Reg 0 Bits_32(1,01010100,0,0), // Outputs LVCMOS Positive&Negative Active - Non-inverted Bits_32(1,01010100,0,0), @@ -47,7 +49,7 @@ static uint32_t table_Pri_Ref[] = { // For the External 10 MHz input LVDS with external termination, // Effectively DC coupled -static uint32_t table_Sec_Ref[] = { +static const uint32_t table_Sec_Ref[] = { Bits_32(0001,01010100,0,100000), // Reg 0 -- use Secondary Reference for all channels Bits_32(0001,01010100,0,100000), // Outputs LVCMOS Positive&Negative Active - Non-inverted Bits_32(0001,01010100,0,100000), @@ -81,7 +83,6 @@ static bool get_bit(uint8_t bit_number) { // Send 32 bits to TI chip, LSB first. // Don't worry about reading any bits back at this time static void send_SPI(uint32_t bits) { - // Basically, when the clock is low, one can set MOSI to anything, as it's // ignored. set_bit(CE_, Lo); // Start SPI transaction with TI chip @@ -130,7 +131,8 @@ void setup_TI_CDCE18005(TI_Input_10_MHz which_input) { for(uint8_t i=0; i<table_size; i++){ temp = table_Pri_Ref[i]<<4; temp |= i; - send_SPI(temp); // Make sure the register's address is in the LSBs + // Make sure the register's address is in the LSBs + send_SPI(temp); } } else { // is Secondary_Ext -- External 10 MHz input from SMA connector @@ -169,6 +171,10 @@ uint32_t get_TI_CDCE18005(CDCE18005 which_register){ return receive_SPI(); } +void set_TI_CDCE18005(CDCE18005 which_register, uint32_t bits){ + send_SPI((bits << 4) | which_register); +} + bool check_TI_CDCE18005(TI_Input_10_MHz which_input, CDCE18005 which_register) { diff --git a/firmware/octoclock/lib/enc28j60.c b/firmware/octoclock/lib/enc28j60.c index f0bbee0e7..ead7e4ec8 100644 --- a/firmware/octoclock/lib/enc28j60.c +++ b/firmware/octoclock/lib/enc28j60.c @@ -1,337 +1,211 @@ -/*! \file enc28j60.c \brief Microchip ENC28J60 Ethernet Interface Driver. */ -//***************************************************************************** -// -// File Name : 'enc28j60.c' -// Title : Microchip ENC28J60 Ethernet Interface Driver -// Author : Pascal Stang (c)2005 -// Created : 9/22/2005 -// Revised : 5/19/2014 -// Version : 0.1 -// Target MCU : Atmel AVR series -// Editor Tabs : 4 -// -// Description : This driver provides initialization and transmit/receive -// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. -// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin -// chip, using an SPI interface to the host processor. -// -//***************************************************************************** +/* + * Copyright 2015 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #include <octoclock.h> #include <net/enc28j60.h> -#include <net/enc28j60conf.h> -#include <avr/io.h> #include <util/delay.h> -u08 Enc28j60Bank; -u16 NextPacketPtr; - -u08 enc28j60ReadOp(u08 op, u08 address) -{ - u08 data; - - // assert CS - ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); - - // issue read command - SPDR = op | (address & ADDR_MASK); - while(!(SPSR & (1<<SPIF))); - // read data - SPDR = 0x00; - while(!(SPSR & (1<<SPIF))); - // do dummy read if needed - if(address & 0x80) - { - SPDR = 0x00; - while(!(inb(SPSR) & (1<<SPIF))); - } - data = SPDR; - - // release CS - ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); - - return data; -} +static uint8_t current_bank; +static uint16_t next_pkt_ptr; -void enc28j60WriteOp(u08 op, u08 address, u08 data) -{ - // assert CS - ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); +#define SET_CS_ACTIVE() SPI_PORT &= ~(1<<SPI_CS); +#define SET_CS_PASSIVE() SPI_PORT |= (1<<SPI_CS); +#define SPI_WAIT() while(!(SPSR & (1<<SPIF))); - // issue write command - SPDR = op | (address & ADDR_MASK); - while(!(SPSR & (1<<SPIF))); - // write data - SPDR = data; - while(!(SPSR & (1<<SPIF))); +static uint8_t enc28j60_read_op(uint8_t op, uint8_t addr){ + SET_CS_ACTIVE(); + SPDR = (op | (addr & ADDR_MASK)); + SPI_WAIT(); + SPDR = 0x00; + SPI_WAIT(); - // release CS - ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); -} + if(addr & 0x80){ + SPDR = 0x00; + SPI_WAIT(); + } -void enc28j60ReadBuffer(u16 len, u08* data) -{ - // assert CS - ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); - - // issue read command - SPDR = ENC28J60_READ_BUF_MEM; - while(!(SPSR & (1<<SPIF))); - while(len--) - { - // read data - SPDR = 0x00; - while(!(SPSR & (1<<SPIF))); - *data++ = SPDR; - } - // release CS - ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); + SET_CS_PASSIVE(); + return SPDR; } -void enc28j60WriteBuffer(u16 len, u08* data) -{ - // assert CS - ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); - - // issue write command - SPDR = ENC28J60_WRITE_BUF_MEM; - while(!(SPSR & (1<<SPIF))); - while(len--) - { - // write data - SPDR = *data++; - while(!(SPSR & (1<<SPIF))); - } - // release CS - ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); +static void enc28j60_write_op(uint8_t op, uint8_t addr, uint8_t value){ + SET_CS_ACTIVE(); + + SPDR = (op | (addr & ADDR_MASK)); + SPI_WAIT(); + SPDR = value; + SPI_WAIT(); + + SET_CS_PASSIVE(); } -void enc28j60SetBank(u08 address) -{ - // set the bank (if needed) - if((address & BANK_MASK) != Enc28j60Bank) - { - // set the bank - enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0)); - enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5); - Enc28j60Bank = (address & BANK_MASK); - } +static void enc28j60_read_buffer(uint8_t* buf, uint16_t len){ + SET_CS_ACTIVE(); + + SPDR = RBM; + SPI_WAIT(); + while(len){ + len--; + SPDR = 0x00; + SPI_WAIT(); + *buf = SPDR; + buf++; + } + *buf = '\0'; + + SET_CS_PASSIVE(); } -u08 enc28j60Read(u08 address) -{ - // set the bank - enc28j60SetBank(address); - // do the read - return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address); +static void enc28j60_write_buffer(uint8_t* buf, uint16_t len){ + SET_CS_ACTIVE(); + + SPDR = WBM; + SPI_WAIT(); + while(len){ + len--; + SPDR = *buf; + buf++; + SPI_WAIT(); + } + + SET_CS_PASSIVE(); } -void enc28j60Write(u08 address, u08 data) -{ - // set the bank - enc28j60SetBank(address); - // do the write - enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data); +static void enc28j60_set_bank(uint8_t addr){ + if((addr & BANK_MASK) != current_bank){ + enc28j60_write_op(BFC, ECON1, (BSEL1|BSEL0)); + enc28j60_write_op(BFS, ECON1, ((addr & BANK_MASK) >> 5)); + current_bank = (addr & BANK_MASK); + } } -u16 enc28j60PhyRead(u08 address) -{ - u16 data; - - // Set the right address and start the register read operation - enc28j60Write(MIREGADR, address); - enc28j60Write(MICMD, MICMD_MIIRD); - - // wait until the PHY read completes - while(enc28j60Read(MISTAT) & MISTAT_BUSY); - - // quit reading - enc28j60Write(MICMD, 0x00); - - // get data value - data = enc28j60Read(MIRDL); - data |= enc28j60Read(MIRDH); - // return the data - return data; +static uint8_t enc28j60_read(uint8_t addr){ + enc28j60_set_bank(addr); + return enc28j60_read_op(RCR, addr); } -void enc28j60PhyWrite(u08 address, u16 data) -{ - // set the PHY register address - enc28j60Write(MIREGADR, address); - - // write the PHY data - enc28j60Write(MIWRL, data); - enc28j60Write(MIWRH, data>>8); - - // wait until the PHY write completes - while(enc28j60Read(MISTAT) & MISTAT_BUSY); +static void enc28j60_write(uint8_t addr, uint16_t value){ + enc28j60_set_bank(addr); + enc28j60_write_op(WCR, addr, value); } -void enc28j60Init(u08* macaddr) -{ - // initialize I/O - sbi(ENC28J60_CONTROL_DDR, ENC28J60_CONTROL_CS); - sbi(ENC28J60_CONTROL_PORT, ENC28J60_CONTROL_CS); - - // setup SPI I/O pins - sbi(ENC28J60_SPI_PORT, ENC28J60_SPI_SCK); // set SCK hi - sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SCK); // set SCK as output - cbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MISO); // set MISO as input - sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MOSI); // set MOSI as output - sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SS); // SS must be output for Master mode to work - // initialize SPI interface - // master mode - sbi(SPCR, MSTR); - // select clock phase positive-going in middle of data - cbi(SPCR, CPOL); - // Data order MSB first - cbi(SPCR,DORD); - // switch to f/4 2X = f/2 bitrate - cbi(SPCR, SPR0); - cbi(SPCR, SPR1); - sbi(SPSR, SPI2X); - // enable SPI - sbi(SPCR, SPE); - - // perform system reset - enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); - - /* - * "After sending an SPI Reset command, the PHY - * clock is stopped but the ESTAT.CLKRDY bit is not - * cleared. Therefore, polling the CLKRDY bit will not - * work to detect if the PHY is ready. - * - * Additionally, the hardware start-up time of 300 us - * may expire before the device is ready to operate. - * - * Work around - * After issuing the Reset command, wait at least - * 1 ms in firmware for the device to be ready." - * - * Source: http://ww1.microchip.com/downloads/en/DeviceDoc/80349c.pdf - */ - _delay_ms(1); - - // do bank 0 stuff - // initialize receive buffer - // 16-bit transfers, must write low byte first - // set receive buffer start address - NextPacketPtr = RXSTART_INIT; - enc28j60Write(ERXSTL, RXSTART_INIT&0xFF); - enc28j60Write(ERXSTH, RXSTART_INIT>>8); - // set receive pointer address - enc28j60Write(ERXRDPTL, RXSTART_INIT&0xFF); - enc28j60Write(ERXRDPTH, RXSTART_INIT>>8); - // set receive buffer end - // ERXND defaults to 0x1FFF (end of ram) - enc28j60Write(ERXNDL, RXSTOP_INIT&0xFF); - enc28j60Write(ERXNDH, RXSTOP_INIT>>8); - // set transmit buffer start - // ETXST defaults to 0x0000 (beginnging of ram) - enc28j60Write(ETXSTL, TXSTART_INIT&0xFF); - enc28j60Write(ETXSTH, TXSTART_INIT>>8); - - // do bank 2 stuff - // enable MAC receive - enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS); - // bring MAC out of reset - enc28j60Write(MACON2, 0x00); - // enable automatic padding and CRC operations - enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN); - // set inter-frame gap (non-back-to-back) - enc28j60Write(MAIPGL, 0x12); - enc28j60Write(MAIPGH, 0x0C); - // set inter-frame gap (back-to-back) - enc28j60Write(MABBIPG, 0x12); - // Set the maximum packet size which the controller will accept - enc28j60Write(MAMXFLL, MAX_FRAMELEN&0xFF); - enc28j60Write(MAMXFLH, MAX_FRAMELEN>>8); - - // do bank 3 stuff - // write MAC address - // NOTE: MAC address in ENC28J60 is byte-backward - enc28j60Write(MAADR5, macaddr[0]); - enc28j60Write(MAADR4, macaddr[1]); - enc28j60Write(MAADR3, macaddr[2]); - enc28j60Write(MAADR2, macaddr[3]); - enc28j60Write(MAADR1, macaddr[4]); - enc28j60Write(MAADR0, macaddr[5]); - - // no loopback of transmitted frames - enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS); - - // switch to bank 0 - enc28j60SetBank(ECON1); - // enable interrutps - enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE); - // enable packet reception - enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN); +void enc28j60_init(uint8_t* mac_addr){ + SPI_DDR |= (1 << SPI_CS); + SET_CS_PASSIVE(); + + SPI_DDR |= ((1 << SPI_MOSI) | (1 << SPI_SCK)); + SPI_DDR &= ~(1 << SPI_MISO); + SPI_PORT &= ~(1 << SPI_MOSI); + SPI_PORT &= ~(1 << SPI_SCK); + SPCR = ((1 << SPE) | (1 << MSTR)); + SPSR |= (1 << SPI2X); + enc28j60_write_op(SC, 0, SC); + next_pkt_ptr = RXSTART_INIT; + + // Designate RX addresses + enc28j60_write(ERXSTL, (RXSTART_INIT & 0xFF)); + enc28j60_write(ERXSTH, (RXSTART_INIT >> 8)); + enc28j60_write(ERXNDL, (RXSTOP_INIT & 0xFF)); + enc28j60_write(ERXNDH, (RXSTOP_INIT >> 8)); + + // Designate TX addresses + enc28j60_write(ETXSTL, (TXSTART_INIT & 0xFF)); + enc28j60_write(ETXSTH, (TXSTART_INIT >> 8)); + enc28j60_write(ETXNDL, (TXSTOP_INIT & 0xFF)); + enc28j60_write(ETXNDH, (TXSTOP_INIT >> 8)); + + // Configure filters + enc28j60_write(ERXFCON, (UCEN|CRCEN|PMEN|BCEN)); + enc28j60_write(EPMM0, 0x3F); + enc28j60_write(EPMM1, 0x30); + enc28j60_write(EPMCSL, 0xF9); + enc28j60_write(EPMCSH, 0xF7); + + // MAC initialization + enc28j60_write(MACON1, (MARXEN|TXPAUS|RXPAUS)); + enc28j60_write(MACON2, 0x00); + enc28j60_write_op(BFS, MACON3, (PADCFG0|TXCRCEN|FRMLNEN)); + enc28j60_write(MAIPGL, 0x12); + enc28j60_write(MAIPGH, 0x0C); + enc28j60_write(MABBIPG, 0x12); + enc28j60_write(MAMXFLL, (MAX_FRAMELEN & 0xFF)); + enc28j60_write(MAMXFLH, (MAX_FRAMELEN >> 8)); + enc28j60_write(MAADR5, mac_addr[0]); + enc28j60_write(MAADR4, mac_addr[1]); + enc28j60_write(MAADR3, mac_addr[2]); + enc28j60_write(MAADR2, mac_addr[3]); + enc28j60_write(MAADR1, mac_addr[4]); + enc28j60_write(MAADR0, mac_addr[5]); + + enc28j60_set_bank(ECON1); + enc28j60_write_op(BFS, ECON1, ENCRXEN); } -void enc28j60PacketSend(unsigned int len1, unsigned char* packet1, unsigned int len2, unsigned char* packet2) -{ - //Errata: Transmit Logic reset - enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST); - enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST); - - // Set the write pointer to start of transmit buffer area - enc28j60Write(EWRPTL, TXSTART_INIT&0xff); - enc28j60Write(EWRPTH, TXSTART_INIT>>8); - // Set the TXND pointer to correspond to the packet size given - enc28j60Write(ETXNDL, (TXSTART_INIT+len1+len2)); - enc28j60Write(ETXNDH, (TXSTART_INIT+len1+len2)>>8); - - // write per-packet control byte - enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00); - - // copy the packet into the transmit buffer - enc28j60WriteBuffer(len1, packet1); - if(len2>0) enc28j60WriteBuffer(len2, packet2); - - // send the contents of the transmit buffer onto the network - enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS); +uint16_t enc28j60_recv(uint8_t* buf, uint16_t max_len){ + uint16_t rxstat, len; + + // Return if no data is available + if(enc28j60_read(EPKTCNT) == 0) return 0; + + enc28j60_write(ERDPTL, (next_pkt_ptr & 0xFF)); + enc28j60_write(ERDPTH, (next_pkt_ptr >> 8)); + next_pkt_ptr = enc28j60_read_op(RBM, 0) | ((uint16_t)enc28j60_read_op(RBM, 0) << 8); + len = enc28j60_read_op(RBM, 0) | ((uint16_t)enc28j60_read_op(RBM, 0) << 8); + len -= 4; + rxstat = enc28j60_read_op(RBM, 0) | ((uint16_t)enc28j60_read_op(RBM, 0) << 8); + + // Length sanity check and actual enc28j60_read call + if(len > (max_len - 1)) len = max_len - 1; + if((rxstat & 0x80) == 0) len = 0; + else enc28j60_read_buffer(buf, len); + + // Update next packet pointer + enc28j60_write(ERXRDPTL, (next_pkt_ptr & 0xFF)); + enc28j60_write(ERXRDPTH, (next_pkt_ptr >> 8)); + if(((next_pkt_ptr - 1) < RXSTART_INIT) || ((next_pkt_ptr - 1) > RXSTOP_INIT)){ + enc28j60_write(ERXRDPTL, (RXSTOP_INIT & 0xFF)); + enc28j60_write(ERXRDPTH, (RXSTOP_INIT >> 8)); + } + else{ + enc28j60_write(ERXRDPTL, ((next_pkt_ptr - 1) & 0xFF)); + enc28j60_write(ERXRDPTH, ((next_pkt_ptr - 1) >> 8)); + } + enc28j60_write_op(BFS, ECON2, PKTDEC); + + return len; } -unsigned int enc28j60PacketReceive(unsigned int maxlen, u08* buf) -{ - u16 rxstat; - u16 len; - - // check if a packet has been received and buffered - if( !enc28j60Read(EPKTCNT) ) - return 0; - - // Set the read pointer to the start of the received packet - enc28j60Write(ERDPTL, (NextPacketPtr)); - enc28j60Write(ERDPTH, (NextPacketPtr)>>8); - // read the next packet pointer - NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0); - NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8; - // read the packet length - len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0); - len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8; - // read the receive status - rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0); - rxstat |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8; - - // limit retrieve length - // (we reduce the MAC-reported length by 4 to remove the CRC) - len = MIN(len, maxlen); - - // copy the packet from the receive buffer - enc28j60ReadBuffer(len, buf); - - // Move the RX read pointer to the start of the next received packet - // This frees the memory we just read out - enc28j60Write(ERXRDPTL, (NextPacketPtr)); - enc28j60Write(ERXRDPTH, (NextPacketPtr)>>8); - - // decrement the packet counter indicate we are done with this packet - enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC); - - return len; +void enc28j60_send(uint8_t* buf, uint16_t len){ + + // Wait for any current transmission to finish + while(enc28j60_read_op(RCR, ECON1) & TXRTS){ + if(enc28j60_read(EIR) & TXERIF){ + enc28j60_write_op(BFS, ECON1, TXRST); + enc28j60_write_op(BFC, ECON1, TXRST); + } + } + + enc28j60_write(EWRPTL, (TXSTART_INIT & 0xFF)); + enc28j60_write(EWRPTH, (TXSTART_INIT >> 8)); + enc28j60_write(ETXNDL, ((TXSTART_INIT + len) & 0xFF)); + enc28j60_write(ETXNDH, ((TXSTART_INIT + len) >> 8)); + enc28j60_write_op(WBM, 0, 0x00); + enc28j60_write_buffer(buf, len); + enc28j60_write_op(BFS, ECON1, TXRTS); } diff --git a/firmware/octoclock/lib/init.c b/firmware/octoclock/lib/init.c index 827ccb376..8592aa091 100644 --- a/firmware/octoclock/lib/init.c +++ b/firmware/octoclock/lib/init.c @@ -71,7 +71,7 @@ void setup_atmel_io_ports(){ // /pd_cdcd, /sync_code, /ce need to be 1 (disabled) to start // all bits are outputs, except PA7 (gps_lock) and PA3 (MISO_CDCE) are inputs -PORTA = Bits_8(00110010); +PORTA = Bits_8(00100010); DDRA = 1<<DDA6 | 1<<DDA5 | 1<<DDA4 | 1<<DDA2 | 1<<DDA1 | 1<<DDA0; /* @@ -90,8 +90,8 @@ DDRA = 1<<DDA6 | 1<<DDA5 | 1<<DDA4 | 1<<DDA2 | 1<<DDA1 | 1<<DDA0; * */ -PORTB = Bits_8(01100001); // Initial Value is all zeros -DDRB = 1<<DDB2 | 1<<DDB4 | 1<<DDB7; // MOSI is an output; the Not Connected pins are also outputs +PORTB = Bits_8(01100001); // Initial Value is all zeros +DDRB = Bits_8(11110111); // MOSI is an output; the Not Connected pins are also outputs /* * Port C diff --git a/firmware/octoclock/lib/network.c b/firmware/octoclock/lib/network.c index bb49de4f6..22fc2b54b 100644 --- a/firmware/octoclock/lib/network.c +++ b/firmware/octoclock/lib/network.c @@ -27,6 +27,7 @@ #include <debug.h> #include <octoclock.h> +#include <state.h> #include <network.h> #include <net/enc28j60.h> @@ -34,12 +35,14 @@ #include <net/if_arp.h> #include <net/ethertype.h> +#include <util/delay.h> + #include "arp_cache.h" /*********************************************************************** * Constants + Globals **********************************************************************/ -static const size_t out_buff_size = 512; +static const size_t out_buff_size = ETH_BUF_SIZE; static const eth_mac_addr_t BCAST_MAC_ADDR = {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; #define MAX_UDP_LISTENERS 10 @@ -139,7 +142,7 @@ send_pkt( //grab an out buffer and pointer //select the output buffer based on type of packet uint8_t *p; - p = buf_out; + p = eth_buf; size_t total_len = 0; //create a list of all buffers to copy @@ -149,7 +152,7 @@ send_pkt( //copy each buffer into the out buffer for (size_t i = 0; i < sizeof(buffs)/sizeof(buffs[0]); i++){ total_len += lens[i]; //use full length (not clipped) - size_t bytes_remaining = out_buff_size - (size_t)(p - (uint8_t*)buf_out); + size_t bytes_remaining = out_buff_size - (size_t)(p - (uint8_t*)eth_buf); if (lens[i] > bytes_remaining) lens[i] = bytes_remaining; memcpy(p, buffs[i], lens[i]); p += lens[i]; @@ -161,7 +164,7 @@ send_pkt( //For some reason, the ENC28J60 won't send the CRC //if you don't tell it to send another byte after //the given packet - enc28j60PacketSend(total_len+1, buf_out, 0, 0); + enc28j60_send(eth_buf, total_len); } static void @@ -333,15 +336,15 @@ handle_arp_packet(struct arp_eth_ipv4 *p, size_t size) void handle_eth_packet(size_t recv_len) { - eth_hdr_t *eth_hdr = (eth_hdr_t *)buf_in; + eth_hdr_t *eth_hdr = (eth_hdr_t *)eth_buf; uint16_t ethertype = htons(eth_hdr->ethertype); if (ethertype == ETHERTYPE_ARP){ - struct arp_eth_ipv4 *arp = (struct arp_eth_ipv4 *)(buf_in + sizeof(eth_hdr_t)); + struct arp_eth_ipv4 *arp = (struct arp_eth_ipv4 *)(eth_buf + sizeof(eth_hdr_t)); handle_arp_packet(arp, recv_len-ETH_HLEN); } else if (ethertype == ETHERTYPE_IPV4){ - struct ip_hdr *ip = (struct ip_hdr *)(buf_in + sizeof(eth_hdr_t)); + struct ip_hdr *ip = (struct ip_hdr *)(eth_buf + sizeof(eth_hdr_t)); if (_IPH_V(ip) != 4 || _IPH_HL(ip) != 5) // ignore pkts w/ bad version or options return; @@ -357,7 +360,7 @@ handle_eth_packet(size_t recv_len) bool is_my_ip = memcmp(&ip->dest, &htonl_local_ip_addr, sizeof(_local_ip_addr)) == 0; if (!is_bcast && !is_my_ip) return; - arp_cache_update(&ip->src, (eth_mac_addr_t *)(((char *)buf_in)+6)); + arp_cache_update(&ip->src, (eth_mac_addr_t *)(((char *)eth_buf)+6)); switch (_IPH_PROTO(ip)){ case IP_PROTO_UDP: @@ -381,7 +384,6 @@ handle_eth_packet(size_t recv_len) **********************************************************************/ static bool send_garp = false; -static bool sent_initial_garp = false; static uint32_t num_overflows = 0; // Six overflows is the closest overflow count to one minute. @@ -390,6 +392,7 @@ ISR(TIMER1_OVF_vect){ if(!(num_overflows % 6)) send_garp = true; } +// Send a GARP packet once per minute. static void send_gratuitous_arp(){ send_garp = false; @@ -415,18 +418,9 @@ send_gratuitous_arp(){ // Executed every loop void network_check(void){ - size_t recv_len = enc28j60PacketReceive(512, buf_in); + size_t recv_len = enc28j60_recv(eth_buf, ETH_BUF_SIZE); if(recv_len > 0) handle_eth_packet(recv_len); - /* - * Send a gratuitous ARP packet two seconds after Ethernet - * initialization. - */ - if(!sent_initial_garp && (num_overflows == 0 && TCNT1 > (TIMER1_ONE_SECOND*2))){ - sent_initial_garp = true; - send_garp = true; - } - if(send_garp) send_gratuitous_arp(); } @@ -435,9 +429,10 @@ void network_init(void){ * Read MAC address from EEPROM and initialize Ethernet driver. If EEPROM is blank, * use default MAC address instead. */ + eeprom_busy_wait(); if(eeprom_read_byte(0) == 0xFF){ _MAC_ADDR(_local_mac_addr.addr, 0x00,0x80,0x2F,0x11,0x22,0x33); - _local_ip_addr.addr = default_ip; + _local_ip_addr.addr = _IP(192,168,10,3); using_network_defaults = true; } else{ @@ -446,5 +441,8 @@ void network_init(void){ using_network_defaults = false; } - enc28j60Init((uint8_t*)&_local_mac_addr); + enc28j60_init((uint8_t*)&_local_mac_addr); + init_udp_listeners(); + + send_garp = true; } diff --git a/firmware/octoclock/lib/state.c b/firmware/octoclock/lib/state.c index 0dbcc6ece..26e1b783c 100644 --- a/firmware/octoclock/lib/state.c +++ b/firmware/octoclock/lib/state.c @@ -15,110 +15,80 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <avr/interrupt.h> #include <avr/io.h> +#include <avrlibdefs.h> #include <debug.h> #include <octoclock.h> #include <clkdist.h> #include <state.h> -void led(LEDs which, int turn_it_on) { +// Global state variables +volatile bool g_ext_ref_present = false; +volatile bool g_gps_present = false; +volatile switch_pos_t g_switch_pos = PREFER_INTERNAL; +volatile ref_t g_ref = NO_REF; +void led(led_t which, bool on){ // selects the proper bit uint8_t LED = 0x20 << which; - if(turn_it_on) + if(on) PORTC |= LED; else PORTC &= ~LED; } -void LEDs_Off(void){ - led(Top,false); - led(Middle,false); - led(Bottom,false); +void leds_off(void){ + led(LED_TOP, false); + led(LED_MIDDLE, false); + led(LED_BOTTOM, false); } -void force_internal(void){ - led(Top,true); - led(Middle,false); - led(Bottom,true); +static void force_internal(void){ + led(LED_TOP, true); + led(LED_MIDDLE, false); + led(LED_BOTTOM, true); + // Tell ClkDist chip to use internal signals + cli(); setup_TI_CDCE18005(Primary_GPS); + sei(); - // Set PPS to Primary (1) n.b.: "1" in general means "Internal" for all - // such signals + // Set PPS to internal PORTA |= (1<<PA6); } -void force_external(void){ - led(Top, false); - led(Middle, true); - led(Bottom, true); +static void force_external(void){ + led(LED_TOP, false); + led(LED_MIDDLE, true); + led(LED_BOTTOM, true); + // Tell Clkdist chip to use external signals + cli(); setup_TI_CDCE18005(Secondary_Ext); + sei(); - // Set PPS to External + // Set PPS to external PORTA &= ~(1<<PA6); } void prefer_internal(void){ - // if internal is NOT OK, then force external - if(global_gps_present) + // If internal is NOT OK, then force external + if(g_gps_present) force_internal(); - else if(global_ext_ref_is_present) + else if(g_ext_ref_present) force_external(); else - LEDs_Off(); + leds_off(); } void prefer_external(void){ - // if external is NOT OK, then force internal - if(global_ext_ref_is_present) + // If external is NOT OK, then force internal + if(g_ext_ref_present) force_external(); - else if(global_gps_present) + else if(g_gps_present) force_internal(); else - LEDs_Off(); -} - -static uint8_t prev_PE7 = 0; -static uint32_t timer0_num_overflows = 0; - -ISR(TIMER0_OVF_vect){ - global_gps_present = (PIND & (1<<DDD4)); - - // Every ~1/10 second - if(!(timer0_num_overflows % 610)){ - prev_PE7 = (PINE & (1<<DDE7)); - - if(get_switch_pos() == UP) prefer_internal(); - else prefer_external(); - - global_ext_ref_is_present = false; - } - - if(!global_ext_ref_is_present){ - global_ext_ref_is_present = (prev_PE7 != (PINE & (1<<DDE7))); - } - - timer0_num_overflows++; -} - -ref_t which_ref(void){ - if(!global_gps_present && !global_ext_ref_is_present) global_which_ref = NO_REF; - else if(global_gps_present && !global_ext_ref_is_present) global_which_ref = INTERNAL; - else if(!global_gps_present && global_ext_ref_is_present) global_which_ref = EXTERNAL; - else global_which_ref = (get_switch_pos() == UP) ? INTERNAL : EXTERNAL; - - return global_which_ref; -} - -switch_pos_t get_switch_pos(void){ - uint8_t portC = PINC; - - // UP is prefer internal, - // DOWN is prefer external - return (portC & (1<<DDC1)) ? DOWN : UP; + leds_off(); } diff --git a/firmware/octoclock/lib/udp_handlers.c b/firmware/octoclock/lib/udp_handlers.c index 1f20112c9..49b9b8023 100644 --- a/firmware/octoclock/lib/udp_handlers.c +++ b/firmware/octoclock/lib/udp_handlers.c @@ -36,7 +36,7 @@ void handle_udp_ctrl_packet( pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM; pkt_out.sequence = pkt_in->sequence; - //If the firmware is incompatible, only respond to queries + // If the firmware is incompatible, only respond to queries if(pkt_in->code == OCTOCLOCK_QUERY_CMD){ pkt_out.code = OCTOCLOCK_QUERY_ACK; pkt_out.len = 0; @@ -50,44 +50,43 @@ void handle_udp_ctrl_packet( octoclock_fw_eeprom_t *eeprom_info = (octoclock_fw_eeprom_t*)pkt_out.data; - //Read values from EEPROM into packet + // Read values from EEPROM into packet + eeprom_busy_wait(); eeprom_read_block(eeprom_info, 0, sizeof(octoclock_fw_eeprom_t)); - //If EEPROM network fields are not fully populated, copy defaults + // If EEPROM network fields are not fully populated, copy defaults if(using_network_defaults){ _MAC_ADDR(eeprom_info->mac_addr, 0x00,0x80,0x2F,0x11,0x22,0x33); - eeprom_info->ip_addr = default_ip; - eeprom_info->dr_addr = default_dr; - eeprom_info->netmask = default_netmask; + eeprom_info->ip_addr = _IP(192,168,10,3); + eeprom_info->dr_addr = _IP(192,168,10,1); + eeprom_info->netmask = _IP(255,255,255,0); } - //Check if strings or revision is empty - if(eeprom_info->serial[0] == 0xFF) memset(eeprom_info->serial, 0, 10); - if(eeprom_info->name[0] == 0xFF) memset(eeprom_info->name, 0, 10); + // Check if strings or revision is empty if(eeprom_info->revision == 0xFF) eeprom_info->revision = 0; break; case BURN_EEPROM_CMD:{ - //Confirm length of data + // Confirm length of data if(pkt_in->len != sizeof(octoclock_fw_eeprom_t)){ pkt_out.code = BURN_EEPROM_FAILURE_ACK; break; } /* - * In all cases, a full octoclock_fw_eeprom_t is written to lower the overall - * number of writes due to this EEPROM's smaller amount of safe writes. * It is up to the host to make sure that the values that should be * preserved are present in the octoclock_fw_eeprom_t struct. */ const octoclock_fw_eeprom_t *eeprom_pkt = (octoclock_fw_eeprom_t*)pkt_in->data; pkt_out.len = 0; - //Write EEPROM data from packet + // Write EEPROM data from packet + eeprom_busy_wait(); eeprom_write_block(eeprom_pkt, 0, sizeof(octoclock_fw_eeprom_t)); - //Read back and compare to packet to confirm successful write + // Read back and compare to packet to confirm successful write uint8_t eeprom_contents[sizeof(octoclock_fw_eeprom_t)]; + eeprom_busy_wait(); eeprom_read_block(eeprom_contents, 0, sizeof(octoclock_fw_eeprom_t)); uint8_t n = memcmp(eeprom_contents, eeprom_pkt, sizeof(octoclock_fw_eeprom_t)); pkt_out.code = n ? BURN_EEPROM_FAILURE_ACK @@ -99,12 +98,12 @@ void handle_udp_ctrl_packet( pkt_out.code = SEND_STATE_ACK; pkt_out.len = sizeof(octoclock_state_t); - //Populate octoclock_state_t fields + // Populate octoclock_state_t fields octoclock_state_t *state = (octoclock_state_t*)pkt_out.data; - state->external_detected = global_ext_ref_is_present ? 1 : 0; - state->gps_detected = (PIND & _BV(DDD4)) ? 1 : 0; - state->which_ref = (uint8_t)which_ref(); - state->switch_pos = (uint8_t)get_switch_pos(); + state->external_detected = g_ext_ref_present ? 1 : 0; + state->gps_detected = g_gps_present ? 1 : 0; + state->which_ref = (uint8_t)g_ref; + state->switch_pos = (uint8_t)g_switch_pos; break; case RESET_CMD: diff --git a/firmware/octoclock/lib/usart.c b/firmware/octoclock/lib/usart.c index 3620ac5e9..a267e43c6 100644 --- a/firmware/octoclock/lib/usart.c +++ b/firmware/octoclock/lib/usart.c @@ -34,16 +34,8 @@ char usart_getc(void){ return UDR1; } -char usart_getc_noblock(void){ - return ((UCSR1A & (1 << RXC))) ? UDR1 : -1; -} - void usart_putc(char ch){ while((UCSR1A & (1 << UDRE1)) == 0); UDR1 = ch; } - -void usart_putc_nowait(char ch){ - if((UCSR1A & (1 << UDRE1)) != 0) UDR1 = ch; -} diff --git a/firmware/octoclock/octoclock_r4/CMakeLists.txt b/firmware/octoclock/octoclock_r4/CMakeLists.txt index c3559d8d4..9223721c8 100644 --- a/firmware/octoclock/octoclock_r4/CMakeLists.txt +++ b/firmware/octoclock/octoclock_r4/CMakeLists.txt @@ -43,7 +43,7 @@ add_custom_target( ) add_custom_target( upload_r4 - ${AVRDUDE} -p atmega128 -c ${PROGRAMMER} -P usb -U efuse:w:0xFF:m -U hfuse:w:0x81:m -U lfuse:w:0xFF:m -U flash:w:octoclock_r4_fw.hex:i + ${AVRDUDE} -p atmega128 -c ${PROGRAMMER} -P usb -U efuse:w:0xFF:m -U hfuse:w:0x81:m -U lfuse:w:0xEF:m -U flash:w:octoclock_r4_fw.hex:i WORKING_DIRECTORY ${CMAKE_BINARY_DIR} DEPENDS octoclock_r4_fw_hex COMMENT "Uploading OctoClock firmware to device with ${PROGRAMMER}" diff --git a/firmware/octoclock/octoclock_r4/octoclock_r4_main.c b/firmware/octoclock/octoclock_r4/octoclock_r4_main.c index 5e8e6d09b..b1df34195 100644 --- a/firmware/octoclock/octoclock_r4/octoclock_r4_main.c +++ b/firmware/octoclock/octoclock_r4/octoclock_r4_main.c @@ -36,7 +36,7 @@ * JTAGEN = [X] * SPIEN = [X] * EESAVE = [X] - * BOOTSZ = 4096W_F000 + * BOOTSZ = 4095W_F000 * BOOTRST = [ ] * CKOPT = [X] * BODLEVEL = 2V7 @@ -49,57 +49,165 @@ * */ +#include <stdlib.h> #include <string.h> #include <stdint.h> #include <stdbool.h> #include <avr/eeprom.h> +#include <avr/interrupt.h> #include <avr/io.h> +#include <avrlibdefs.h> #include <octoclock.h> -#include <clkdist.h> #include <debug.h> +#include <clkdist.h> #include <state.h> #include <network.h> #include <usart.h> -#include <gpsdo.h> -#include <net/enc28j60.h> #include <net/udp_handlers.h> +/* + * Timer 3 (16-bit) + * * Set input capture trigger to rising edge + * * Set prescaler to 1 + * * Enable overflow interrupt + * * Set timer to 0 + */ +#define TIMER3_INIT() TCCR3B = (1 << ICES3) | (1 << CS30); \ + ETIMSK |= (1 << TOIE3); \ + TCNT3 = 0; \ + ICR3 = 0; + +/* + * We use TIMER3 as a watchdog timer for external reference + * detection. Once a signal is detected, we allow for five + * timer overflows (~26 ms) without another signal before + * deciding that there is no external reference connected. + */ +#define EXT_REF_TIMEOUT 5 + +static volatile uint16_t num_overflows = 0; +static uint16_t current_num_overflows = 0; +static uint16_t prev_num_overflows = 0; +static uint16_t current_ICR3 = 0; +static uint16_t prev_ICR3 = 0; +static ref_t prev_ref = NO_REF; +static switch_pos_t prev_switch_pos = PREFER_EXTERNAL; +bool top = false; + +ISR(TIMER3_OVF_vect){ + num_overflows++; +} + /******************************************************************************* * Main Routine *******************************************************************************/ int main(void){ - asm("cli"); + /* + * Initializations + */ + cli(); + // Make sure interrupts belong to us + MCUCR = (1<<IVCE); + MCUCR = 0; + + // Initialize global variables + g_ext_ref_present = false; + g_gps_present = false; + g_switch_pos = PREFER_INTERNAL; + g_ref = NO_REF; + + // Atmega128 setup_atmel_io_ports(); - network_init(); - #ifndef DEBUG - asm("sei"); - #endif + // Reset ClkDist chip + reset_TI_CDCE18005(); - init_udp_listeners(); - register_udp_listener(OCTOCLOCK_UDP_CTRL_PORT, handle_udp_ctrl_packet); + // GPSDO communication + usart_init(); + + // Ethernet stack + network_init(); + register_udp_listener(OCTOCLOCK_UDP_CTRL_PORT, handle_udp_ctrl_packet); register_udp_listener(OCTOCLOCK_UDP_GPSDO_PORT, handle_udp_gpsdo_packet); - DEBUG_INIT(); // Does nothing when not in debug mode - DEBUG_LOG(" "); //Force a newline between runs - usart_init(); + // Timers + TIMER1_INIT(); // Network + TIMER3_INIT(); // External reference check + + // Debug (does nothing when not in debug mode) + DEBUG_INIT(); + DEBUG_LOG(" "); // Force a newline between runs + + leds_off(); + + sei(); + + // Check if GPS present (should only need to happen once) + g_gps_present = (PIND & (1<<DDD4)); + + // State of previous iteration + prev_ref = NO_REF; + prev_switch_pos = PREFER_EXTERNAL; + cli(); + prev_ICR3 = ICR3; + sei(); + prev_num_overflows = 0; + + /* + * Main loop + */ + while(true){ + // Check switch position + g_switch_pos = (PINC & (1<<DDC1)) ? PREFER_EXTERNAL : PREFER_INTERNAL; + + /* + * Check input capture pin for external reference detection. + * + * 16-bit reads could be corrupted during an interrupt, so + * disable interrupts for safety. + */ + cli(); + current_ICR3 = ICR3; + current_num_overflows = num_overflows; + sei(); + + // Signal detected, reset timer + if(current_ICR3 != prev_ICR3){ + cli(); + TCNT3 = 0; + num_overflows = 0; + sei(); + g_ext_ref_present = true; + } + + // Timeout, no external reference detected + if(current_num_overflows >= EXT_REF_TIMEOUT){ + g_ext_ref_present = false; + } - //Set initial ClkDist and front panel settings - led(Middle,true); - setup_TI_CDCE18005(Primary_GPS); // 10 MHz from Internal Source + // Determine and set reference based on state + if(!g_gps_present && !g_ext_ref_present) g_ref = NO_REF; + else if(g_gps_present && !g_ext_ref_present) g_ref = INTERNAL; + else if(!g_gps_present && g_ext_ref_present) g_ref = EXTERNAL; + else g_ref = (g_switch_pos == PREFER_INTERNAL) ? INTERNAL : EXTERNAL; - led(Top,true); - PORTA |= (1<<PA6); // PPS from Internal source + if((g_ref != prev_ref) || (g_switch_pos != prev_switch_pos)){ + if(g_switch_pos == PREFER_INTERNAL) prefer_internal(); + else prefer_external(); + } - TIMER0_INIT(); - TIMER1_INIT(); + // Record this iteration's state + prev_ref = g_ref; + prev_switch_pos = g_switch_pos; + prev_ICR3 = current_ICR3; + prev_num_overflows = current_num_overflows; - while(true) { + // Handle incoming Ethernet packets network_check(); } } diff --git a/firmware/usrp3/CMakeLists.txt b/firmware/usrp3/CMakeLists.txt index c25adb68a..f71b79b0c 100644 --- a/firmware/usrp3/CMakeLists.txt +++ b/firmware/usrp3/CMakeLists.txt @@ -68,6 +68,20 @@ FIND_PROGRAM(OBJDUMP zpu-elf-objdump) FIND_PROGRAM(HEXDUMP hexdump) ######################################################################## +# Firmware tracing support +######################################################################## +# Look at include/trace.h to see what the different trace levels map to. +SET(TRACE_LEVEL "0" CACHE STRING "Firmware Trace Level") #0 by default +OPTION(TRACE_LEVEL "Firmware Trace Level" "") +IF(TRACE_LEVEL) + #If TRACE_LEVEL == 0, don't define UHD_FW_TRACE_LEVEL so that the C + #code can easily detect if tracing is requested + IF(${TRACE_LEVEL} GREATER 0) + ADD_DEFINITIONS(-DUHD_FW_TRACE_LEVEL=${TRACE_LEVEL}) + ENDIF(${TRACE_LEVEL} GREATER 0) +ENDIF(TRACE_LEVEL) + +######################################################################## # helper functions to build output formats ######################################################################## SET(GEN_OUTPUTS_BIN_SIZE "bin_size_not_set") #set before calling diff --git a/firmware/usrp3/include/ethernet.h b/firmware/usrp3/include/ethernet.h index 52f14d05b..a6bacfcd0 100644 --- a/firmware/usrp3/include/ethernet.h +++ b/firmware/usrp3/include/ethernet.h @@ -31,7 +31,7 @@ typedef void (*ethernet_link_changed_callback_t)(int ethnum, int speed); /*! * \brief one time call to initialize ethernet */ -void xge_ethernet_init(const uint32_t eth); +void ethernet_init(const uint32_t eth); /*! * \brief Return number of ethernet interfaces @@ -44,8 +44,7 @@ void dump_mdio_regs(const uint8_t eth, uint32_t mdio_port); /*! * \brief Test status of SFP+ modules */ -void -xge_poll_sfpp_status(const uint32_t eth); +void poll_sfpp_status(const uint32_t eth); //! get the link status of eth (true for link up) bool ethernet_get_link_up(const uint32_t eth); diff --git a/firmware/usrp3/include/trace.h b/firmware/usrp3/include/trace.h new file mode 100644 index 000000000..0daa231fe --- /dev/null +++ b/firmware/usrp3/include/trace.h @@ -0,0 +1,82 @@ +// +// Copyright 2015 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_TRACE_H +#define INCLUDED_TRACE_H + +#include <stdint.h> +#include <stdbool.h> +#include <printf.h> + +/* + * Enables basic conditional tracing support + * If UHD_FW_TRACE_LEVEL is defined, all messages + * with a verbosity >= UHD_FW_TRACE_LEVEL will be + * printed. + * + * An alternate way of defining the level is the "TRACE_LEVEL" + * variable in cmake. (eg. -DTRACE_LEVEL=13). + */ +//#define UHD_FW_TRACE_LEVEL 13 + +typedef enum +{ + /* 0-9: Use for performance/restricted debugging */ + ERROR = 10, + WARN = 11, + INFO = 12, + /* 13-19: Use for general debugging */ + DEBUG = 20, //Verbose! +} trace_level_t; + +static inline int _trace_typecheck_conv(trace_level_t lvl) { + return (int)lvl; +} + +#define UHD_FW_PRINTF(...) printf(__VA_ARGS__) +#define UHD_FW_BEAUTIFY_LVL(lvl) "[" #lvl "] " + +/* + * UHD_FW_TRACE(<log level>, <message>) + * - Simple trace. Print the messages with the log level as the prefix and \n at the end + * + * UHD_FW_TRACE_FSTR(<log level>, <format string>, <args>) + * - Trace format string with the log level as the prefix and \n at the end + * + * UHD_FW_TRACE_SHORT(<log level>, <message>) + * - Simple trace. Print the messages without the log level prefix or \n at the end + * + * UHD_FW_TRACE_FSTR_SHORT(<log level>, <format string>, <args>) + * - Trace format string without the log level prefix or \n at the end + */ +#ifdef UHD_FW_TRACE_LEVEL + #define UHD_FW_TRACE(lvl, fmt) \ + if (UHD_FW_TRACE_LEVEL >= _trace_typecheck_conv(lvl)) UHD_FW_PRINTF(UHD_FW_BEAUTIFY_LVL(lvl) fmt "\r\n"); + #define UHD_FW_TRACE_FSTR(lvl, fmt, ...) \ + if (UHD_FW_TRACE_LEVEL >= _trace_typecheck_conv(lvl)) UHD_FW_PRINTF(UHD_FW_BEAUTIFY_LVL(lvl) fmt "\r\n", __VA_ARGS__); + #define UHD_FW_TRACE_SHORT(lvl, fmt) \ + if (UHD_FW_TRACE_LEVEL >= _trace_typecheck_conv(lvl)) UHD_FW_PRINTF(fmt); + #define UHD_FW_TRACE_FSTR_SHORT(lvl, fmt, ...) \ + if (UHD_FW_TRACE_LEVEL >= _trace_typecheck_conv(lvl)) UHD_FW_PRINTF(fmt, __VA_ARGS__); +#else + #define UHD_FW_TRACE(lvl, fmt) ; + #define UHD_FW_TRACE_FSTR(lvl, fmt, ...) ; + #define UHD_FW_TRACE_SHORT(lvl, fmt) ; + #define UHD_FW_TRACE_FSTR_SHORT(lvl, fmt, ...) ; +#endif + +#endif /* INCLUDED_TRACE_H */ diff --git a/firmware/usrp3/lib/ethernet.c b/firmware/usrp3/lib/ethernet.c index 7a86980c7..91efbfe1d 100644 --- a/firmware/usrp3/lib/ethernet.c +++ b/firmware/usrp3/lib/ethernet.c @@ -22,7 +22,7 @@ #include "../x300/x300_defs.h" #include "ethernet.h" #include "mdelay.h" -#include "printf.h" +#include <trace.h> #include "wb_i2c.h" #include "wb_utils.h" //#include "memory_map.h" @@ -225,7 +225,7 @@ xge_read_sfpp_type(const uint32_t base, const uint32_t delay_ms) x = xge_i2c_rd(base, MODULE_DEV_ADDR, 3); // I2C Error? if (x < 0) { - printf("DEBUG: I2C error in SFPP_TYPE.\n"); + UHD_FW_TRACE(ERROR, "I2C error in SFPP_TYPE."); return x; } // Decode module type. These registers and values are defined in SFF-8472 @@ -235,55 +235,55 @@ xge_read_sfpp_type(const uint32_t base, const uint32_t delay_ms) } if (x & 0x10) { - printf("DEBUG: SFFP_TYPE_SR.\n"); + UHD_FW_TRACE(DEBUG, "SFFP_TYPE_SR."); return SFFP_TYPE_SR; } if (x & 0x20) { - printf("DEBUG: SFFP_TYPE_LR.\n"); + UHD_FW_TRACE(DEBUG, "SFFP_TYPE_LR."); return SFFP_TYPE_LR; } if (x & 0x40) { - printf("DEBUG: SFFP_TYPE_LRM.\n"); + UHD_FW_TRACE(DEBUG, "SFFP_TYPE_LRM."); return SFFP_TYPE_LRM; } // Search for legacy 1000-Base SFP types x = xge_i2c_rd(base, MODULE_DEV_ADDR, 0x6); if (x < 0) { - printf("DEBUG: I2C error in SFPP_TYPE.\n"); + UHD_FW_TRACE(ERROR, "I2C error in SFPP_TYPE."); return x; } if (x & 0x01) { - printf("DEBUG: SFFP_TYPE_1000BASE_SX.\n"); + UHD_FW_TRACE(DEBUG, "SFFP_TYPE_1000BASE_SX."); return SFFP_TYPE_1000BASE_SX; } if (x & 0x02) { - printf("DEBUG: SFFP_TYPE_1000BASE_LX.\n"); + UHD_FW_TRACE(DEBUG, "SFFP_TYPE_1000BASE_LX."); return SFFP_TYPE_1000BASE_LX; } if (x & 0x08) { - printf("DEBUG: SFFP_TYPE_1000BASE_T.\n"); + UHD_FW_TRACE(DEBUG, "SFFP_TYPE_1000BASE_T."); return SFFP_TYPE_1000BASE_T; } // Not one of the standard optical types..now try to deduce if it's twinax aka 10GSFP+CU // which is not covered explicitly in SFF-8472 x = xge_i2c_rd(base, MODULE_DEV_ADDR, 8); if (x < 0) { - printf("DEBUG: I2C error in SFPP_TYPE.\n"); + UHD_FW_TRACE(ERROR, "I2C error in SFPP_TYPE."); return x; } if ((x & 4) == 0) // Passive SFP+ cable type goto unknown; // x = xge_i2c_rd(MODULE_DEV_ADDR, 6); -// printf("SFP+ reg6 read as %x\n",x); +// UHD_FW_TRACE(DEBUG, "SFP+ reg6 read as %x",x); // if (x < 0) // return x; // if (x != 0x04) // Returns 1000Base-CX as Compliance code // goto unknown; x = xge_i2c_rd(base, MODULE_DEV_ADDR, 0xA); if (x < 0) { - printf("DEBUG: I2C error in SFPP_TYPE.\n"); + UHD_FW_TRACE(ERROR, "I2C error in SFPP_TYPE."); return x; } if (x & 0x80) { @@ -292,117 +292,124 @@ xge_read_sfpp_type(const uint32_t base, const uint32_t delay_ms) x = xge_i2c_rd(base, MODULE_DEV_ADDR, 0x12); if (x < 0) { - printf("DEBUG: I2C error in SFPP_TYPE.\n"); + UHD_FW_TRACE(ERROR, "I2C error in SFPP_TYPE."); return x; } - printf("DEBUG: TwinAx.\n"); + UHD_FW_TRACE(DEBUG, "TwinAx."); // If cable length support is greater than 10M then pick correct type return x > 10 ? SFFP_TYPE_TWINAX_LONG : SFFP_TYPE_TWINAX; } unknown: - printf("DEBUG: Unknown SFP+ type.\n"); + UHD_FW_TRACE(WARN, "Unknown SFP+ type."); // Not a supported Module type return SFFP_TYPE_UNKNOWN; } - -// Pull reset line low for 100ms then release and wait 100ms -static void -xge_hard_phy_reset(const uint32_t base) +static void xge_mac_init(const uint32_t base) { - wb_poke32(base, 1); - mdelay(100); - wb_poke32(base, 0); - mdelay(100); - + UHD_FW_TRACE(DEBUG, "Begining XGE MAC init sequence."); + xge_regs->config = XGE_TX_ENABLE; } -static void -xge_mac_init(const uint32_t base) +// base is pointer to XGE MAC on Wishbone. +static void xge_phy_init(const uint8_t eth, const uint32_t mdio_port_arg) { - printf("INFO: Begining XGE MAC init sequence.\n"); - xge_regs->config = XGE_TX_ENABLE; + int x; + uint32_t mdio_port = eth==0 ? 1 : mdio_port_arg; + // Read LASI Ctrl register to capture state. + //y = xge_read_mdio(0x9002,XGE_MDIO_DEVICE_PMA,XGE_MDIO_ADDR_PHY_A); + UHD_FW_TRACE(DEBUG, "Begining XGE PHY init sequence."); + // Software reset + x = read_mdio(eth, 0x0, XGE_MDIO_DEVICE_PMA,mdio_port); + x = x | (1 << 15); + write_mdio(eth, 0x0,XGE_MDIO_DEVICE_PMA,mdio_port,x); + while(x&(1<<15)) { + x = read_mdio(eth, 0x0,XGE_MDIO_DEVICE_PMA,mdio_port); + } } -// base is pointer to XGE MAC on Wishbone. -static void -xge_phy_init(const uint8_t eth, const uint32_t mdio_port) +void update_eth_state(const uint32_t eth) { - int x; - // Read LASI Ctrl register to capture state. - //y = xge_read_mdio(0x9002,XGE_MDIO_DEVICE_PMA,XGE_MDIO_ADDR_PHY_A); - printf("INFO: Begining XGE PHY init sequence.\n"); - // Software reset - x = read_mdio(eth, 0x0, XGE_MDIO_DEVICE_PMA,mdio_port); - x = x | (1 << 15); - write_mdio(eth, 0x0,XGE_MDIO_DEVICE_PMA,mdio_port,x); - while(x&(1<<15)) - x = read_mdio(eth, 0x0,XGE_MDIO_DEVICE_PMA,mdio_port); + const bool old_link_up = links_up[eth]; + const uint32_t status_reg_addr = (eth==0) ? RB_SFPP_STATUS0 : RB_SFPP_STATUS1; + const bool is_10g = (wb_peek32(SR_ADDR(RB0_BASE, eth == 0 ? RB_ETH_TYPE0 : RB_ETH_TYPE1)) == 1); + + uint32_t sfpp_status = wb_peek32(SR_ADDR(RB0_BASE, status_reg_addr)) & 0xFFFF; + if ((sfpp_status & (SFPP_STATUS_RXLOS|SFPP_STATUS_TXFAULT|SFPP_STATUS_MODABS)) == 0) { + //SFP+ pin state changed. Reinitialize PHY and MAC + if (is_10g) { + xge_mac_init((eth==0) ? XGE0_BASE : XGE1_BASE); + xge_phy_init(eth ,MDIO_PORT); + } else { + //No-op for 1G + } + + int8_t timeout = 100; + bool link_up = false; + do { + if (is_10g) { + link_up = ((read_mdio(eth, XGE_MDIO_STATUS1,XGE_MDIO_DEVICE_PMA,MDIO_PORT)) & (1 << 2)) != 0; + } else { + link_up = ((wb_peek32(SR_ADDR(RB0_BASE, status_reg_addr)) >> 16) & 0x1) != 0; + } + } while (!link_up && timeout-- > 0); + + links_up[eth] = link_up; + } + else + { + links_up[eth] = false; + } + + if (!old_link_up && links_up[eth]) u3_net_stack_send_arp_request(eth, u3_net_stack_get_ip_addr(eth)); + UHD_FW_TRACE_FSTR(INFO, "The link on eth port %u is %s", eth, links_up[eth]?"up":"down"); } -void -xge_poll_sfpp_status(const uint32_t eth) +void poll_sfpp_status(const uint32_t eth) { - uint32_t x; - // Has MODDET/MODAbS changed since we last looked? - x = wb_peek32(SR_ADDR(RB0_BASE, (eth==0) ? RB_SFPP_STATUS0 : RB_SFPP_STATUS1 )); - - if (x & SFPP_STATUS_RXLOS_CHG) - printf("DEBUG: eth%1d RXLOS changed state: %d\n", eth, x & SFPP_STATUS_RXLOS); - if (x & SFPP_STATUS_TXFAULT_CHG) - printf("DEBUG: eth%1d TXFAULT changed state: %d\n", eth,(x & SFPP_STATUS_TXFAULT) >> 1 ); - if (x & SFPP_STATUS_MODABS_CHG) - printf("DEBUG: eth%1d MODABS changed state: %d\n", eth, (x & SFPP_STATUS_MODABS) >> 2); - - if (x & (SFPP_STATUS_RXLOS_CHG|SFPP_STATUS_TXFAULT_CHG|SFPP_STATUS_MODABS_CHG)) - { - if (( x & (SFPP_STATUS_RXLOS|SFPP_STATUS_TXFAULT|SFPP_STATUS_MODABS)) == 0) + uint32_t x; + // Has MODDET/MODAbS changed since we last looked? + x = wb_peek32(SR_ADDR(RB0_BASE, (eth==0) ? RB_SFPP_STATUS0 : RB_SFPP_STATUS1 )); + + if (x & SFPP_STATUS_RXLOS_CHG) + UHD_FW_TRACE_FSTR(DEBUG, "eth%1d RXLOS changed state: %d", eth, (x & SFPP_STATUS_RXLOS)); + if (x & SFPP_STATUS_TXFAULT_CHG) + UHD_FW_TRACE_FSTR(DEBUG, "eth%1d TXFAULT changed state: %d", eth, ((x & SFPP_STATUS_TXFAULT) >> 1)); + if (x & SFPP_STATUS_MODABS_CHG) + UHD_FW_TRACE_FSTR(DEBUG, "eth%1d MODABS changed state: %d", eth, ((x & SFPP_STATUS_MODABS) >> 2)); + + //update the link up status + if ((x & SFPP_STATUS_RXLOS_CHG) || (x & SFPP_STATUS_TXFAULT_CHG) || (x & SFPP_STATUS_MODABS_CHG)) { - if (wb_peek32(SR_ADDR(RB0_BASE, eth == 0 ? RB_ETH_TYPE0 : RB_ETH_TYPE1)) == 1) - { - xge_ethernet_init(eth); - dump_mdio_regs((eth==0) ? XGE0_BASE : XGE1_BASE,MDIO_PORT); - mdelay(100); - dump_mdio_regs((eth==0) ? XGE0_BASE : XGE1_BASE,MDIO_PORT); - mdelay(100); - dump_mdio_regs((eth==0) ? XGE0_BASE : XGE1_BASE,MDIO_PORT); - } + update_eth_state(eth); } - } - if (x & SFPP_STATUS_MODABS_CHG) { - // MODDET has changed state since last checked - if (x & SFPP_STATUS_MODABS) { - // MODDET is high, module currently removed. - printf("INFO: An SFP+ module has been removed from eth port %d.\n", eth); - } else { - // MODDET is low, module currently inserted. - // Return status. - printf("INFO: A new SFP+ module has been inserted into eth port %d.\n", eth); - xge_read_sfpp_type((eth==0) ? I2C0_BASE : I2C2_BASE,1); + if (x & SFPP_STATUS_MODABS_CHG) { + // MODDET has changed state since last checked + if (x & SFPP_STATUS_MODABS) { + // MODDET is high, module currently removed. + UHD_FW_TRACE_FSTR(INFO, "An SFP+ module has been removed from eth port %d.", eth); + } else { + // MODDET is low, module currently inserted. + // Return status. + UHD_FW_TRACE_FSTR(INFO, "A new SFP+ module has been inserted into eth port %d.", eth); + xge_read_sfpp_type((eth==0) ? I2C0_BASE : I2C2_BASE,1); + } } - } - - //update the link up status - const bool old_link_up = links_up[eth]; - links_up[eth] = ((read_mdio(eth, XGE_MDIO_STATUS1,XGE_MDIO_DEVICE_PMA,MDIO_PORT)) & (1 << 2)) != 0; - //The link became up, send a GARP so everyone knows our mac/ip association - if (!old_link_up && links_up[eth]) u3_net_stack_send_arp_request(eth, u3_net_stack_get_ip_addr(eth)); } - -void -xge_ethernet_init(const uint32_t eth) +void ethernet_init(const uint32_t eth) { - xge_mac_init((eth==0) ? XGE0_BASE : XGE1_BASE); - //xge_hard_phy_reset(); - xge_phy_init(eth ,MDIO_PORT); - uint32_t x = wb_peek32(SR_ADDR(RB0_BASE, (eth==0) ? RB_SFPP_STATUS0 : RB_SFPP_STATUS1 )); - printf(" eth%1d SFP initial state: RXLOS: %d TXFAULT: %d MODABS: %d\n", - eth, - x & SFPP_STATUS_RXLOS, - (x & SFPP_STATUS_TXFAULT) >> 1, - (x & SFPP_STATUS_MODABS) >> 2); +#ifdef UHD_FW_TRACE_LEVEL + uint32_t x = wb_peek32(SR_ADDR(RB0_BASE, (eth==0) ? RB_SFPP_STATUS0 : RB_SFPP_STATUS1 )); + UHD_FW_TRACE_FSTR(DEBUG, "eth%1d SFP initial state: RXLOS: %d TXFAULT: %d MODABS: %d", + eth, + (x & SFPP_STATUS_RXLOS), + ((x & SFPP_STATUS_TXFAULT) >> 1), + ((x & SFPP_STATUS_MODABS) >> 2)); +#endif + links_up[eth] = false; + update_eth_state(eth); } // @@ -412,187 +419,179 @@ xge_ethernet_init(const uint32_t eth) void decode_reg(uint32_t address, uint32_t device, uint32_t data) { + UHD_FW_TRACE_FSTR(DEBUG, + "[MDIO Register Dump for Addr=%x, Device=%x]\n- Raw Value = %x", + address, device, data); int x; - printf("Device: "); - printf("%x",device); - printf(" "); switch(address) { case XGE_MDIO_CONTROL1: - printf("CONTROL1: "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "CONTROL1: %x = ", data); for (x=15; x >= 0 ; x--) if ((data & (1 << x)) != 0) // Bits set. switch(x) { - case 15: printf("Reset,"); break; - case 14: printf("Loopback,"); break; - case 11: printf("Low Power Mode,"); break; - case 5:case 4:case 3:case 2: printf("RESERVED speed value,"); break; - case 0: printf("PMA loopback,"); break; + case 15: UHD_FW_TRACE_SHORT(DEBUG, "Reset,"); break; + case 14: UHD_FW_TRACE_SHORT(DEBUG, "Loopback,"); break; + case 11: UHD_FW_TRACE_SHORT(DEBUG, "Low Power Mode,"); break; + case 5:case 4:case 3:case 2: UHD_FW_TRACE_SHORT(DEBUG, "RESERVED speed value,"); break; + case 0: UHD_FW_TRACE_SHORT(DEBUG, "PMA loopback,"); break; } //else // Bits clear. //switch (x) { - //case 13: case 6: printf(" None 10Gb/s speed set!"); break; + //case 13: case 6: UHD_FW_TRACE_SHORT(DEBUG, " None 10Gb/s speed set!"); break; //} - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XGE_MDIO_STATUS1: - printf("STATUS1: "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "STATUS1: %x = ", data); for (x=15; x >= 0 ; x--) if ((data & (1 << x)) != 0) // Bits set. switch(x) { - case 7: printf("Fault Detected,"); break; - case 2: printf("Link is Up,"); break; - case 1: printf("Supports Low Power,"); break; + case 7: UHD_FW_TRACE_SHORT(DEBUG, "Fault Detected,"); break; + case 2: UHD_FW_TRACE_SHORT(DEBUG, "Link is Up,"); break; + case 1: UHD_FW_TRACE_SHORT(DEBUG, "Supports Low Power,"); break; } else // Bits Clear switch(x) { - case 2: printf("Link is Down,"); break; + case 2: UHD_FW_TRACE_SHORT(DEBUG, "Link is Down,"); break; } - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XGE_MDIO_SPEED: - printf("SPEED ABILITY: "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "SPEED ABILITY: %x = ", data); for (x=15; x >= 0 ; x--) if ((data & (1 << x)) != 0) // Bits set. switch(x) { case 15:case 14:case 13:case 12:case 11:case 10:case 9: - case 8:case 7:case 6:case 5:case 4:case 3:case 2:case 1: printf("RESERVED bits set!,"); break; - case 0: printf("Capable of 10Gb/s,"); + case 8:case 7:case 6:case 5:case 4:case 3:case 2:case 1: UHD_FW_TRACE_SHORT(DEBUG, "RESERVED bits set!,"); break; + case 0: UHD_FW_TRACE_SHORT(DEBUG, "Capable of 10Gb/s,"); } else // Bits clear. switch(x) { - case 0: printf("Incapable of 10Gb/s,"); break; + case 0: UHD_FW_TRACE_SHORT(DEBUG, "Incapable of 10Gb/s,"); break; } - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XGE_MDIO_DEVICES1: - printf("DEVICES IN PACKAGE: "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "DEVICES IN PACKAGE: %x = ", data); for (x=15; x >= 0 ; x--) if ((data & (1 << x)) != 0) // Bits set. switch(x) { - case 7: printf("Auto-Negotiation,"); break; - case 6: printf("TC,"); break; - case 5: printf("DTE XS,"); break; - case 4: printf("PHY XS,"); break; - case 3: printf("PCS,"); break; - case 2: printf("WIS,"); break; - case 1: printf("PMD/PMA,"); break; - case 0: printf("Clause 22 registers,"); break; + case 7: UHD_FW_TRACE_SHORT(DEBUG, "Auto-Negotiation,"); break; + case 6: UHD_FW_TRACE_SHORT(DEBUG, "TC,"); break; + case 5: UHD_FW_TRACE_SHORT(DEBUG, "DTE XS,"); break; + case 4: UHD_FW_TRACE_SHORT(DEBUG, "PHY XS,"); break; + case 3: UHD_FW_TRACE_SHORT(DEBUG, "PCS,"); break; + case 2: UHD_FW_TRACE_SHORT(DEBUG, "WIS,"); break; + case 1: UHD_FW_TRACE_SHORT(DEBUG, "PMD/PMA,"); break; + case 0: UHD_FW_TRACE_SHORT(DEBUG, "Clause 22 registers,"); break; } - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XGE_MDIO_DEVICES2: - printf("DEVICES IN PACKAGE (cont): "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "DEVICES IN PACKAGE (cont): %x = ", data); for (x=15; x >= 0 ; x--) if ((data & (1 << x)) != 0) // Bits set. switch(x) { - case 15: printf("Vendor device 2,"); break; - case 14: printf("Vendor device 1,"); break; - case 13: printf("Clause 22 extension,"); break; + case 15: UHD_FW_TRACE_SHORT(DEBUG, "Vendor device 2,"); break; + case 14: UHD_FW_TRACE_SHORT(DEBUG, "Vendor device 1,"); break; + case 13: UHD_FW_TRACE_SHORT(DEBUG, "Clause 22 extension,"); break; } - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XGE_MDIO_CONTROL2: - printf("CONTROL2: "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "CONTROL2: %x = ", data); // PMA/PMD if (device == XGE_MDIO_DEVICE_PMA) switch((data & 0xf)) { - case 0xF: printf("10BASE-T,"); break; - case 0xE: printf("100BASE-TX,"); break; - case 0xD: printf("1000BASE-KX,"); break; - case 0xC: printf("1000BASE-T,"); break; - case 0xB: printf("10GBASE-KR,"); break; - case 0xA: printf("10GBASE-KX4,"); break; - case 0x9: printf("10GBASE-T,"); break; - case 0x8: printf("10GBASE-LRM,"); break; - case 0x7: printf("10GBASE-SR,"); break; - case 0x6: printf("10GBASE-LR,"); break; - case 0x5: printf("10GBASE-ER,"); break; - case 0x4: printf("10GBASE-LX4,"); break; - // case 0x3: printf("10GBASE-SW,"); break; - // case 0x2: printf("10GBASE-LW,"); break; - // case 0x1: printf("10GBASE-EW,"); break; - case 0x0: printf("10GBASE-CX4,"); break; + case 0xF: UHD_FW_TRACE_SHORT(DEBUG, "10BASE-T,"); break; + case 0xE: UHD_FW_TRACE_SHORT(DEBUG, "100BASE-TX,"); break; + case 0xD: UHD_FW_TRACE_SHORT(DEBUG, "1000BASE-KX,"); break; + case 0xC: UHD_FW_TRACE_SHORT(DEBUG, "1000BASE-T,"); break; + case 0xB: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-KR,"); break; + case 0xA: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-KX4,"); break; + case 0x9: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-T,"); break; + case 0x8: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-LRM,"); break; + case 0x7: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-SR,"); break; + case 0x6: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-LR,"); break; + case 0x5: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-ER,"); break; + case 0x4: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-LX4,"); break; + // case 0x3: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-SW,"); break; + // case 0x2: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-LW,"); break; + // case 0x1: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-EW,"); break; + case 0x0: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-CX4,"); break; } else if (device == XGE_MDIO_DEVICE_PCS) // PCS switch((data & 0x3)) { - case 0x3: printf("10GBASE-T PCS,"); break; - case 0x2: printf("10GBASE-W PCS,"); break; - case 0x1: printf("10GBASE-X PCS,"); break; - case 0x0: printf("10GBASE-R PCS,"); break; + case 0x3: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-T PCS,"); break; + case 0x2: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-W PCS,"); break; + case 0x1: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-X PCS,"); break; + case 0x0: UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-R PCS,"); break; } - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XGE_MDIO_STATUS2: - printf("STATUS2: "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "STATUS2: %x = ", data); for (x=15; x >= 0 ; x--) if ((data & (1 << x)) != 0) // Bits set. switch(x) { - case 15: if ((data & (1 << 14)) == 0) printf("Device responding,"); break; - case 13: if (device == XGE_MDIO_DEVICE_PMA) printf("Able detect a Tx fault,"); break; - case 12: if (device == XGE_MDIO_DEVICE_PMA) printf("Able detect an Rx fault,"); break; - case 11: printf("Fault on Tx path,"); break; - case 10: printf("Fault on Rx path,"); break; - case 9: if (device == XGE_MDIO_DEVICE_PMA) printf("Extended abilities in Reg1.11,"); break; - case 8: if (device == XGE_MDIO_DEVICE_PMA) printf("Able to disable TX,"); break; - case 7: if (device == XGE_MDIO_DEVICE_PMA) printf("10GBASE-SR,"); break; - case 6: if (device == XGE_MDIO_DEVICE_PMA) printf("10GBASE-LR,"); break; - case 5: if (device == XGE_MDIO_DEVICE_PMA) printf("10GBASE-ER,"); break; - case 4: if (device == XGE_MDIO_DEVICE_PMA) printf("10GBASE-LX4,"); break; - case 3: if (device == XGE_MDIO_DEVICE_PMA) printf("10GBASE-SW,"); break; - case 2: if (device == XGE_MDIO_DEVICE_PMA) printf("10GBASE-LW,"); break; - case 1: if (device == XGE_MDIO_DEVICE_PMA) printf("10GBASE-EW,"); break; - case 0: if (device == XGE_MDIO_DEVICE_PMA) printf("loopback,"); break; + case 15: if ((data & (1 << 14)) == 0) UHD_FW_TRACE_SHORT(DEBUG, "Device responding,"); break; + case 13: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "Able detect a Tx fault,"); break; + case 12: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "Able detect an Rx fault,"); break; + case 11: UHD_FW_TRACE_SHORT(DEBUG, "Fault on Tx path,"); break; + case 10: UHD_FW_TRACE_SHORT(DEBUG, "Fault on Rx path,"); break; + case 9: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "Extended abilities in Reg1.11,"); break; + case 8: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "Able to disable TX,"); break; + case 7: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-SR,"); break; + case 6: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-LR,"); break; + case 5: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-ER,"); break; + case 4: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-LX4,"); break; + case 3: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-SW,"); break; + case 2: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-LW,"); break; + case 1: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "10GBASE-EW,"); break; + case 0: if (device == XGE_MDIO_DEVICE_PMA) UHD_FW_TRACE_SHORT(DEBUG, "loopback,"); break; } - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XGE_MDIO_LANESTATUS: - printf("LANE STATUS: "); - printf("%x",data); printf(" "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "LANE STATUS: %x = ", data); for (x=15; x >= 0 ; x--) if ((data & (1 << x)) != 0) // Bits set. switch(x) { - case 12: printf("Lanes aligned,"); break; - case 11: printf("Able to generate test patterns,"); break; - case 3: printf("Lane 3 synced,"); break; - case 2: printf("Lane 2 synced,"); break; - case 1: printf("Lane 1 synced,"); break; - case 0: printf("Lane 0 synced,"); break; + case 12: UHD_FW_TRACE_SHORT(DEBUG, "Lanes aligned,"); break; + case 11: UHD_FW_TRACE_SHORT(DEBUG, "Able to generate test patterns,"); break; + case 3: UHD_FW_TRACE_SHORT(DEBUG, "Lane 3 synced,"); break; + case 2: UHD_FW_TRACE_SHORT(DEBUG, "Lane 2 synced,"); break; + case 1: UHD_FW_TRACE_SHORT(DEBUG, "Lane 1 synced,"); break; + case 0: UHD_FW_TRACE_SHORT(DEBUG, "Lane 0 synced,"); break; } else // Bits clear switch(x) { - case 3: printf("Lane 3 not synced,"); break; - case 2: printf("Lane 2 not synced,"); break; - case 1: printf("Lane 1 not synced,"); break; - case 0: printf("Lane 0 not synced,"); break; + case 3: UHD_FW_TRACE_SHORT(DEBUG, "Lane 3 not synced,"); break; + case 2: UHD_FW_TRACE_SHORT(DEBUG, "Lane 2 not synced,"); break; + case 1: UHD_FW_TRACE_SHORT(DEBUG, "Lane 1 not synced,"); break; + case 0: UHD_FW_TRACE_SHORT(DEBUG, "Lane 0 not synced,"); break; } - printf(" \n"); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); break; case XILINX_CORE_VERSION: - printf("XILINX CORE VERSION: %x ",data); - printf("Version: %d.%d ",(data&0xf000)>>12,(data&0xf00)>>8); - printf("Patch: %d ",(data&0xE)>>1); - if (data&0x1) printf("Evaluation Version of core"); - printf("\n"); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "XILINX CORE VERSION: %x ",data); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "Version: %d.%d ",((data&0xf000)>>12),((data&0xf00)>>8)); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "Patch: %d ",((data&0xE)>>1)); + UHD_FW_TRACE_SHORT(DEBUG, " \n"); + if (data&0x1) UHD_FW_TRACE(WARN, "Evaluation Version of core"); break; default: - printf("Register @ address: "); - printf("%x",address); - printf(" has value: "); - printf("%x\n",data); + UHD_FW_TRACE_SHORT(DEBUG, "Register @ address: "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "%x",address); + UHD_FW_TRACE_SHORT(DEBUG, " has value: "); + UHD_FW_TRACE_FSTR_SHORT(DEBUG, "%x\n",data); break; } } @@ -605,7 +604,6 @@ dump_mdio_regs(const uint8_t eth, uint32_t mdio_port) unsigned int regs_a[9] = {0,1,4,5,6,7,8,32,33}; unsigned int regs_b[10] = {0,1,4,5,6,7,8,10,11,65535}; - printf("\n"); for (y = 0; y < 10; y++) { @@ -621,7 +619,6 @@ dump_mdio_regs(const uint8_t eth, uint32_t mdio_port) decode_reg(regs_a[y],XGE_MDIO_DEVICE_PCS,x); } - printf("\n"); /* for (y = 0; y < 8; y++) */ /* { */ diff --git a/firmware/usrp3/lib/u3_net_stack.c b/firmware/usrp3/lib/u3_net_stack.c index 6b8ef096c..16eb0f9fe 100644 --- a/firmware/usrp3/lib/u3_net_stack.c +++ b/firmware/usrp3/lib/u3_net_stack.c @@ -3,7 +3,7 @@ #include <u3_net_stack.h> #include <string.h> //memcmp -#include <printf.h> +#include <trace.h> #define MAX_NETHS 4 @@ -281,7 +281,7 @@ void u3_net_stack_send_arp_request(const uint8_t ethno, const struct ip_addr *ad static void handle_arp_packet(const uint8_t ethno, const struct arp_eth_ipv4 *p) { - //printf("handle_arp_packet\n"); + UHD_FW_TRACE(DEBUG, "handle_arp_packet"); if (p->ar_hrd != ARPHRD_ETHER || p->ar_pro != ETHERTYPE_IPV4 || p->ar_hln != sizeof(eth_mac_addr_t) @@ -291,7 +291,7 @@ static void handle_arp_packet(const uint8_t ethno, const struct arp_eth_ipv4 *p) //got an arp reply -- injest it into the arp cache if (p->ar_op == ARPOP_REPLY) { - //printf("ARPOP_REPLY\n"); + UHD_FW_TRACE(DEBUG, "ARPOP_REPLY"); struct ip_addr ip_addr; memcpy(&ip_addr, p->ar_sip, sizeof(ip_addr)); eth_mac_addr_t mac_addr; @@ -302,7 +302,7 @@ static void handle_arp_packet(const uint8_t ethno, const struct arp_eth_ipv4 *p) //got an arp request -- reply if its for our address if (p->ar_op == ARPOP_REQUEST) { - //printf("ARPOP_REQUEST\n"); + UHD_FW_TRACE(DEBUG, "ARPOP_REQUEST"); if (memcmp(p->ar_tip, u3_net_stack_get_ip_addr(ethno), sizeof(struct ip_addr)) == 0) { send_arp_reply(ethno, p, u3_net_stack_get_mac_addr(ethno)); @@ -344,7 +344,7 @@ void u3_net_stack_send_udp_pkt( eth_mac_addr_t dst_mac_addr; if (!resolve_ip(dst, &dst_mac_addr)) { - printf("u3_net_stack_send_udp_pkt arp_cache_lookup fail\n"); + UHD_FW_TRACE(WARN, "u3_net_stack_send_udp_pkt arp_cache_lookup fail"); return; } @@ -396,7 +396,7 @@ static void handle_udp_packet( return; } } - printf("Unhandled UDP packet src=%u, dest=%u\n", udp->src, udp->dest); + UHD_FW_TRACE_FSTR(ERROR, "Unhandled UDP packet src=%u, dest=%u", udp->src, udp->dest); //TODO send destination unreachable } @@ -445,7 +445,7 @@ static void handle_icmp_packet( return; } } - printf("Unhandled ICMP packet type=%u\n", icmp->type); + UHD_FW_TRACE_FSTR(ERROR, "Unhandled ICMP packet type=%u", icmp->type); } static void handle_icmp_dur_packet( @@ -484,7 +484,7 @@ void u3_net_stack_send_icmp_pkt( eth_mac_addr_t dst_mac_addr; if (!resolve_ip(dst, &dst_mac_addr)) { - printf("u3_net_stack_send_echo_request arp_cache_lookup fail\n"); + UHD_FW_TRACE(WARN, "u3_net_stack_send_echo_request arp_cache_lookup fail"); return; } @@ -533,17 +533,17 @@ static void handle_eth_packet(const void *buff, const size_t num_bytes) { const padded_eth_hdr_t *eth_hdr = (padded_eth_hdr_t *)buff; const uint8_t *eth_body = ((const uint8_t *)buff) + sizeof(padded_eth_hdr_t); - //printf("handle_eth_packet got ethertype 0x%x\n", (unsigned)eth_hdr->ethertype); + UHD_FW_TRACE_FSTR(DEBUG, "handle_eth_packet got ethertype 0x%x", (unsigned)eth_hdr->ethertype); if (eth_hdr->ethertype == ETHERTYPE_ARP) { - //printf("eth_hdr->ethertype == ETHERTYPE_ARP\n"); + UHD_FW_TRACE(DEBUG, "eth_hdr->ethertype == ETHERTYPE_ARP"); const struct arp_eth_ipv4 *arp = (const struct arp_eth_ipv4 *)eth_body; handle_arp_packet(eth_hdr->ethno, arp); } else if (eth_hdr->ethertype == ETHERTYPE_IPV4) { - //printf("eth_hdr->ethertype == ETHERTYPE_IPV4\n"); + UHD_FW_TRACE(DEBUG, "eth_hdr->ethertype == ETHERTYPE_IPV4"); const struct ip_hdr *ip = (const struct ip_hdr *)eth_body; const uint8_t *ip_body = eth_body + IP_HLEN; @@ -572,7 +572,7 @@ static void handle_eth_packet(const void *buff, const size_t num_bytes) ); } } - else return; // Not ARP or IPV4, ignore + else return; // Not ARP or IPV4, ignore } void u3_net_stack_handle_one(void) @@ -581,7 +581,7 @@ void u3_net_stack_handle_one(void) const void *ptr = wb_pkt_iface64_rx_try_claim(pkt_iface_config, &num_bytes); if (ptr != NULL) { - //printf("u3_net_stack_handle_one got %u bytes\n", (unsigned)num_bytes); + UHD_FW_TRACE_FSTR(DEBUG, "u3_net_stack_handle_one got %u bytes", (unsigned)num_bytes); incr_stat_counts(ptr); handle_eth_packet(ptr, num_bytes); wb_pkt_iface64_rx_release(pkt_iface_config); diff --git a/firmware/usrp3/x300/x300_defs.h b/firmware/usrp3/x300/x300_defs.h index 65c5d5a23..c4011bd12 100644 --- a/firmware/usrp3/x300/x300_defs.h +++ b/firmware/usrp3/x300/x300_defs.h @@ -51,6 +51,7 @@ static const int RB_SPI_RDY = 1; static const int RB_SPI_DATA = 2; static const int RB_ETH_TYPE0 = 4; static const int RB_ETH_TYPE1 = 5; +static const int RB_FPGA_COMPAT = 6; static const int RB_SFPP_STATUS0 = 8; static const int RB_SFPP_STATUS1 = 9; diff --git a/firmware/usrp3/x300/x300_init.c b/firmware/usrp3/x300/x300_init.c index 66fb120f3..ef97412a2 100644 --- a/firmware/usrp3/x300/x300_init.c +++ b/firmware/usrp3/x300/x300_init.c @@ -7,7 +7,7 @@ #include <wb_i2c.h> #include <stdint.h> #include <stdbool.h> -#include <printf.h> +#include <trace.h> #include <wb_pkt_iface64.h> #include <u3_net_stack.h> #include <link_state_route_proto.h> @@ -73,7 +73,6 @@ const void *pick_inited_field(const void *eeprom, const void *def, const size_t static void init_network(void) { pkt_config = wb_pkt_iface64_init(PKT_RAM0_BASE, 0x1ffc); - printf("PKT RAM0 BASE 0x%x\n", (&pkt_config)->base); u3_net_stack_init(&pkt_config); link_state_route_proto_init(); @@ -115,7 +114,9 @@ static void init_network(void) static void putc(void *p, char c) { -#ifdef X300_DEBUG_UART +//If FW_TRACE_LEVEL is defined, then the trace level is set +//to a non-zero number. Turn on the debug UART to enable tracing +#ifdef UHD_FW_TRACE_LEVEL wb_uart_putc(UART1_BASE, c); #endif } @@ -129,7 +130,11 @@ void x300_init(void) //udp_uart_init(UART0_BASE, X300_GPSDO_UDP_PORT); //now we can init the rest with prints - printf("X300 ZPU Init Begin -- CPU CLOCK is %d MHz\n", CPU_CLOCK/1000000); + UHD_FW_TRACE(INFO, "[ZPU Initializing]"); + UHD_FW_TRACE_FSTR(INFO, "-- Firmware Compat Number: %u.%u", (int)X300_FW_COMPAT_MAJOR, (int)X300_FW_COMPAT_MINOR); + uint32_t fpga_compat = wb_peek32(SR_ADDR(SET0_BASE, RB_FPGA_COMPAT)); + UHD_FW_TRACE_FSTR(INFO, "-- FPGA Compat Number: %u.%u", (fpga_compat>>16), (fpga_compat&0xFFFF)); + UHD_FW_TRACE_FSTR(INFO, "-- Clock Frequency: %u MHz", (CPU_CLOCK/1000000)); //i2c rate init wb_i2c_init(I2C0_BASE, CPU_CLOCK); @@ -139,30 +144,26 @@ void x300_init(void) //hold phy in reset wb_poke32(SR_ADDR(SET0_BASE, SR_SW_RST), SW_RST_PHY); - printf("DEBUG: eth0 is %2dG\n",(wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE0))==1) ? 10 : 1); - printf("DEBUG: eth1 is %2dG\n",(wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE1))==1) ? 10 : 1); - //setup net stack and eth state machines init_network(); //phy reset release wb_poke32(SR_ADDR(SET0_BASE, SR_SW_RST), 0); - // For eth interfaces, initialize the PHY's - mdelay(100); - if (wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE0)) == 1) { - xge_ethernet_init(0); - } - if (wb_peek32(SR_ADDR(RB0_BASE, RB_ETH_TYPE1)) == 1) { - xge_ethernet_init(1); - } - //print network summary for (uint8_t e = 0; e < ethernet_ninterfaces(); e++) { - printf(" MAC%u: %s\n", (int)e, mac_addr_to_str(u3_net_stack_get_mac_addr(e))); - printf(" IP%u: %s\n", (int)e, ip_addr_to_str(u3_net_stack_get_ip_addr(e))); - printf(" SUBNET%u: %s\n", (int)e, ip_addr_to_str(u3_net_stack_get_subnet(e))); - printf(" BCAST%u: %s\n", (int)e, ip_addr_to_str(u3_net_stack_get_bcast(e))); + uint32_t offset = SR_ADDR(RB0_BASE, ((e==1)?RB_ETH_TYPE1:RB_ETH_TYPE0)); + UHD_FW_TRACE_FSTR(INFO, "Ethernet Port %u:", (int)e); + UHD_FW_TRACE_FSTR(INFO, "-- PHY: %s", ((wb_peek32(offset)==1) ? "10Gbps" : "1Gbps")); + UHD_FW_TRACE_FSTR(INFO, "-- MAC: %s", mac_addr_to_str(u3_net_stack_get_mac_addr(e))); + UHD_FW_TRACE_FSTR(INFO, "-- IP: %s", ip_addr_to_str(u3_net_stack_get_ip_addr(e))); + UHD_FW_TRACE_FSTR(INFO, "-- SUBNET: %s", ip_addr_to_str(u3_net_stack_get_subnet(e))); + UHD_FW_TRACE_FSTR(INFO, "-- BCAST: %s", ip_addr_to_str(u3_net_stack_get_bcast(e))); } + + // For eth interfaces, initialize the PHY's + mdelay(100); + ethernet_init(0); + ethernet_init(1); } diff --git a/firmware/usrp3/x300/x300_main.c b/firmware/usrp3/x300/x300_main.c index d865e1d09..3b812a2c4 100644 --- a/firmware/usrp3/x300/x300_main.c +++ b/firmware/usrp3/x300/x300_main.c @@ -13,7 +13,7 @@ #include <udp_uart.h> #include <u3_net_stack.h> #include <link_state_route_proto.h> -#include <printf.h> +#include <trace.h> #include <string.h> #include <print_addrs.h> @@ -33,7 +33,7 @@ void program_udp_framer( const eth_mac_addr_t *dst_mac = u3_net_stack_arp_cache_lookup(dst_ip); const size_t ethbase = (ethno == 0)? SR_ETHINT0 : SR_ETHINT1; const size_t vdest = (sid >> 16) & 0xff; - printf("handle_udp_prog_framer sid %u vdest %u\n", sid, vdest); + UHD_FW_TRACE_FSTR(INFO, "handle_udp_prog_framer sid %u vdest %u\n", sid, vdest); //setup source framer const eth_mac_addr_t *src_mac = u3_net_stack_get_mac_addr(ethno); @@ -204,7 +204,7 @@ void handle_udp_mtu_detect( if (buff == NULL) { return; } else if (!(request->flags & X300_MTU_DETECT_ECHO_REQUEST)) { - printf("DEBUG: MTU detect got unknown request\n"); + UHD_FW_TRACE(WARN, "MTU detect got unknown request"); reply.flags |= X300_MTU_DETECT_ERROR; } @@ -445,12 +445,12 @@ int main(void) static const uint32_t tick_delta = CPU_CLOCK/1000; if (ticks_passed > tick_delta) { + poll_sfpp_status(0); // Every so often poll XGE Phy to look for SFP+ hotplug events. + poll_sfpp_status(1); // Every so often poll XGE Phy to look for SFP+ hotplug events. handle_link_state(); //deal with router table update handle_claim(); //deal with the host claim register update_leds(); //run the link and activity leds garp(); //send periodic garps - xge_poll_sfpp_status(0); // Every so often poll XGE Phy to look for SFP+ hotplug events. - xge_poll_sfpp_status(1); // Every so often poll XGE Phy to look for SFP+ hotplug events. last_cronjob = wb_peek32(SR_ADDR(RB0_BASE, RB_COUNTER)); } diff --git a/fpga-src b/fpga-src -Subproject dd8147301da1dafe9cc985227317bc3cd12c528 +Subproject 4b1929a07a36f025bfcc97dc21daedf76fc887f diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt index 5c4a27b7f..12b24df0d 100644 --- a/host/CMakeLists.txt +++ b/host/CMakeLists.txt @@ -166,6 +166,22 @@ IF(MSVC) ADD_DEFINITIONS(/MP) #multi-threaded build ENDIF(MSVC) +IF(MINGW) + #Avoid depending on MinGW runtime DLLs + CHECK_CXX_COMPILER_FLAG(-static-libgcc HAVE_STATIC_LIBGCC_FLAG) + IF(HAVE_STATIC_LIBGCC_FLAG) + SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static-libgcc") + SET(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -static-libgcc") + SET(CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} -static-libgcc") + ENDIF() + CHECK_CXX_COMPILER_FLAG(-static-libstdc++ HAVE_STATIC_LIBSTDCXX_FLAG) + IF(HAVE_STATIC_LIBSTDCXX_FLAG) + SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static-libstdc++") + SET(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -static-libstdc++") + SET(CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} -static-libstdc++") + ENDIF() +ENDIF() + IF(CYGWIN) ADD_DEFINITIONS(-D__USE_W32_SOCKETS) #boost asio says we need this ENDIF(CYGWIN) @@ -235,9 +251,9 @@ PYTHON_CHECK_MODULE( ) PYTHON_CHECK_MODULE( - "Cheetah templates 2.0.0 or greater" - "Cheetah" "Cheetah.Version >= '2.0.0'" - HAVE_PYTHON_MODULE_CHEETAH + "Mako templates 0.4 or greater" + "mako" "mako.__version__ >= '0.4.2'" + HAVE_PYTHON_MODULE_MAKO ) ######################################################################## @@ -268,14 +284,14 @@ UHD_INSTALL(FILES #{{{IMG_SECTION # This section is written automatically by /images/create_imgs_package.py # Any manual changes in here will be overwritten. -SET(UHD_IMAGES_MD5SUM "eb2d694e0444f02752a988d14488064e") -SET(UHD_IMAGES_DOWNLOAD_SRC "uhd-images_003.008.005-rc1.zip") +SET(UHD_IMAGES_MD5SUM "05f558e044c75dc660afd8b384946f72") +SET(UHD_IMAGES_DOWNLOAD_SRC "uhd-images_003.009.git-214-g31b8d05c.zip") #}}} ######################################################################## # Register top level components ######################################################################## -LIBUHD_REGISTER_COMPONENT("LibUHD" ENABLE_LIBUHD ON "Boost_FOUND;HAVE_PYTHON_PLAT_MIN_VERSION;HAVE_PYTHON_MODULE_CHEETAH" OFF) +LIBUHD_REGISTER_COMPONENT("LibUHD" ENABLE_LIBUHD ON "Boost_FOUND;HAVE_PYTHON_PLAT_MIN_VERSION;HAVE_PYTHON_MODULE_MAKO" OFF) LIBUHD_REGISTER_COMPONENT("Examples" ENABLE_EXAMPLES ON "ENABLE_LIBUHD" OFF) LIBUHD_REGISTER_COMPONENT("Utils" ENABLE_UTILS ON "ENABLE_LIBUHD" OFF) LIBUHD_REGISTER_COMPONENT("Tests" ENABLE_TESTS ON "ENABLE_LIBUHD" OFF) @@ -285,7 +301,7 @@ LIBUHD_REGISTER_COMPONENT("Tests" ENABLE_TESTS ON "ENABLE_LIBUHD" OFF) ######################################################################## SET(HAS_FPGA_SUBMODULE FALSE) EXECUTE_PROCESS( - COMMAND ${PYTHON_EXECUTABLE} -c "import os; print os.path.abspath(os.path.join('${CMAKE_SOURCE_DIR}', '..', 'fpga-src'))" + COMMAND ${PYTHON_EXECUTABLE} -c "import os; print(os.path.abspath(os.path.join('${CMAKE_SOURCE_DIR}', '..', 'fpga-src')))" OUTPUT_VARIABLE FPGA_SUBMODULE_DIR OUTPUT_STRIP_TRAILING_WHITESPACE ) @@ -369,9 +385,6 @@ ENDFOREACH(Boost_Comp) IF(ENABLE_USB) LIST(APPEND UHD_LINK_LIST_STATIC "usb-1.0") ENDIF(ENABLE_USB) -IF(ENABLE_ORC) - LIST(APPEND UHD_LINK_LIST_STATIC "orc-0.4") -ENDIF(ENABLE_ORC) CONFIGURE_FILE( ${CMAKE_SOURCE_DIR}/cmake/Modules/UHDConfigVersion.cmake.in @@ -421,5 +434,19 @@ ELSEIF(UHDHOST_PKG) SET(PRINT_APPEND " (Debian uhd-host package configuration)") ENDIF(LIBUHD_PKG) UHD_PRINT_COMPONENT_SUMMARY() +IF(UHD_VERSION_DEVEL) + MESSAGE(STATUS "******************************************************") + IF(UHD_VERSION_PATCH STREQUAL "git") + MESSAGE(STATUS "* You are building the UHD development master branch.") + MESSAGE(STATUS "* For production code, we recommend our stable,") + MESSAGE(STATUS "* releases or using the release branch (maint).") + ELSE() + MESSAGE(STATUS "* You are building a development branch of UHD.") + MESSAGE(STATUS "* These branches are designed to provide early access") + MESSAGE(STATUS "* to UHD and USRP features, but should be considered") + MESSAGE(STATUS "* unstable and/or experimental!") + ENDIF(UHD_VERSION_PATCH STREQUAL "git") + MESSAGE(STATUS "******************************************************") +ENDIF(UHD_VERSION_DEVEL) MESSAGE(STATUS "Building version: ${UHD_VERSION}${PRINT_APPEND}") MESSAGE(STATUS "Using install prefix: ${CMAKE_INSTALL_PREFIX}") diff --git a/host/apps/omap_debug/.gitignore b/host/apps/omap_debug/.gitignore deleted file mode 100644 index 008a23138..000000000 --- a/host/apps/omap_debug/.gitignore +++ /dev/null @@ -1,20 +0,0 @@ -.gitignore -clkgen-config -fpga-downloader -usrp-e-button -usrp-e-crc-rw -usrp-e-ctl -usrp-e-debug-pins -usrp-e-fpga-rw -usrp-e-gpio -usrp-e-i2c -usrp-e-lb-test -usrp-e-led -usrp-e-loopback -usrp-e-random-loopback -usrp-e-rw -usrp-e-spi -usrp-e-timed -usrp-e-uart -usrp-e-uart-rx -usrp-e-mm-loopback diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile deleted file mode 100644 index f8b9f2bd9..000000000 --- a/host/apps/omap_debug/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 -CXXFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 - -all : usrp-e-spi usrp-e-i2c usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx usrp-e-gpio usrp-e-debug-pins - -usrp-e-spi : usrp-e-spi.c - -usrp-e-i2c : usrp-e-i2c.c - -usrp-e-uart : usrp-e-uart.c - -usrp-e-uart-rx : usrp-e-uart-rx.c - -usrp-e-led : usrp-e-led.c - -usrp-e-ctl : usrp-e-ctl.c - -usrp-e-button : usrp-e-button.c - -usrp-e-gpio : usrp-e-gpio.c - -usrp-e-debug-pins : usrp-e-debug-pins.c -clean : - rm -f usrp-e-spi - rm -f usrp-e-i2c - rm -f usrp-e-uart - rm -f usrp-e-uart-rx - rm -f usrp-e-led - rm -f usrp-e-ctl - rm -f usrp-e-button - rm -f usrp-e-gpio - rm -f usrp-e-debug-pins - rm -f usrp-e-lb-test diff --git a/host/apps/omap_debug/set_debug_pins.py b/host/apps/omap_debug/set_debug_pins.py deleted file mode 100755 index 0f9ecd7b9..000000000 --- a/host/apps/omap_debug/set_debug_pins.py +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/python - -import os - -# Memory Map -misc_base = 0 -uart_base = 1 -spi_base = 2 -i2c_base = 3 -gpio_base = 4 * 128 -settings_base = 5 - -# GPIO offset -gpio_pins = 0 -gpio_ddr = 4 -gpio_ctrl_lo = 8 -gpio_ctrl_hi = 12 - -def set_reg(reg, val): - os.system("./usrp1-e-ctl w %d 1 %d" % (reg,val)) - -def get_reg(reg): - fin,fout = os.popen4("./usrp1-e-ctl r %d 1" % (reg,)) - print fout.read() - -# Set DDRs to output -set_reg(gpio_base+gpio_ddr, 0xFFFF) -set_reg(gpio_base+gpio_ddr+2, 0xFFFF) - -# Set CTRL to Debug #0 ( A is for debug 0, F is for debug 1 ) -set_reg(gpio_base+gpio_ctrl_lo, 0xAAAA) -set_reg(gpio_base+gpio_ctrl_lo+2, 0xAAAA) -set_reg(gpio_base+gpio_ctrl_hi, 0xAAAA) -set_reg(gpio_base+gpio_ctrl_hi+2, 0xAAAA) - diff --git a/host/apps/omap_debug/test.c b/host/apps/omap_debug/test.c deleted file mode 100644 index 36f4d700a..000000000 --- a/host/apps/omap_debug/test.c +++ /dev/null @@ -1,34 +0,0 @@ -#include <stdio.h> - -void -main() -{ - int x; - char *y; - long long z; - - x = 0x01020304; - z = 0x0102030405060708LL; - - printf("%x\n",x); - y = (char *)&x; - printf("%x\n",y[0]); - printf("%x\n",y[1]); - printf("%x\n",y[2]); - printf("%x\n",y[3]); - - printf("Printing z ...\n"); - printf("%llx\n",z); - printf("Printing z done\n"); - - y = (char *)&z; - printf("%x\n",y[0]); - printf("%x\n",y[1]); - printf("%x\n",y[2]); - printf("%x\n",y[3]); - printf("%x\n",y[4]); - printf("%x\n",y[5]); - printf("%x\n",y[6]); - printf("%x\n",y[7]); -} - diff --git a/host/apps/omap_debug/u1e-read-stream.c b/host/apps/omap_debug/u1e-read-stream.c deleted file mode 100644 index 4e4c21d9e..000000000 --- a/host/apps/omap_debug/u1e-read-stream.c +++ /dev/null @@ -1,21 +0,0 @@ -#include <stdio.h> -#include <sys/types.h> -#include <fcntl.h> - -int main(int rgc, char *argv[]) -{ - int fp, cnt, n; - short buf[1024]; - - n = 0; - - fp = open("/dev/usrp1_e0", O_RDONLY); - printf("fp = %d\n", fp); - - do { - cnt = read(fp, buf, 2048); - n++; -// printf("Bytes read - %d\n", cnt); - } while(n < 10*512); - printf("Data - %hX\n", buf[0]); -} diff --git a/host/apps/omap_debug/usrp-e-button.c b/host/apps/omap_debug/usrp-e-button.c deleted file mode 100644 index f13291491..000000000 --- a/host/apps/omap_debug/usrp-e-button.c +++ /dev/null @@ -1,56 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <sys/types.h> -#include <fcntl.h> -#include <string.h> -#include <sys/ioctl.h> -#include <unistd.h> - -#include "usrp_e.h" -#include "usrp_e_regs.hpp" - -// Usage: usrp_e_uart <string> - -#define PB1 (1<<8) -#define PB2 (1<<9) -#define PB3 (1<<10) -#define P1 (0) -#define P2 (0xFF) -#define P3 (0xAA) -#define P4 (0x55) - -int main(int argc, char *argv[]) -{ - int fp, ret; - struct usrp_e_ctl16 d; - int pb1=0, pb2=0, pb3=0, p1=0, p2=0, p3=0, p4=0; - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - d.offset = UE_REG_MISC_SW; - d.count = 1; - - do { - ret = ioctl(fp, USRP_E_READ_CTL16, &d); - if (d.buf[0] & PB1) { - pb1 = 1; - printf("Pushbutton 1 hit\n"); - } - - if (d.buf[0] & PB2) { - pb2 = 1; - printf("Pushbutton 2 hit\n"); - } - - if (d.buf[0] & PB3) { - pb3 = 1; - printf("Pushbutton 3 hit\n"); - } - - sleep(1); - - } while (!(pb1 && pb2 && pb3)); - - return 0; -} diff --git a/host/apps/omap_debug/usrp-e-ctl.c b/host/apps/omap_debug/usrp-e-ctl.c deleted file mode 100644 index 69c48ee6f..000000000 --- a/host/apps/omap_debug/usrp-e-ctl.c +++ /dev/null @@ -1,48 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <sys/types.h> -#include <fcntl.h> -#include <sys/ioctl.h> - -#include "usrp_e.h" - -// Usage: usrp_e_ctl w|r offset number_of_values val1 val2 .... - -int main(int argc, char *argv[]) -{ - int fp, i, cnt, ret; - struct usrp_e_ctl16 ctl_data; - - if (argc < 4) { - printf("Usage: usrp_e_ctl w|r offset number_of_values val1 val2 ....\n"); - exit(-1); - } - - cnt = atoi(argv[3]); - - ctl_data.offset = atoi(argv[2]); - ctl_data.count = cnt; - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - if (*argv[1] == 'w') { - for (i=0; i<cnt; i++) - ctl_data.buf[i] = atoi(argv[4+i]); - - ret = ioctl(fp, USRP_E_WRITE_CTL16, &ctl_data); - printf("Return value from write ioctl = %d\n", ret); - } - - if (*argv[1] == 'r') { - ret = ioctl(fp, USRP_E_READ_CTL16, &ctl_data); - printf("Return value from write ioctl = %d\n", ret); - - for (i=0; i<ctl_data.count; i++) { - if (!(i%8)) - printf("\nData at %4d :", i); - printf(" %5d", ctl_data.buf[i]); - } - printf("\n"); - } -} diff --git a/host/apps/omap_debug/usrp-e-debug-pins.c b/host/apps/omap_debug/usrp-e-debug-pins.c deleted file mode 100644 index d18bbf990..000000000 --- a/host/apps/omap_debug/usrp-e-debug-pins.c +++ /dev/null @@ -1,77 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <unistd.h> -#include <sys/types.h> -#include <fcntl.h> -#include <string.h> -#include <sys/ioctl.h> - -#include "usrp_e.h" -#include "usrp_e_regs.hpp" - -// Usage: usrp_e_gpio <string> - -static int fp; - -static int read_reg(__u16 reg) -{ - int ret; - struct usrp_e_ctl16 d; - - d.offset = reg; - d.count = 1; - ret = ioctl(fp, USRP_E_READ_CTL16, &d); - return d.buf[0]; -} - -static void write_reg(__u16 reg, __u16 val) -{ - int ret; - struct usrp_e_ctl16 d; - - d.offset = reg; - d.count = 1; - d.buf[0] = val; - ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); -} - -int main(int argc, char *argv[]) -{ - int test; - - test = 0; - if (argc < 2) { - printf("%s 0|1|off\n", argv[0]); - } - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - if (fp < 0) { - perror("Open failed"); - return -1; - } - - if (strcmp(argv[1], "0") == 0) { - printf("Selected 0 based on %s\n", argv[1]); - write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); - write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); - write_reg(UE_REG_GPIO_TX_SEL, 0x0); - write_reg(UE_REG_GPIO_RX_SEL, 0x0); - write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); - write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); - } else if (strcmp(argv[1], "1") == 0) { - printf("Selected 1 based on %s\n", argv[1]); - write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); - write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); - write_reg(UE_REG_GPIO_TX_SEL, 0xFFFF); - write_reg(UE_REG_GPIO_RX_SEL, 0xFFFF); - write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); - write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); - } else { - printf("Selected off based on %s\n", argv[1]); - write_reg(UE_REG_GPIO_TX_DDR, 0x0); - write_reg(UE_REG_GPIO_RX_DDR, 0x0); - } - - return 0; -} diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c deleted file mode 100644 index da8709ae1..000000000 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ /dev/null @@ -1,87 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/types.h> -#include <fcntl.h> -#include <sys/ioctl.h> - -#include "usrp_e.h" - -// Usage: usrp_e_i2c w address data0 data1 data 2 .... -// Usage: usrp_e_i2c r address count - -int main(int argc, char *argv[]) -{ - int fp, ret, i, tmp; - struct usrp_e_i2c *i2c_msg; - int direction, address, count; - - if (argc < 3) { - printf("Usage: usrp-e-i2c w address data0 data1 data2 ...\n"); - printf("Usage: usrp-e-i2c r address count\n"); - printf("All addresses and data in hex.\n"); - exit(-1); - } - - if (strcmp(argv[1], "r") == 0) { - direction = 0; - } else if (strcmp(argv[1], "w") == 0) { - direction = 1; - } else { - return -1; - } - - sscanf(argv[2], "%X", &address); - printf("Address = %X\n", address); - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - if (fp < 0) { - perror("Open failed"); - return -1; - } - -// sleep(1); - - if (direction) { - count = argc - 3; - } else { - sscanf(argv[3], "%X", &count); - } - printf("Count = %X\n", count); - - i2c_msg = malloc(sizeof(i2c_msg) + count * sizeof(char)); - - i2c_msg->addr = address; - i2c_msg->len = count; - - for (i = 0; i < count; i++) { - i2c_msg->data[i] = i; - } - - if (direction) { - // Write - - for (i=0; i<count; i++) { - sscanf(argv[3+i], "%X", &tmp); - i2c_msg->data[i] = tmp; - } - - ret = ioctl(fp, USRP_E_I2C_WRITE, i2c_msg); - printf("Return value from i2c_write ioctl: %d\n", ret); - } else { - // Read - - ret = ioctl(fp, USRP_E_I2C_READ, i2c_msg); - printf("Return value from i2c_read ioctl: %d\n", ret); - - printf("Ioctl: %d Data read :", ret); - for (i=0; i<count; i++) { - printf(" %X", i2c_msg->data[i]); - } - printf("\n"); - - } - return 0; -} diff --git a/host/apps/omap_debug/usrp-e-lb-test.c b/host/apps/omap_debug/usrp-e-lb-test.c deleted file mode 100644 index 68848064e..000000000 --- a/host/apps/omap_debug/usrp-e-lb-test.c +++ /dev/null @@ -1,58 +0,0 @@ -#include <stdio.h> -#include <sys/types.h> -#include <fcntl.h> -#include <pthread.h> -#include <stdlib.h> -#include <unistd.h> -#include <stddef.h> -#include "usrp_e.h" - -// max length #define PKT_DATA_LENGTH 1016 - -int main(int argc, char *argv[]) -{ - struct usrp_transfer_frame *tx_data, *rx_data; - int i, fp, packet_data_length, cnt; - struct usrp_e_ctl16 d; - - if (argc < 2) { - printf("%s data_size (in bytes < 2040)\n", argv[0]); - return -1; - } - - packet_data_length = atoi(argv[1]); - - fp = open("/dev/usrp_e0", O_RDWR); - - d.offset = 14; - d.count = 1; - d.buf[0] = (1 << 13); - ioctl(fp, USRP_E_WRITE_CTL16, &d); - - tx_data = malloc(2048); - rx_data = malloc(2048); - - tx_data->status = 0; - tx_data->len = sizeof(struct usrp_transfer_frame) + packet_data_length; - - while (1) { - - for (i = 0; i < packet_data_length; i++) { - tx_data->buf[i] = random() >> 24; - - } - - cnt = write(fp, tx_data, 2048); - cnt = read(fp, rx_data, 2048); - - if (tx_data->len != rx_data->len) - printf("Bad frame length sent %d, read %d\n", tx_data->len, rx_data->len); - - for (i = 0; i < packet_data_length; i++) { - if (tx_data->buf[i] != rx_data->buf[i]) - printf("Bad data at %d, sent %d, received %d\n", i, tx_data->buf[i], rx_data->buf[i]); - } - printf("---------------------------------------------------\n"); - sleep(1); - } -} diff --git a/host/apps/omap_debug/usrp-e-led.c b/host/apps/omap_debug/usrp-e-led.c deleted file mode 100644 index d1b6c8996..000000000 --- a/host/apps/omap_debug/usrp-e-led.c +++ /dev/null @@ -1,35 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <sys/types.h> -#include <fcntl.h> -#include <string.h> -#include <sys/ioctl.h> -#include <unistd.h> - -#include "usrp_e.h" -#include "usrp_e_regs.hpp" - -// Usage: usrp_e_uart <string> - - -int main(int argc, char *argv[]) -{ - int fp, i, ret; - struct usrp_e_ctl16 d; - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - d.offset = UE_REG_MISC_BASE; - d.count = 1; - - while (1) { - for (i=0; i<8; i++) { - d.buf[0] = i; - ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); - sleep(1); - } - } - - return 0; -} diff --git a/host/apps/omap_debug/usrp-e-ram.c b/host/apps/omap_debug/usrp-e-ram.c deleted file mode 100644 index d548f7ccd..000000000 --- a/host/apps/omap_debug/usrp-e-ram.c +++ /dev/null @@ -1,25 +0,0 @@ -#include <stdio.h> -#include <sys/types.h> -#include <fcntl.h> - -int main(int rgc, char *argv[]) -{ - int fp, i, cnt; - unsigned short buf[1024]; - unsigned short buf_rb[1024]; - - fp = open("/dev/usrp1_e0", O_RDWR); - printf("fp = %d\n", fp); - - for (i=0; i<1024; i++) - buf[i] = i*256; - write(fp, buf, 2048); - read(fp, buf_rb, 2048); - - printf("Read back %hX %hX\n", buf_rb[0], buf_rb[1]); - - for (i=0; i<1024; i++) { - if (buf[i] != buf_rb[i]) - printf("Read - %hX, expected - %hX\n", buf_rb[i], buf[i]); - } -} diff --git a/host/apps/omap_debug/usrp-e-read.c b/host/apps/omap_debug/usrp-e-read.c deleted file mode 100644 index c28f018d5..000000000 --- a/host/apps/omap_debug/usrp-e-read.c +++ /dev/null @@ -1,18 +0,0 @@ -#include <stdio.h> -#include <sys/types.h> -#include <fcntl.h> - -int main(int rgc, char *argv[]) -{ - int fp, cnt; - short buf[1024]; - - fp = open("/dev/usrp1_e0", O_RDONLY); - printf("fp = %d\n", fp); - - do { - cnt = read(fp, buf, 2048); -// printf("Bytes read - %d\n", cnt); - } while(1); - printf("Data - %hX\n", buf[0]); -} diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c deleted file mode 100644 index c353c409b..000000000 --- a/host/apps/omap_debug/usrp-e-spi.c +++ /dev/null @@ -1,54 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <unistd.h> -#include <sys/types.h> -#include <fcntl.h> -#include <sys/ioctl.h> - -#include "usrp_e.h" - -// Usage: usrp_e_spi w|rb slave data - -int main(int argc, char *argv[]) -{ - int fp, slave, length, ret; - unsigned int data; - struct usrp_e_spi spi_dat; - - if (argc < 5) { - printf("Usage: usrp_e_spi w|rb slave transfer_length data\n"); - exit(-1); - } - - slave = atoi(argv[2]); - length = atoi(argv[3]); - data = atoll(argv[4]); - - printf("Data = %X\n", data); - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - if (fp < 0) { - perror("Open failed"); - return -1; - } - -// sleep(1); - - - spi_dat.slave = slave; - spi_dat.data = data; - spi_dat.length = length; - spi_dat.flags = UE_SPI_PUSH_FALL | UE_SPI_LATCH_RISE; - - if (*argv[1] == 'r') { - spi_dat.readback = 1; - ret = ioctl(fp, USRP_E_SPI, &spi_dat); - printf("Ioctl returns: %d, Data returned = %d\n", ret, spi_dat.data); - } else { - spi_dat.readback = 0; - ioctl(fp, USRP_E_SPI, &spi_dat); - } - - return 0; -} diff --git a/host/apps/omap_debug/usrp-e-uart-rx.c b/host/apps/omap_debug/usrp-e-uart-rx.c deleted file mode 100644 index 24b417980..000000000 --- a/host/apps/omap_debug/usrp-e-uart-rx.c +++ /dev/null @@ -1,53 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <sys/types.h> -#include <fcntl.h> -#include <string.h> -#include <sys/ioctl.h> - -#include "usrp_e.h" -#include "usrp_e_regs.hpp" - -// Usage: usrp_e_uart <string> - - -int main(int argc, char *argv[]) -{ - int fp, ret; - struct usrp_e_ctl16 d; - __u16 clkdiv; - - if (argc == 0) { - printf("Usage: usrp-e-uart-rx <opt clkdiv>\n"); - printf("clkdiv = 278 is 230.4k \n"); - printf("clkdiv = 556 is 115.2k \n"); - exit(-1); - } - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - if (argc == 2) { - clkdiv = atoi(argv[1]); - d.offset = UE_REG_UART_CLKDIV; - d.count = 1; - d.buf[0] = clkdiv; - ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); - } - - while(1) { - d.offset = UE_REG_UART_RXLEVEL; - d.count = 1; - ret = ioctl(fp, USRP_E_READ_CTL16, &d); - - if (d.buf[0] > 0) { - d.offset = UE_REG_UART_RXCHAR; - d.count = 1; - ret = ioctl(fp, USRP_E_READ_CTL16, &d); - printf("%c", d.buf[0]); - fflush(stdout); - } - } - - return 0; -} diff --git a/host/apps/omap_debug/usrp-e-uart.c b/host/apps/omap_debug/usrp-e-uart.c deleted file mode 100644 index 2956c407f..000000000 --- a/host/apps/omap_debug/usrp-e-uart.c +++ /dev/null @@ -1,48 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <sys/types.h> -#include <fcntl.h> -#include <string.h> -#include <sys/ioctl.h> - -#include "usrp_e.h" -#include "usrp_e_regs.hpp" - -// Usage: usrp_e_uart <string> - - -int main(int argc, char *argv[]) -{ - int fp, i, ret; - struct usrp_e_ctl16 d; - char *str = argv[1]; - __u16 clkdiv; - - if (argc < 2) { - printf("Usage: usrp_e_uart <string> <opt clkdiv>\n"); - printf("clkdiv = 278 is 230.4k \n"); - printf("clkdiv = 556 is 115.2k \n"); - exit(-1); - } - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - if (argc == 3) { - clkdiv = atoi(argv[2]); - d.offset = UE_REG_UART_CLKDIV; - d.count = 1; - d.buf[0] = clkdiv; - ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); - } - - for (i=0; i<strlen(str); i++) { - d.offset = UE_REG_UART_TXCHAR; - d.count = 1; - d.buf[0] = str[i]; - ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); - printf("Wrote %X, to %X, ret = %d\n", d.buf[0], d.offset, ret); - } - - return 0; -} diff --git a/host/apps/omap_debug/usrp-e-write.c b/host/apps/omap_debug/usrp-e-write.c deleted file mode 100644 index 903c0071f..000000000 --- a/host/apps/omap_debug/usrp-e-write.c +++ /dev/null @@ -1,21 +0,0 @@ -#include <stdio.h> -#include <sys/types.h> -#include <fcntl.h> - -int main(int rgc, char *argv[]) -{ - int fp, i, cnt; - short buf[1024]; - - fp = open("/dev/usrp1_e0", O_WRONLY); - printf("fp = %d\n", fp); - - for (i=0; i<1024; i++) { - buf[i] = i; - } - -// do { - cnt = write(fp, buf, 2048); - printf("Bytes written - %d\n", cnt); -// } while (1); -} diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h deleted file mode 100644 index 2c4aa2ac1..000000000 --- a/host/apps/omap_debug/usrp_e.h +++ /dev/null @@ -1,60 +0,0 @@ - -/* - * Copyright (C) 2010 Ettus Research, LLC - * - * Written by Philip Balister <philip@opensdr.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __USRP_E_H -#define __USRP_E_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -struct usrp_e_ctl16 { - __u32 offset; - __u32 count; - __u16 buf[20]; -}; - -struct usrp_e_ctl32 { - __u32 offset; - __u32 count; - __u32 buf[10]; -}; - -#define USRP_E_IOC_MAGIC 'u' -#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16) -#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16) -#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32) -#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32) -#define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t) -#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28) - -#define USRP_E_COMPAT_NUMBER 2 - -/* Flag defines */ -#define RB_USER (1<<0) -#define RB_KERNEL (1<<1) -#define RB_OVERRUN (1<<2) -#define RB_DMA_ACTIVE (1<<3) -#define RB_USER_PROCESS (1<<4) - -struct ring_buffer_info { - int flags; - int len; -}; - -struct usrp_e_ring_buffer_size_t { - int num_pages_rx_flags; - int num_rx_frames; - int num_pages_tx_flags; - int num_tx_frames; -}; - -#endif diff --git a/host/cmake/Modules/FindORC.cmake b/host/cmake/Modules/FindORC.cmake deleted file mode 100644 index e13eae235..000000000 --- a/host/cmake/Modules/FindORC.cmake +++ /dev/null @@ -1,36 +0,0 @@ -######################################################################## -# Find the library for ORC development files -######################################################################## - -INCLUDE(FindPkgConfig) -PKG_CHECK_MODULES(PC_ORC "orc-0.4") -PKG_CHECK_MODULES(PC_ORC_V4_11 "orc-0.4 > 0.4.11") - -#we are using the pkg config as a version check -#if we have pkg config, the right version must be found -#the alternative is that no pkg config orc is found -if (PC_ORC_V4_11_FOUND OR NOT PC_ORC_FOUND) - -FIND_PATH( - ORC_INCLUDE_DIRS - NAMES orc/orc.h - HINTS $ENV{ORC_DIR}/include/orc-0.4 - ${PC_ORC_INCLUDEDIR} - PATHS /usr/local/include/orc-0.4 - /usr/include/orc-0.4 -) - -FIND_LIBRARY( - ORC_LIBRARIES - NAMES orc-0.4 - HINTS $ENV{ORC_DIR}/lib - ${PC_ORC_LIBDIR} - PATHS /usr/local/lib - /usr/lib -) - -endif() #both PC ORC FOUND - -INCLUDE(FindPackageHandleStandardArgs) -FIND_PACKAGE_HANDLE_STANDARD_ARGS(ORC DEFAULT_MSG ORC_LIBRARIES ORC_INCLUDE_DIRS) -MARK_AS_ADVANCED(ORC_LIBRARIES ORC_INCLUDE_DIRS) diff --git a/host/cmake/Modules/UHDPython.cmake b/host/cmake/Modules/UHDPython.cmake index fdcdccb4b..a3da150a1 100644 --- a/host/cmake/Modules/UHDPython.cmake +++ b/host/cmake/Modules/UHDPython.cmake @@ -51,7 +51,7 @@ MESSAGE(STATUS "Python interpreter: ${PYTHON_EXECUTABLE}") MESSAGE(STATUS "Override with: -DPYTHON_EXECUTABLE=<path-to-python>") IF(NOT PYTHONINTERP_FOUND) - MESSAGE(FATAL_ERROR "Error: Python interpretor required by the build system.") + MESSAGE(FATAL_ERROR "Error: Python interpreter required by the build system.") ENDIF(NOT PYTHONINTERP_FOUND) MACRO(PYTHON_CHECK_MODULE desc mod cmd have) diff --git a/host/cmake/Modules/UHDVersion.cmake b/host/cmake/Modules/UHDVersion.cmake index 66b4402ed..b8b256834 100644 --- a/host/cmake/Modules/UHDVersion.cmake +++ b/host/cmake/Modules/UHDVersion.cmake @@ -27,9 +27,9 @@ FIND_PACKAGE(Git QUIET) # - set UHD_VERSION_DEVEL to true for master and development branches ######################################################################## SET(UHD_VERSION_MAJOR 003) -SET(UHD_VERSION_MINOR 008) -SET(UHD_VERSION_PATCH 005) -SET(UHD_VERSION_DEVEL FALSE) +SET(UHD_VERSION_MINOR 009) +SET(UHD_VERSION_PATCH git) +SET(UHD_VERSION_DEVEL TRUE) ######################################################################## # Set up trimmed version numbers for DLL resource files and packages @@ -38,7 +38,7 @@ SET(UHD_VERSION_DEVEL FALSE) FUNCTION(DEPAD_NUM input_num output_num) EXECUTE_PROCESS( WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND ${PYTHON_EXECUTABLE} -c "print int('${input_num}')" + COMMAND ${PYTHON_EXECUTABLE} -c "print(int('${input_num}'))" OUTPUT_VARIABLE depadded_num OUTPUT_STRIP_TRAILING_WHITESPACE ) SET(${output_num} ${depadded_num} PARENT_SCOPE) @@ -69,12 +69,12 @@ EXECUTE_PROCESS( IF(_git_describe_result EQUAL 0) EXECUTE_PROCESS( WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} - COMMAND ${PYTHON_EXECUTABLE} -c "print '${_git_describe}'.split('-')[-2]" + COMMAND ${PYTHON_EXECUTABLE} -c "print('${_git_describe}'.split('-')[-2])" OUTPUT_VARIABLE UHD_GIT_COUNT OUTPUT_STRIP_TRAILING_WHITESPACE ) EXECUTE_PROCESS( WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} - COMMAND ${PYTHON_EXECUTABLE} -c "print '${_git_describe}'.split('-')[-1]" + COMMAND ${PYTHON_EXECUTABLE} -c "print('${_git_describe}'.split('-')[-1])" OUTPUT_VARIABLE UHD_GIT_HASH OUTPUT_STRIP_TRAILING_WHITESPACE ) ENDIF() diff --git a/host/cmake/Toolchains/mingw_cross.cmake b/host/cmake/Toolchains/mingw_cross.cmake new file mode 100644 index 000000000..7c5adb002 --- /dev/null +++ b/host/cmake/Toolchains/mingw_cross.cmake @@ -0,0 +1,69 @@ +# Use this command: +# +# cmake -DCMAKE_TOOLCHAIN_FILE=cmake/Toolchain-mingw.cmake . +# +# or for out of source: +# +# cmake -DCMAKE_TOOLCHAIN_FILE=../cmake/Toolchain-mingw.cmake .. +# +# You will need at least CMake 2.6.0. +# +# Adjust the following paths to suit your environment. +# +# This file was based on http://www.cmake.org/Wiki/CmakeMingw + +# the name of the target operating system +set(CMAKE_SYSTEM_NAME Windows) + +# Assume the target architecture. +# XXX for some reason the value set here gets cleared before we reach the +# main CMakeLists.txt; see that file for a workaround. +# set(CMAKE_SYSTEM_PROCESSOR i686) + +# Which compilers to use for C and C++, and location of target +# environment. +if(EXISTS /usr/i586-mingw32msvc) + # First look in standard location as used by Debian/Ubuntu/etc. + set(CMAKE_C_COMPILER i586-mingw32msvc-gcc) + set(CMAKE_CXX_COMPILER i586-mingw32msvc-g++) + set(CMAKE_RC_COMPILER i586-mingw32msvc-windres) + set(CMAKE_FIND_ROOT_PATH /usr/i586-mingw32msvc) +elseif(EXISTS /usr/i686-w64-mingw32) + # First look in standard location as used by Debian/Ubuntu/etc. + set(CMAKE_C_COMPILER i686-w64-mingw32-gcc) + set(CMAKE_CXX_COMPILER i686-w64-mingw32-g++) + set(CMAKE_RC_COMPILER i686-w64-mingw32-windres) + set(CMAKE_AR:FILEPATH /usr/bin/i686-w64-mingw32-ar) +elseif(EXISTS /opt/mingw) + # You can get a MinGW environment using the script at <http://mxe.cc>. + # It downloads and builds MinGW and most of the dependencies for you. + # You can use the toolchain file generated by MXE called `mxe-conf.cmake' + # or you can use this file by adjusting the above and following paths. + set(CMAKE_C_COMPILER /opt/mingw/usr/bin/i686-pc-mingw32-gcc) + set(CMAKE_CXX_COMPILER /opt/mingw/usr/bin/i686-pc-mingw32-g++) + set(CMAKE_RC_COMPILER /opt/mingw/usr/bin/i686-pc-mingw32-windres) + set(CMAKE_FIND_ROOT_PATH /opt/mingw/usr/i686-pc-mingw32) +else() + # Else fill in local path which the user will likely adjust. + # This is the location assumed by <http://www.libsdl.org/extras/win32/cross/> + set(CMAKE_C_COMPILER /usr/local/cross-tools/bin/i386-mingw32-gcc) + set(CMAKE_CXX_COMPILER /usr/local/cross-tools/bin/i386-mingw32-g++) + set(CMAKE_RC_COMPILER /usr/local/cross-tools/bin/i386-mingw32-windres) + set(CMAKE_FIND_ROOT_PATH /usr/local/cross-tools) +endif() + +# Adjust the default behaviour of the FIND_XXX() commands: +# search headers and libraries in the target environment, search +# programs in the host environment +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +# Tell pkg-config not to look at the target environment's .pc files. +# Setting PKG_CONFIG_LIBDIR sets the default search directory, but we have to +# set PKG_CONFIG_PATH as well to prevent pkg-config falling back to the host's +# path. +set(ENV{PKG_CONFIG_LIBDIR} ${CMAKE_FIND_ROOT_PATH}/lib/pkgconfig) +set(ENV{PKG_CONFIG_PATH} ${CMAKE_FIND_ROOT_PATH}/lib/pkgconfig) + +set(ENV{MINGDIR} ${CMAKE_FIND_ROOT_PATH}) diff --git a/host/cmake/Toolchains/oe-sdk_cross.cmake b/host/cmake/Toolchains/oe-sdk_cross.cmake index ea77815c9..f8ef0157c 100644 --- a/host/cmake/Toolchains/oe-sdk_cross.cmake +++ b/host/cmake/Toolchains/oe-sdk_cross.cmake @@ -9,5 +9,3 @@ set( CMAKE_FIND_ROOT_PATH $ENV{OECORE_NATIVE_SYSROOT} $ENV{OECORE_TARGET_SYSROOT set( CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER ) set( CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY ) set( CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY ) -set ( ORC_INCLUDE_DIRS $ENV{OECORE_TARGET_SYSROOT}/usr/include/orc-0.4 ) -set ( ORC_LIBRARY_DIRS $ENV{OECORE_TARGET_SYSROOT}/usr/lib ) diff --git a/host/docs/build.dox b/host/docs/build.dox index 1097ab5ab..f3fdf5aa6 100644 --- a/host/docs/build.dox +++ b/host/docs/build.dox @@ -11,7 +11,7 @@ package manager. <b>Mac OS X Notes:</b> Install the Xcode app to get the build tools (GCC and Make). -Use MacPorts to get the Boost and Cheetah dependencies. +Use MacPorts to get the Boost and Mako dependencies. Other dependencies can be downloaded as DMG installers from the web or installed via MacPorts. See the UHD OS X build instructions for more information: \ref build_instructions_osx @@ -57,22 +57,20 @@ Other compilers (or lower versions) may work, but are unsupported. ### Python -- **Purpose:** used by Cheetah and utility scripts +- **Purpose:** used by mako and utility scripts - **Minimum Version:** 2.6 - **Usage:** build time + runtime utility scripts (required) - **Download URL:** http://www.python.org/download/ -### Cheetah +### Mako - **Purpose:** source code generation -- **Minimum Version:** 2.0 +- **Minimum Version:** 0.5.0 - **Usage:** build time (required) -- **Download URL:** http://www.cheetahtemplate.org/download.html -- **Download URL (Windows installer):** http://feisley.com/python/cheetah/ +- **Download URL:** http://www.makotemplates.org/download.html **Alternative method:** -Install **setuptools**, and use the **easy_install** command to install Cheetah. -http://pypi.python.org/pypi/setuptools +You can use `pip` or `easy_install` to install Mako from PyPi. ### Doxygen @@ -96,7 +94,7 @@ or install msysGit from http://code.google.com/p/msysgit/downloads/list. You can install all the dependencies through the package manager: - sudo apt-get install libboost-all-dev libusb-1.0-0-dev python-cheetah doxygen python-docutils cmake + sudo apt-get install libboost-all-dev libusb-1.0-0-dev python-mako doxygen python-docutils cmake Your actual command may differ. @@ -104,7 +102,7 @@ Your actual command may differ. You can install all the dependencies through the package manager: - sudo yum -y install boost-devel libusb1-devel python-cheetah doxygen python-docutils cmake + sudo yum -y install boost-devel libusb1-devel python-mako doxygen python-docutils cmake Your actual command may differ. diff --git a/host/docs/dboards.dox b/host/docs/dboards.dox index 3d6866a42..812a3a09e 100644 --- a/host/docs/dboards.dox +++ b/host/docs/dboards.dox @@ -372,6 +372,10 @@ Sensors: - **rssi**: float for measured RSSI in dBm - **temperature**: float for measured temperature in degC +\subsection dboards_e300 E310 MIMO XCVR board + +Please refer to \ref e3x0_dboard_e310. + \subsection dboards_dbsrxmod DBSRX - Modifying for other boards that USRP1 Due to different clocking capabilities, the DBSRX will require diff --git a/host/docs/octoclock.dox b/host/docs/octoclock.dox index 45a12e93a..58d2b1f99 100644 --- a/host/docs/octoclock.dox +++ b/host/docs/octoclock.dox @@ -7,41 +7,24 @@ - Hardware Capabilities: - Fully integrated timing source with 8-Way distribution (10 MHz and 1 PPS) - User selection between internal GPSDO (when present) or external 10 MHz/1 PPS source + - Ethernet bootloader for easy firmware upgrade - Source detection with automatic switch over in case of failure or disconnect - Streaming GPS time and NMEA strings over Ethernet (OctoClock-G only) \section octoclock_load Loading Firmware onto the Octoclock -\subsection bootloader OctoClock bootloader - -If you purchased your OctoClock device before Ethernet functionality was introduced, or if your unit's -bootloader has somehow become corrupted, you must burn the bootloader onto the device before you can load -the primary firmware. - -To load the bootloader onto the OctoClock, two things are needed: - -- AVR programmer -- AVRdude software - -Connect the AVR programmer to J108, as specified on the <a href="http://files.ettus.com/schematics/octoclock/octoclock.pdf"> -schematics</a>. Once you verify that the programmer is properly connected, run the following commands to burn the firmware: +First, the OctoClock's bootloader needs to be loaded onto the device. Connect the AVR programmer to J108, as +specified on the <a href="http://files.ettus.com/schematics/octoclock/octoclock.pdf">schematics</a>. Once you +verify that the programmer is properly connected, run the following commands to load the bootloader: cd <install path>/share/uhd/images - avrdude -p atmega128 -c <programmer name> -P usb -U efuse:w:0xFF:m -U hfuse:w:0x80:m -U lfuse:w:0xFF:m -U flash:w:octoclock_bootloader.hex:i + avrdude -p atmega128 -c <programmer name> -P usb -U efuse:w:0xFF:m -U hfuse:w:0x80:m -U lfuse:w:0xEF:m -U flash:w:octoclock_r4_fw.hex:i + +When the bootloader is loaded, it will have a default IP address of `192.168.10.3`. \b Note: On Linux, `sudo avrdude ...` might be necessary to gain access to the programmer. -Once the bootloader has been burned, power-cycle your OctoClock device and refer to the below instructions on burning the OctoClock's -primary firmware. - -\subsection application Primary Octoclock firmware - -To load firmware onto the OctoClock, you must use the `octoclock_firmware_burner` utility, specifying the IP -address of the OctoClock device, as follows: - - octoclock_firmware_burner --addr=192.168.10.3 - \section octoclock_network Setting Up Networking \subsection host_interface Setting up the host interface diff --git a/host/docs/uhd.dox b/host/docs/uhd.dox index 949c710b1..fcd0a25b0 100644 --- a/host/docs/uhd.dox +++ b/host/docs/uhd.dox @@ -12,6 +12,7 @@ Some additional pages on developing UHD are also available here: \li \subpage page_coding \li \subpage page_converters \li \subpage page_stream +\li \subpage page_rtp */ // vim:ft=doxygen: diff --git a/host/docs/usrp_b200.dox b/host/docs/usrp_b200.dox index bd79c4470..1da7f2aee 100644 --- a/host/docs/usrp_b200.dox +++ b/host/docs/usrp_b200.dox @@ -38,15 +38,40 @@ images: The master clock rate feeds the RF frontends and the DSP chains. Users may select non-default clock rates to acheive integer decimations or -interpolations in the DSP chains. The default master clock rate defaults -to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz. +interpolations in the DSP chains. The clock rate can be set to any value +between 5 MHz and 61.44 MHz (or 30.72 MHz for dual-channel mode). +Note that rates above 56 MHz are possible, but not recommended. The user can set the master clock rate through the usrp API call uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the -device arguments, which many applications take: : +device arguments, which many applications take: uhd_usrp_probe --args="master_clock_rate=52e6" +The property to control the master clock rate is a double value, called `tick_rate`. + +\subsection b200_auto_mcr Automatic Clock Rate Setting + +The default clock rate setting is to automatically set a clock rate +depending on the requested sampling rate. The automatic clock rate selection +is disabled when either `master_clock_rate` is given in the device initialization +arguments, or when uhd::usrp::multi_usrp::set_master_clock_rate() is called. + +Note that the master clock rate must be an integer multiple of the sampling +rate. If a master clock rate is chosen for which this condition does not +hold, a warning will be displayed and a different sampling rate is used internally. + +Nevertheless, there are multiple valid values for the master clock rate +for most sampling rates. The auto clock rate selection attempts to use +the largest possible clock rate as to enable as many half-band filters +as possible. Expert users might have cases where a more fine-grained +control over the resampling stages is required, in which case manually +selecting a master clock rate might be more suitable than the automatic +rate. + +The property to dis- or enable the auto tick rate is a boolean value, +`auto_tick_rate`. + \section b200_fe RF Frontend Notes The B200 features an integrated RF frontend. diff --git a/host/docs/usrp_e3x0.dox b/host/docs/usrp_e3x0.dox index a05914bba..ff03dedcd 100644 --- a/host/docs/usrp_e3x0.dox +++ b/host/docs/usrp_e3x0.dox @@ -188,9 +188,9 @@ builds) $ export MACHINE="ettus-e300" $ bitbake gnuradio-dev-image \endcode -When this completes, the files needed to create the sd card are in -`tmp-glibc/deploy/images/ettus-e300`. See \ref e3x0_upgrade_sd_card for instructions to write the image to your sd card. +When this completes, the files needed to create the SD card are in +`tmp-glibc/deploy/images/ettus-e300` -# Build the toolchain. \code{.sh} @@ -544,7 +544,7 @@ usrp->set_rx_subdev_spec("A:A A:B"); The following sensors are available for the USRP-E Series motherboards; they can be queried through the API. -- **fe_locked** - rx / tx frontend pll locked +- **fe_locked** - rx / tx frontend PLL locked - **temp** - processor temperature value - **gps_time** and **gps_locked** sensors are added when the GPS is found diff --git a/host/docs/usrp_x3x0_config.dox b/host/docs/usrp_x3x0_config.dox index 2ee449cc2..ed80c31de 100644 --- a/host/docs/usrp_x3x0_config.dox +++ b/host/docs/usrp_x3x0_config.dox @@ -320,38 +320,12 @@ Real-time scheduling is enabled via different methods depending on your application and operating system. In GNU Radio Companion, it can be turned on in each individual flowgraph. -\subsection x3x0cfg_hostpc_volk Building with ORC & Volk +\subsection x3x0cfg_hostpc_volk SIMD Acceleration Especially when running high-performance applications, processing -performance can be dramatically improved by SIMD instructions. UHD uses -ORC to provide SIMD capability, and GNU Radio includes a SIMD library -called "Volk". These should both be used to guarantee optimum -performance. - -\subsubsection x3x0cfg_hostpc_volk_orc Compiling UHD with ORC - -ORC, the <a href="http://code.entropywave.com/orc/">Oil Runtime Compiler</a>, -is a third-party compiler that UHD uses to create efficient SIMD code for -your particular computer. ORC is generally easily installed from your -OS's package manager. - -On Fedora: - - $ sudo yum update; sudo yum install orc-compiler orc-devel - -On Ubuntu: - - $ sudo apt-get update; sudo apt-get install liborc-<version> liborc-<version>-dev - -After installing ORC, when building UHD from source, you should see -"ORC" as one of the configured UHD components. - - -- ###################################################### - -- # UHD enabled components - -- ###################################################### - -- * LibUHD - <cut for brevity> - -- * ORC +performance can be dramatically improved by SIMD instructions. +GNU Radio includes a SIMD library +called "Volk", which should be used to guarantee optimum performance. \subsubsection x3x0cfg_hostpc_volk_volk Compiling GNURadio with Volk diff --git a/host/docs/vrt_chdr.dox b/host/docs/vrt_chdr.dox new file mode 100644 index 000000000..8ab177b21 --- /dev/null +++ b/host/docs/vrt_chdr.dox @@ -0,0 +1,83 @@ +/*! \page page_rtp Radio Transport Protocols + +\tableofcontents + +Radio transport protocols are used to exchange samples (or other items) between host and devices. +If one were to sniff Ethernet traffic between a USRP and a PC, the packets would conform to a +radio transport protocol. + +For USRP devices, two radio transport protocols are relevent: VRT (the VITA Radio Transport protocol) +and CVITA (compressed VITA), also known as CHDR. Generation-3 devices and the B200 use CHDR, the rest +use VRT. + +\section rtp_vrt VRT + +VRT is an open protocol defined by the VITA-49 standard. It was designed for interoperability, +and to allow different device types to work with different software stacks. + +VRT is a very verbose standard, and only a subset is implemented in UHD/USRPs. +The full standard is available from the VITA website: http://www.vita.com . + + +\section rtp_chdr CVITA (CHDR) + +For the third generation of Ettus devices, a new type transport protocol was designed. +It reduces the complexity of the original standard and uses a fixed-length 64-Bit header +for everything except the timestamp. Because this is a "compressed" form of VITA, it +was dubbed "Compressed VITA" (CVITA). The compressed header is called CHDR, which is why +the protocol is often called CHDR itself (pronounced like the cheese "cheddar"). + +By compressing all information into a 64-bit line, the header can efficiently be parsed +in newer FPGAs, where the common streaming protocol is 64-Bit AXI. The first line in a +packet already provides all necessary information to proceed. + +Some CHDR-specific functions can be found in: uhd::transport::vrt::chdr. + +The form of a CVITA packet is the following: + +Address (Bytes) | Length (Bytes) | Payload +----------------|----------------|---------------------------- +0 | 8 | Compressed Header (CHDR) +8 | 8 | Fractional Time (Optional!) +8/16 | - | Data + +If there is no timestamp present, the data starts at address 8, otherwise, it starts at 16. + +The 64 Bits in the compressed header have the following meaning: + +Bits | Meaning +-------|-------------------------------------------------- +63:62 | Packet Type +61 | Has fractional time stamp (1: Yes) +60 | End-of-burst or error flag +59:48 | 12-bit sequence number +47:32 | Total packet length in Bytes +31:0 | Stream ID (SID) + + +The packet type is determined mainly by the first two bits, although +the EOB or error flag are also taken into consideration: + +Bit 63 | Bit 62 | Bit 60 | Packet Type +-------|--------|--------|-------------- +0 | 0 | 0 | Data +0 | 0 | 1 | Data (End-of-burst) +0 | 1 | 0 | Flow Control +1 | 0 | 0 | Command Packet +1 | 1 | 0 | Command Response +1 | 1 | 1 | Command Response (Error) + +\section vrt_tools Tools + +For CHDR, we provide a Wireshark dissector under tools/chdr_dissector. It can be used +for Ethernet links as well as USB (e.g., for the B210). + +\section vrt_code Code + +Relevent code sections for the radio transport layer are: +* uhd::transport::vrt - Namespace for radio transport protocol related functions and definitions +* uhd::transport::vrt::chdr - Sub-namespace specifically for CVITA/CHDR +* uhd::sid_t - Datatype to represent SIDs + +*/ +// vim:ft=doxygen: diff --git a/host/examples/CMakeLists.txt b/host/examples/CMakeLists.txt index 1e6f2f013..92947d86c 100644 --- a/host/examples/CMakeLists.txt +++ b/host/examples/CMakeLists.txt @@ -29,14 +29,13 @@ SET(example_sources test_messages.cpp test_pps_input.cpp test_timed_commands.cpp - transport_hammer.cpp tx_bursts.cpp tx_samples_from_file.cpp tx_timed_samples.cpp tx_waveforms.cpp txrx_loopback_to_file.cpp latency_test.cpp - fpgpio.cpp + gpio.cpp ) IF(ENABLE_OCTOCLOCK) diff --git a/host/examples/benchmark_rate.cpp b/host/examples/benchmark_rate.cpp index 03d8f3477..cc3ef04a4 100644 --- a/host/examples/benchmark_rate.cpp +++ b/host/examples/benchmark_rate.cpp @@ -43,7 +43,12 @@ unsigned long long num_seq_errors = 0; /*********************************************************************** * Benchmark RX Rate **********************************************************************/ -void benchmark_rx_rate(uhd::usrp::multi_usrp::sptr usrp, const std::string &rx_cpu, uhd::rx_streamer::sptr rx_stream){ +void benchmark_rx_rate( + uhd::usrp::multi_usrp::sptr usrp, + const std::string &rx_cpu, + uhd::rx_streamer::sptr rx_stream, + bool random_nsamps +) { uhd::set_thread_priority_safe(); //print pre-test summary @@ -68,15 +73,19 @@ void benchmark_rx_rate(uhd::usrp::multi_usrp::sptr usrp, const std::string &rx_c rx_stream->issue_stream_cmd(cmd); while (not boost::this_thread::interruption_requested()){ + if (random_nsamps) { + cmd.num_samps = rand() % max_samps_per_packet; + rx_stream->issue_stream_cmd(cmd); + } try { - num_rx_samps += rx_stream->recv(buffs, max_samps_per_packet, md)*rx_stream->get_num_channels(); + num_rx_samps += rx_stream->recv(buffs, max_samps_per_packet, md)*rx_stream->get_num_channels(); } catch (...) { - /* apparently, the boost thread interruption can sometimes result in - throwing exceptions not of type boost::exception, this catch allows - this thread to still attempt to issue the STREAM_MODE_STOP_CONTINUOUS - */ - break; + /* apparently, the boost thread interruption can sometimes result in + throwing exceptions not of type boost::exception, this catch allows + this thread to still attempt to issue the STREAM_MODE_STOP_CONTINUOUS + */ + break; } //handle the error codes @@ -109,7 +118,12 @@ void benchmark_rx_rate(uhd::usrp::multi_usrp::sptr usrp, const std::string &rx_c /*********************************************************************** * Benchmark TX Rate **********************************************************************/ -void benchmark_tx_rate(uhd::usrp::multi_usrp::sptr usrp, const std::string &tx_cpu, uhd::tx_streamer::sptr tx_stream){ +void benchmark_tx_rate( + uhd::usrp::multi_usrp::sptr usrp, + const std::string &tx_cpu, + uhd::tx_streamer::sptr tx_stream, + bool random_nsamps=false +) { uhd::set_thread_priority_safe(); //print pre-test summary @@ -127,9 +141,25 @@ void benchmark_tx_rate(uhd::usrp::multi_usrp::sptr usrp, const std::string &tx_c buffs.push_back(&buff.front()); //same buffer for each channel md.has_time_spec = (buffs.size() != 1); - while (not boost::this_thread::interruption_requested()){ - num_tx_samps += tx_stream->send(buffs, max_samps_per_packet, md)*tx_stream->get_num_channels();; - md.has_time_spec = false; + if (random_nsamps) { + std::srand( (unsigned int)time(NULL) ); + while(not boost::this_thread::interruption_requested()){ + size_t total_num_samps = rand() % max_samps_per_packet; + size_t num_acc_samps = 0; + const float timeout = 1; + + usrp->set_time_now(uhd::time_spec_t(0.0)); + while(num_acc_samps < total_num_samps){ + //send a single packet + num_tx_samps += tx_stream->send(buffs, max_samps_per_packet, md, timeout)*tx_stream->get_num_channels(); + num_acc_samps += std::min(total_num_samps-num_acc_samps, tx_stream->get_max_num_samps()); + } + } + } else { + while (not boost::this_thread::interruption_requested()){ + num_tx_samps += tx_stream->send(buffs, max_samps_per_packet, md)*tx_stream->get_num_channels(); + md.has_time_spec = false; + } } //send a mini EOB packet @@ -182,6 +212,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::string rx_cpu, tx_cpu; std::string mode; std::string channel_list; + bool random_nsamps = false; //setup the program options po::options_description desc("Allowed options"); @@ -196,6 +227,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("rx_cpu", po::value<std::string>(&rx_cpu)->default_value("fc32"), "specify the host/cpu sample mode for RX") ("tx_cpu", po::value<std::string>(&tx_cpu)->default_value("fc32"), "specify the host/cpu sample mode for TX") ("mode", po::value<std::string>(&mode)->default_value("none"), "multi-channel sync mode option: none, mimo") + ("random", "Run with random values of samples in send() and recv() to stress-test the I/O.") ("channels", po::value<std::string>(&channel_list)->default_value("0"), "which channel(s) to use (specify \"0\", \"1\", \"0,1\", etc)") ; po::variables_map vm; @@ -213,6 +245,12 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ return ~0; } + // Random number of samples? + if (vm.count("random")) { + std::cout << "Using random number of samples in send() and recv() calls." << std::endl; + random_nsamps = true; + } + //create a usrp device std::cout << std::endl; uhd::device_addrs_t device_addrs = uhd::device::find(args, uhd::device::USRP); @@ -251,7 +289,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ uhd::stream_args_t stream_args(rx_cpu, rx_otw); stream_args.channels = channel_nums; uhd::rx_streamer::sptr rx_stream = usrp->get_rx_stream(stream_args); - thread_group.create_thread(boost::bind(&benchmark_rx_rate, usrp, rx_cpu, rx_stream)); + thread_group.create_thread(boost::bind(&benchmark_rx_rate, usrp, rx_cpu, rx_stream, random_nsamps)); } //spawn the transmit test thread @@ -261,7 +299,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ uhd::stream_args_t stream_args(tx_cpu, tx_otw); stream_args.channels = channel_nums; uhd::tx_streamer::sptr tx_stream = usrp->get_tx_stream(stream_args); - thread_group.create_thread(boost::bind(&benchmark_tx_rate, usrp, tx_cpu, tx_stream)); + thread_group.create_thread(boost::bind(&benchmark_tx_rate, usrp, tx_cpu, tx_stream, random_nsamps)); thread_group.create_thread(boost::bind(&benchmark_tx_rate_async_helper, tx_stream)); } @@ -287,6 +325,5 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //finished std::cout << std::endl << "Done!" << std::endl << std::endl; - return EXIT_SUCCESS; } diff --git a/host/examples/fpgpio.cpp b/host/examples/fpgpio.cpp deleted file mode 100644 index c57893669..000000000 --- a/host/examples/fpgpio.cpp +++ /dev/null @@ -1,418 +0,0 @@ -// -// Copyright 2014 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -// Example for front panel GPIO. -// Bits are set as follows: -// FPGPIO[0] = ATR output 1 at idle -// FPGPIO[1] = ATR output 1 during RX -// FPGPIO[2] = ATR output 1 during TX -// FPGPIO[3] = ATR output 1 during full duplex -// FPGPIO[4] = output -// FPGPIO[5] = input -// FPGPIO[6] = input (X series only) -// FPGPIO[7] = input (X series only) -// FPGPIO[8] = input (X series only) -// FPGPIO[9] = input (X series only) -// FPGPIO[10] = input (X series only) -// The example cycles through idle, TX, RX, and full duplex, spending 2 seconds for each. -// Outputs can be physically looped back to inputs for verification testing. - -#include <uhd/utils/thread_priority.hpp> -#include <uhd/utils/safe_main.hpp> -#include <uhd/usrp/multi_usrp.hpp> -#include <uhd/convert.hpp> -#include <boost/program_options.hpp> -#include <boost/format.hpp> -#include <boost/cstdint.hpp> -#include <boost/thread.hpp> -#include <csignal> -#include <iostream> - -static const std::string FPGPIO_DEFAULT_CPU_FORMAT = "fc32"; -static const std::string FPGPIO_DEFAULT_OTW_FORMAT = "sc16"; -static const double FPGPIO_DEFAULT_RX_RATE = 500e3; -static const double FPGPIO_DEFAULT_TX_RATE = 500e3; -static const double FPGPIO_DEFAULT_DWELL_TIME = 2.0; -static const std::string FPGPIO_DEFAULT_GPIO = "FP0"; -static const size_t FPGPIO_DEFAULT_NUM_BITS = 11; - -static UHD_INLINE boost::uint32_t FPGPIO_BIT(const size_t x) -{ - return (1 << x); -} - -namespace po = boost::program_options; - -static bool stop_signal_called = false; -void sig_int_handler(int){stop_signal_called = true;} - -std::string to_bit_string(boost::uint32_t val, const size_t num_bits) -{ - std::string out; - for (int i = num_bits - 1; i >= 0; i--) - { - std::string bit = ((val >> i) & 1) ? "1" : "0"; - out += " "; - out += bit; - } - return out; -} - -void output_reg_values( - const std::string bank, - const uhd::usrp::multi_usrp::sptr &usrp, - const size_t num_bits) -{ - std::cout << (boost::format("Bit ")); - for (int i = num_bits - 1; i >= 0; i--) - std::cout << (boost::format(" %s%d") % (i < 10 ? " " : "") % i); - std::cout << std::endl; - std::cout << "CTRL: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("CTRL"))), - num_bits) - << std::endl; - - std::cout << "DDR: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("DDR"))), - num_bits) - << std::endl; - - std::cout << "ATR_0X: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("ATR_0X"))), - num_bits) - << std::endl; - - std::cout << "ATR_RX: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("ATR_RX"))), - num_bits) - << std::endl; - - std::cout << "ATR_TX: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("ATR_TX"))), - num_bits) - << std::endl; - - std::cout << "ATR_XX: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("ATR_XX"))), - num_bits) - << std::endl; - - std::cout << "OUT: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("OUT"))), - num_bits) - << std::endl; - - std::cout << "READBACK: " << to_bit_string( - boost::uint32_t(usrp->get_gpio_attr(bank, std::string("READBACK"))), - num_bits) - << std::endl; -} - -int UHD_SAFE_MAIN(int argc, char *argv[]) -{ - uhd::set_thread_priority_safe(); - - //variables to be set by po - std::string args; - std::string cpu, otw; - double rx_rate, tx_rate, dwell; - std::string fpgpio; - size_t num_bits; - - //setup the program options - po::options_description desc("Allowed options"); - desc.add_options() - ("help", "help message") - ("args", po::value<std::string>(&args)->default_value(""), "multi uhd device address args") - ("repeat", "repeat loop until Ctrl-C is pressed") - ("cpu", po::value<std::string>(&cpu)->default_value(FPGPIO_DEFAULT_CPU_FORMAT), "cpu data format") - ("otw", po::value<std::string>(&otw)->default_value(FPGPIO_DEFAULT_OTW_FORMAT), "over the wire data format") - ("rx_rate", po::value<double>(&rx_rate)->default_value(FPGPIO_DEFAULT_RX_RATE), "rx sample rate") - ("tx_rate", po::value<double>(&tx_rate)->default_value(FPGPIO_DEFAULT_TX_RATE), "tx sample rate") - ("dwell", po::value<double>(&dwell)->default_value(FPGPIO_DEFAULT_DWELL_TIME), "dwell time in seconds for each test case") - ("gpio", po::value<std::string>(&fpgpio)->default_value(FPGPIO_DEFAULT_GPIO), "name of gpio bank") - ("bits", po::value<size_t>(&num_bits)->default_value(FPGPIO_DEFAULT_NUM_BITS), "number of bits in gpio bank") - ; - po::variables_map vm; - po::store(po::parse_command_line(argc, argv, desc), vm); - po::notify(vm); - - //print the help message - if (vm.count("help")){ - std::cout << boost::format("Front Panel GPIO %s") % desc << std::endl; - return ~0; - } - - //create a usrp device - std::cout << std::endl; - std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; - uhd::usrp::multi_usrp::sptr usrp = uhd::usrp::multi_usrp::make(args); - std::cout << boost::format("Using Device: %s") % usrp->get_pp_string() << std::endl; - - //print out initial unconfigured state of FP GPIO - std::cout << "Unconfigured GPIO values:" << std::endl; - output_reg_values(fpgpio, usrp, num_bits); - - //configure GPIO registers - boost::uint32_t ctrl = 0; // default all as manual - boost::uint32_t ddr = 0; // default all as input - boost::uint32_t atr_idle = 0; - boost::uint32_t atr_rx = 0; - boost::uint32_t atr_tx = 0; - boost::uint32_t atr_duplex = 0; - boost::uint32_t mask = 0x7ff; - - //set up FPGPIO outputs: - //FPGPIO[0] = ATR output 1 at idle - ctrl |= FPGPIO_BIT(0); - atr_idle |= FPGPIO_BIT(0); - ddr |= FPGPIO_BIT(0); - - //FPGPIO[1] = ATR output 1 during RX - ctrl |= FPGPIO_BIT(1); - ddr |= FPGPIO_BIT(1); - atr_rx |= FPGPIO_BIT(1); - - //FPGPIO[2] = ATR output 1 during TX - ctrl |= FPGPIO_BIT(2); - ddr |= FPGPIO_BIT(2); - atr_tx |= FPGPIO_BIT(2); - - //FPGPIO[3] = ATR output 1 during full duplex - ctrl |= FPGPIO_BIT(3); - ddr |= FPGPIO_BIT(3); - atr_duplex |= FPGPIO_BIT(3); - - //FPGPIO[4] = output - ddr |= FPGPIO_BIT(4); - - //set data direction register (DDR) - usrp->set_gpio_attr(fpgpio, std::string("DDR"), ddr, mask); - - //set ATR registers - usrp->set_gpio_attr(fpgpio, std::string("ATR_0X"), atr_idle, mask); - usrp->set_gpio_attr(fpgpio, std::string("ATR_RX"), atr_rx, mask); - usrp->set_gpio_attr(fpgpio, std::string("ATR_TX"), atr_tx, mask); - usrp->set_gpio_attr(fpgpio, std::string("ATR_XX"), atr_duplex, mask); - - //set control register - usrp->set_gpio_attr(fpgpio, std::string("CTRL"), ctrl, mask); - - //print out initial state of FP GPIO - std::cout << "\nConfigured GPIO values:" << std::endl; - output_reg_values(fpgpio, usrp, num_bits); - std::cout << std::endl; - - //set up streams - uhd::stream_args_t rx_args(cpu, otw); - uhd::stream_args_t tx_args(cpu, otw); - uhd::rx_streamer::sptr rx_stream = usrp->get_rx_stream(rx_args); - uhd::tx_streamer::sptr tx_stream = usrp->get_tx_stream(tx_args); - uhd::stream_cmd_t rx_cmd(uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS); - rx_cmd.stream_now = true; - usrp->set_rx_rate(rx_rate); - usrp->set_tx_rate(tx_rate); - - //set up buffers for tx and rx - const size_t max_samps_per_packet = rx_stream->get_max_num_samps(); - const size_t nsamps_per_buff = max_samps_per_packet; - std::vector<char> rx_buff(max_samps_per_packet*uhd::convert::get_bytes_per_item(cpu)); - std::vector<char> tx_buff(max_samps_per_packet*uhd::convert::get_bytes_per_item(cpu)); - std::vector<void *> rx_buffs, tx_buffs; - for (size_t ch = 0; ch < rx_stream->get_num_channels(); ch++) - rx_buffs.push_back(&rx_buff.front()); //same buffer for each channel - for (size_t ch = 0; ch < tx_stream->get_num_channels(); ch++) - tx_buffs.push_back(&tx_buff.front()); //same buffer for each channel - - uhd::rx_metadata_t rx_md; - uhd::tx_metadata_t tx_md; - tx_md.has_time_spec = false; - tx_md.start_of_burst = true; - uhd::time_spec_t stop_time; - double timeout = 0.01; - uhd::time_spec_t dwell_time(dwell); - int loop = 0; - boost::uint32_t rb, expected; - - //register singal handler - std::signal(SIGINT, &sig_int_handler); - - //Test the mask - only need to test once with no dwell time - std::cout << "\nTesting mask..." << std::flush; - //send a value of all 1's to the DDR with a mask for only bit 10 - usrp->set_gpio_attr(fpgpio, std::string("DDR"), ~0, FPGPIO_BIT(10)); - //bit 10 should now be 1, but all the other bits should be unchanged - rb = usrp->get_gpio_attr(fpgpio, std::string("DDR")) & mask; - expected = ddr | FPGPIO_BIT(10); - if (rb == expected) - std::cout << "pass" << std::endl; - else - std::cout << "fail" << std::endl; - std::cout << std::endl; - output_reg_values(fpgpio, usrp, num_bits); - usrp->set_gpio_attr(fpgpio, std::string("DDR"), ddr, mask); - - while (not stop_signal_called) - { - int failures = 0; - - if (vm.count("repeat")) - std::cout << "Press Ctrl + C to quit..." << std::endl; - - // test user controlled GPIO and ATR idle by setting bit 4 high for 1 second - std::cout << "\nTesting user controlled GPIO and ATR idle output..." << std::flush; - usrp->set_gpio_attr(fpgpio, "OUT", 1 << 4, 1 << 4); - stop_time = usrp->get_time_now() + dwell_time; - while (not stop_signal_called and usrp->get_time_now() < stop_time) - { - boost::this_thread::sleep(boost::posix_time::milliseconds(100)); - } - rb = usrp->get_gpio_attr(fpgpio, "READBACK"); - expected = FPGPIO_BIT(4) | FPGPIO_BIT(0); - if ((rb & expected) != expected) - { - ++failures; - std::cout << "fail" << std::endl; - if ((rb & FPGPIO_BIT(0)) == 0) - std::cout << "Bit 0 should be set, but is not" << std::endl; - if ((rb & FPGPIO_BIT(4)) == 0) - std::cout << "Bit 4 should be set, but is not" << std::endl; - } else { - std::cout << "pass" << std::endl; - } - std::cout << std::endl; - output_reg_values(fpgpio, usrp, num_bits); - usrp->set_gpio_attr(fpgpio, "OUT", 0, FPGPIO_BIT(4)); - if (stop_signal_called) - break; - - // test ATR RX by receiving for 1 second - std::cout << "\nTesting ATR RX output..." << std::flush; - rx_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS; - rx_stream->issue_stream_cmd(rx_cmd); - stop_time = usrp->get_time_now() + dwell_time; - while (not stop_signal_called and usrp->get_time_now() < stop_time) - { - try { - rx_stream->recv(rx_buffs, nsamps_per_buff, rx_md, timeout); - } catch(...){} - } - rb = usrp->get_gpio_attr(fpgpio, "READBACK"); - expected = FPGPIO_BIT(1); - if ((rb & expected) != expected) - { - ++failures; - std::cout << "fail" << std::endl; - std::cout << "Bit 1 should be set, but is not" << std::endl; - } else { - std::cout << "pass" << std::endl; - } - std::cout << std::endl; - output_reg_values(fpgpio, usrp, num_bits); - rx_stream->issue_stream_cmd(uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); - //clear out any data left in the rx stream - try { - rx_stream->recv(rx_buffs, nsamps_per_buff, rx_md, timeout); - } catch(...){} - if (stop_signal_called) - break; - - // test ATR TX by transmitting for 1 second - std::cout << "\nTesting ATR TX output..." << std::flush; - stop_time = usrp->get_time_now() + dwell_time; - tx_md.start_of_burst = true; - tx_md.end_of_burst = false; - while (not stop_signal_called and usrp->get_time_now() < stop_time) - { - try { - tx_stream->send(tx_buffs, nsamps_per_buff, tx_md, timeout); - tx_md.start_of_burst = false; - } catch(...){} - } - rb = usrp->get_gpio_attr(fpgpio, "READBACK"); - expected = FPGPIO_BIT(2); - if ((rb & expected) != expected) - { - ++failures; - std::cout << "fail" << std::endl; - std::cout << "Bit 2 should be set, but is not" << std::endl; - } else { - std::cout << "pass" << std::endl; - } - std::cout << std::endl; - output_reg_values(fpgpio, usrp, num_bits); - tx_md.end_of_burst = true; - try { - tx_stream->send(tx_buffs, nsamps_per_buff, tx_md, timeout); - } catch(...){} - if (stop_signal_called) - break; - - // test ATR RX by transmitting and receiving for 1 second - std::cout << "\nTesting ATR full duplex output..." << std::flush; - rx_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS; - rx_stream->issue_stream_cmd(rx_cmd); - tx_md.start_of_burst = true; - tx_md.end_of_burst = false; - stop_time = usrp->get_time_now() + dwell_time; - while (not stop_signal_called and usrp->get_time_now() < stop_time) - { - try { - tx_stream->send(rx_buffs, nsamps_per_buff, tx_md, timeout); - tx_md.start_of_burst = false; - rx_stream->recv(tx_buffs, nsamps_per_buff, rx_md, timeout); - } catch(...){} - } - rb = usrp->get_gpio_attr(fpgpio, "READBACK"); - expected = FPGPIO_BIT(3); - if ((rb & expected) != expected) - { - ++failures; - std::cout << "fail" << std::endl; - std::cout << "Bit 3 should be set, but is not" << std::endl; - } else { - std::cout << "pass" << std::endl; - } - std::cout << std::endl; - output_reg_values(fpgpio, usrp, num_bits); - rx_stream->issue_stream_cmd(uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); - tx_md.end_of_burst = true; - try { - tx_stream->send(tx_buffs, nsamps_per_buff, tx_md, timeout); - } catch(...){} - //clear out any data left in the rx stream - try { - rx_stream->recv(rx_buffs, nsamps_per_buff, rx_md, timeout); - } catch(...){} - - std::cout << std::endl; - if (failures) - std::cout << failures << " tests failed" << std::endl; - else - std::cout << "All tests passed!" << std::endl; - - if (!vm.count("repeat")) - break; - - std::cout << (boost::format("\nLoop %d completed") % ++loop) << std::endl; - } - - //finished - std::cout << std::endl << "Done!" << std::endl << std::endl; - - return EXIT_SUCCESS; -} diff --git a/host/examples/gpio.cpp b/host/examples/gpio.cpp new file mode 100644 index 000000000..b0d15f35a --- /dev/null +++ b/host/examples/gpio.cpp @@ -0,0 +1,462 @@ +// +// Copyright 2014-15 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +// Example for GPIO testing and bit banging. +// +// This example was originally designed to test the 11 bit wide front panel +// GPIO on the X300 series and has since been adapted to work with any GPIO +// bank on any USRP and provide optional bit banging. Please excuse the +// clutter. Also, there is no current way to detect the width of the +// specified GPIO bank, so the user must specify the width with the --bits +// flag if more than 11 bits. +// +// GPIO Testing: +// For testing, GPIO bits are set as follows: +// GPIO[0] = ATR output 1 at idle +// GPIO[1] = ATR output 1 during RX +// GPIO[2] = ATR output 1 during TX +// GPIO[3] = ATR output 1 during full duplex +// GPIO[4] = output +// GPIO[n:5] = input (all other pins) +// The testing cycles through idle, TX, RX, and full duplex, dwelling on each +// test case (default 2 seconds), and then comparing the readback register with +// the expected values of the outputs for verification. The values of all GPIO +// registers are displayed at the end of each test case. Outputs can be +// physically looped back to inputs to manually verify the inputs. +// +// GPIO Bit Banging: +// GPIO banks have the standard registers of DDR for data direction and OUT +// for output values. Users can bit bang the GPIO bits by using this example +// with the --bitbang flag and specifying the --ddr and --out flags to set the +// values of the corresponding registers. The READBACK register is +// continuously read for the duration of the dwell time (default 2 seconds) so +// users can monitor changes on the inputs. +// +// Automatic Transmit/Receive (ATR): +// In addition to the standard DDR and OUT registers, the GPIO banks also +// have ATR (Automatic Transmit/Receive) control registers that allow the +// GPIO pins to be automatically set to specific values when the USRP is +// idle, transmitting, receiving, or operating in full duplex mode. The +// description of these registers is below: +// CTRL - Control (0=manual, 1=ATR) +// ATR_0X - Values to be set when idle +// ATR_RX - Output values to be set when receiving +// ATR_TX - Output values to be set when transmitting +// ATR_XX - Output values to be set when operating in full duplex +// This code below contains examples of setting all these registers. On +// devices with multiple radios, the ATR for the front panel GPIO is driven +// by the state of the first radio (0 or A). +// +// The UHD API +// The multi_usrp::set_gpio_attr() method is the UHD API for configuring and +// controlling the GPIO banks. The parameters to the method are: +// bank - the name of the GPIO bank (typically "FP0" for front panel GPIO, +// "TX<n>" for TX daughter card GPIO, or +// "RX<n>" for RX daughter card GPIO) +// attr - attribute (register) to change ("DDR", "OUT", "CTRL", "ATR_0X", +// "ATR_RX", "ATR_TX", "ATR_XX") +// value - the value to be set +// mask - a mask indicating which bits in the specified attribute register are +// to be changed (default is all bits). + +#include <uhd/utils/thread_priority.hpp> +#include <uhd/utils/safe_main.hpp> +#include <uhd/usrp/multi_usrp.hpp> +#include <uhd/convert.hpp> +#include <boost/assign.hpp> +#include <boost/program_options.hpp> +#include <boost/format.hpp> +#include <boost/cstdint.hpp> +#include <boost/thread.hpp> +#include <csignal> +#include <iostream> +#include <stdlib.h> + +static const std::string GPIO_DEFAULT_CPU_FORMAT = "fc32"; +static const std::string GPIO_DEFAULT_OTW_FORMAT = "sc16"; +static const double GPIO_DEFAULT_RX_RATE = 500e3; +static const double GPIO_DEFAULT_TX_RATE = 500e3; +static const double GPIO_DEFAULT_DWELL_TIME = 2.0; +static const std::string GPIO_DEFAULT_GPIO = "FP0"; +static const size_t GPIO_DEFAULT_NUM_BITS = 11; +static const std::string GPIO_DEFAULT_CTRL = "0x0"; // all as user controlled +static const std::string GPIO_DEFAULT_DDR = "0x0"; // all as inputs +static const std::string GPIO_DEFAULT_OUT = "0x0"; + +static UHD_INLINE boost::uint32_t GPIO_BIT(const size_t x) +{ + return (1 << x); +} + +namespace po = boost::program_options; + +static bool stop_signal_called = false; +void sig_int_handler(int){stop_signal_called = true;} + +std::string to_bit_string(boost::uint32_t val, const size_t num_bits) +{ + std::string out; + for (int i = num_bits - 1; i >= 0; i--) + { + std::string bit = ((val >> i) & 1) ? "1" : "0"; + out += " "; + out += bit; + } + return out; +} + +void output_reg_values( + const std::string bank, + const uhd::usrp::multi_usrp::sptr &usrp, + const size_t num_bits) +{ + std::vector<std::string> attrs = boost::assign::list_of("CTRL")("DDR")("ATR_0X")("ATR_RX")("ATR_TX")("ATR_XX")("OUT")("READBACK"); + std::cout << (boost::format("%10s ") % "Bit"); + for (int i = num_bits - 1; i >= 0; i--) + std::cout << (boost::format(" %2d") % i); + std::cout << std::endl; + BOOST_FOREACH(std::string &attr, attrs) + { + std::cout << (boost::format("%10s:%s") + % attr % to_bit_string(boost::uint32_t(usrp->get_gpio_attr(bank, attr)), num_bits)) + << std::endl; + } +} + +int UHD_SAFE_MAIN(int argc, char *argv[]) +{ + uhd::set_thread_priority_safe(); + + //variables to be set by po + std::string args; + std::string cpu, otw; + double rx_rate, tx_rate, dwell; + std::string gpio; + size_t num_bits; + std::string ctrl_str; + std::string ddr_str; + std::string out_str; + + //setup the program options + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("args", po::value<std::string>(&args)->default_value(""), "multi uhd device address args") + ("repeat", "repeat loop until Ctrl-C is pressed") + ("cpu", po::value<std::string>(&cpu)->default_value(GPIO_DEFAULT_CPU_FORMAT), "cpu data format") + ("otw", po::value<std::string>(&otw)->default_value(GPIO_DEFAULT_OTW_FORMAT), "over the wire data format") + ("rx_rate", po::value<double>(&rx_rate)->default_value(GPIO_DEFAULT_RX_RATE), "rx sample rate") + ("tx_rate", po::value<double>(&tx_rate)->default_value(GPIO_DEFAULT_TX_RATE), "tx sample rate") + ("dwell", po::value<double>(&dwell)->default_value(GPIO_DEFAULT_DWELL_TIME), "dwell time in seconds for each test case") + ("bank", po::value<std::string>(&gpio)->default_value(GPIO_DEFAULT_GPIO), "name of gpio bank") + ("bits", po::value<size_t>(&num_bits)->default_value(GPIO_DEFAULT_NUM_BITS), "number of bits in gpio bank") + ("bitbang", "single test case where user sets values for CTRL, DDR, and OUT registers") + ("ddr", po::value<std::string>(&ddr_str)->default_value(GPIO_DEFAULT_DDR), "GPIO DDR reg value") + ("out", po::value<std::string>(&out_str)->default_value(GPIO_DEFAULT_OUT), "GPIO OUT reg value") + ; + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help")){ + std::cout << boost::format("gpio %s") % desc << std::endl; + return ~0; + } + + //create a usrp device + std::cout << std::endl; + std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; + uhd::usrp::multi_usrp::sptr usrp = uhd::usrp::multi_usrp::make(args); + std::cout << boost::format("Using Device: %s") % usrp->get_pp_string() << std::endl; + + //print out initial unconfigured state of FP GPIO + std::cout << "Initial GPIO values:" << std::endl; + output_reg_values(gpio, usrp, num_bits); + + //configure GPIO registers + boost::uint32_t ddr = strtoul(ddr_str.c_str(), NULL, 0); + boost::uint32_t out = strtoul(out_str.c_str(), NULL, 0); + boost::uint32_t ctrl = 0; + boost::uint32_t atr_idle = 0; + boost::uint32_t atr_rx = 0; + boost::uint32_t atr_tx = 0; + boost::uint32_t atr_duplex = 0; + boost::uint32_t mask = (1 << num_bits) - 1; + + if (!vm.count("bitbang")) + { + //set up GPIO outputs: + //GPIO[0] = ATR output 1 at idle + ctrl |= GPIO_BIT(0); + atr_idle |= GPIO_BIT(0); + ddr |= GPIO_BIT(0); + + //GPIO[1] = ATR output 1 during RX + ctrl |= GPIO_BIT(1); + ddr |= GPIO_BIT(1); + atr_rx |= GPIO_BIT(1); + + //GPIO[2] = ATR output 1 during TX + ctrl |= GPIO_BIT(2); + ddr |= GPIO_BIT(2); + atr_tx |= GPIO_BIT(2); + + //GPIO[3] = ATR output 1 during full duplex + ctrl |= GPIO_BIT(3); + ddr |= GPIO_BIT(3); + atr_duplex |= GPIO_BIT(3); + + //GPIO[4] = output + ddr |= GPIO_BIT(4); + } + + //set data direction register (DDR) + usrp->set_gpio_attr(gpio, "DDR", ddr, mask); + + //set output values (OUT) + usrp->set_gpio_attr(gpio, "OUT", out, mask); + + //set ATR registers + usrp->set_gpio_attr(gpio, "ATR_0X", atr_idle, mask); + usrp->set_gpio_attr(gpio, "ATR_RX", atr_rx, mask); + usrp->set_gpio_attr(gpio, "ATR_TX", atr_tx, mask); + usrp->set_gpio_attr(gpio, "ATR_XX", atr_duplex, mask); + + //set control register + usrp->set_gpio_attr(gpio, "CTRL", ctrl, mask); + + //print out initial state of FP GPIO + std::cout << "\nConfigured GPIO values:" << std::endl; + output_reg_values(gpio, usrp, num_bits); + std::cout << std::endl; + + //set up streams + uhd::stream_args_t rx_args(cpu, otw); + uhd::stream_args_t tx_args(cpu, otw); + uhd::rx_streamer::sptr rx_stream = usrp->get_rx_stream(rx_args); + uhd::tx_streamer::sptr tx_stream = usrp->get_tx_stream(tx_args); + uhd::stream_cmd_t rx_cmd(uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + rx_cmd.stream_now = true; + usrp->set_rx_rate(rx_rate); + usrp->set_tx_rate(tx_rate); + + //set up buffers for tx and rx + const size_t max_samps_per_packet = rx_stream->get_max_num_samps(); + const size_t nsamps_per_buff = max_samps_per_packet; + std::vector<char> rx_buff(max_samps_per_packet*uhd::convert::get_bytes_per_item(cpu)); + std::vector<char> tx_buff(max_samps_per_packet*uhd::convert::get_bytes_per_item(cpu)); + std::vector<void *> rx_buffs, tx_buffs; + for (size_t ch = 0; ch < rx_stream->get_num_channels(); ch++) + rx_buffs.push_back(&rx_buff.front()); //same buffer for each channel + for (size_t ch = 0; ch < tx_stream->get_num_channels(); ch++) + tx_buffs.push_back(&tx_buff.front()); //same buffer for each channel + + uhd::rx_metadata_t rx_md; + uhd::tx_metadata_t tx_md; + tx_md.has_time_spec = false; + tx_md.start_of_burst = true; + uhd::time_spec_t stop_time; + double timeout = 0.01; + uhd::time_spec_t dwell_time(dwell); + int loop = 0; + boost::uint32_t rb, expected; + + //register signal handler + std::signal(SIGINT, &sig_int_handler); + + if (!vm.count("bitbang")) + { + // Test the mask parameter of the multi_usrp::set_gpio_attr API + // We only need to test once with no dwell time + std::cout << "\nTesting mask..." << std::flush; + //send a value of all 1's to the DDR with a mask for only upper most bit + usrp->set_gpio_attr(gpio, "DDR", ~0, GPIO_BIT(num_bits - 1)); + //upper most bit should now be 1, but all the other bits should be unchanged + rb = usrp->get_gpio_attr(gpio, "DDR") & mask; + expected = ddr | GPIO_BIT(num_bits - 1); + if (rb == expected) + std::cout << "pass:" << std::endl; + else + std::cout << "fail:" << std::endl; + output_reg_values(gpio, usrp, num_bits); + //restore DDR value + usrp->set_gpio_attr(gpio, "DDR", ddr, mask); + } + + while (not stop_signal_called) + { + int failures = 0; + + if (vm.count("repeat")) + std::cout << "Press Ctrl + C to quit..." << std::endl; + + if (vm.count("bitbang")) + { + // dwell and continuously read back GPIO values + stop_time = usrp->get_time_now() + dwell_time; + while (not stop_signal_called and usrp->get_time_now() < stop_time) + { + rb = usrp->get_gpio_attr(gpio, "READBACK"); + std::cout << "\rREADBACK: " << to_bit_string(rb, num_bits); + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + } + std::cout << std::endl; + } + else + { + // test user controlled GPIO and ATR idle by setting bit 4 high for 1 second + std::cout << "\nTesting user controlled GPIO and ATR idle output..." << std::flush; + usrp->set_gpio_attr(gpio, "OUT", 1 << 4, 1 << 4); + stop_time = usrp->get_time_now() + dwell_time; + while (not stop_signal_called and usrp->get_time_now() < stop_time) + { + boost::this_thread::sleep(boost::posix_time::milliseconds(100)); + } + rb = usrp->get_gpio_attr(gpio, "READBACK"); + expected = GPIO_BIT(4) | GPIO_BIT(0); + if ((rb & expected) != expected) + { + ++failures; + std::cout << "fail:" << std::endl; + if ((rb & GPIO_BIT(0)) == 0) + std::cout << "Bit 0 should be set, but is not" << std::endl; + if ((rb & GPIO_BIT(4)) == 0) + std::cout << "Bit 4 should be set, but is not" << std::endl; + } else { + std::cout << "pass:" << std::endl; + } + output_reg_values(gpio, usrp, num_bits); + usrp->set_gpio_attr(gpio, "OUT", 0, GPIO_BIT(4)); + if (stop_signal_called) + break; + + // test ATR RX by receiving for 1 second + std::cout << "\nTesting ATR RX output..." << std::flush; + rx_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS; + rx_stream->issue_stream_cmd(rx_cmd); + stop_time = usrp->get_time_now() + dwell_time; + while (not stop_signal_called and usrp->get_time_now() < stop_time) + { + try { + rx_stream->recv(rx_buffs, nsamps_per_buff, rx_md, timeout); + } catch(...){} + } + rb = usrp->get_gpio_attr(gpio, "READBACK"); + expected = GPIO_BIT(1); + if ((rb & expected) != expected) + { + ++failures; + std::cout << "fail:" << std::endl; + std::cout << "Bit 1 should be set, but is not" << std::endl; + } else { + std::cout << "pass:" << std::endl; + } + output_reg_values(gpio, usrp, num_bits); + rx_stream->issue_stream_cmd(uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); + //clear out any data left in the rx stream + try { + rx_stream->recv(rx_buffs, nsamps_per_buff, rx_md, timeout); + } catch(...){} + if (stop_signal_called) + break; + + // test ATR TX by transmitting for 1 second + std::cout << "\nTesting ATR TX output..." << std::flush; + stop_time = usrp->get_time_now() + dwell_time; + tx_md.start_of_burst = true; + tx_md.end_of_burst = false; + while (not stop_signal_called and usrp->get_time_now() < stop_time) + { + try { + tx_stream->send(tx_buffs, nsamps_per_buff, tx_md, timeout); + tx_md.start_of_burst = false; + } catch(...){} + } + rb = usrp->get_gpio_attr(gpio, "READBACK"); + expected = GPIO_BIT(2); + if ((rb & expected) != expected) + { + ++failures; + std::cout << "fail:" << std::endl; + std::cout << "Bit 2 should be set, but is not" << std::endl; + } else { + std::cout << "pass:" << std::endl; + } + output_reg_values(gpio, usrp, num_bits); + tx_md.end_of_burst = true; + try { + tx_stream->send(tx_buffs, nsamps_per_buff, tx_md, timeout); + } catch(...){} + if (stop_signal_called) + break; + + // test ATR RX by transmitting and receiving for 1 second + std::cout << "\nTesting ATR full duplex output..." << std::flush; + rx_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS; + rx_stream->issue_stream_cmd(rx_cmd); + tx_md.start_of_burst = true; + tx_md.end_of_burst = false; + stop_time = usrp->get_time_now() + dwell_time; + while (not stop_signal_called and usrp->get_time_now() < stop_time) + { + try { + tx_stream->send(rx_buffs, nsamps_per_buff, tx_md, timeout); + tx_md.start_of_burst = false; + rx_stream->recv(tx_buffs, nsamps_per_buff, rx_md, timeout); + } catch(...){} + } + rb = usrp->get_gpio_attr(gpio, "READBACK"); + expected = GPIO_BIT(3); + if ((rb & expected) != expected) + { + ++failures; + std::cout << "fail:" << std::endl; + std::cout << "Bit 3 should be set, but is not" << std::endl; + } else { + std::cout << "pass:" << std::endl; + } + output_reg_values(gpio, usrp, num_bits); + rx_stream->issue_stream_cmd(uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); + tx_md.end_of_burst = true; + try { + tx_stream->send(tx_buffs, nsamps_per_buff, tx_md, timeout); + } catch(...){} + //clear out any data left in the rx stream + try { + rx_stream->recv(rx_buffs, nsamps_per_buff, rx_md, timeout); + } catch(...){} + + std::cout << std::endl; + if (failures) + std::cout << failures << " tests failed" << std::endl; + else + std::cout << "All tests passed!" << std::endl; + } + + if (!vm.count("repeat")) + break; + + if (not stop_signal_called) + std::cout << (boost::format("\nLoop %d completed") % ++loop) << std::endl; + } + + //finished + std::cout << std::endl << "Done!" << std::endl << std::endl; + + return EXIT_SUCCESS; +} diff --git a/host/examples/rx_samples_to_file.cpp b/host/examples/rx_samples_to_file.cpp index 80b72de9c..934dce586 100644 --- a/host/examples/rx_samples_to_file.cpp +++ b/host/examples/rx_samples_to_file.cpp @@ -56,7 +56,7 @@ template<typename samp_type> void recv_to_file( std::vector<samp_type> buff(samps_per_buff); std::ofstream outfile; if (not null) - outfile.open(file.c_str(), std::ofstream::binary); + outfile.open(file.c_str(), std::ofstream::binary); bool overflow_message = true; //setup streaming @@ -78,8 +78,8 @@ template<typename samp_type> void recv_to_file( typedef std::map<size_t,size_t> SizeMap; SizeMap mapSizes; - while(not stop_signal_called and (num_requested_samples != num_total_samps or num_requested_samples == 0)){ - boost::system_time now = boost::get_system_time(); + while(not stop_signal_called and (num_requested_samples != num_total_samps or num_requested_samples == 0)) { + boost::system_time now = boost::get_system_time(); size_t num_rx_samps = rx_stream->recv(&buff.front(), buff.size(), md, 3.0, enable_size_map); @@ -88,7 +88,7 @@ template<typename samp_type> void recv_to_file( break; } if (md.error_code == uhd::rx_metadata_t::ERROR_CODE_OVERFLOW){ - if (overflow_message){ + if (overflow_message) { overflow_message = false; std::cerr << boost::format( "Got an overflow indication. Please consider the following:\n" @@ -110,99 +110,99 @@ template<typename samp_type> void recv_to_file( throw std::runtime_error(error); } - if (enable_size_map){ - SizeMap::iterator it = mapSizes.find(num_rx_samps); - if (it == mapSizes.end()) - mapSizes[num_rx_samps] = 0; - mapSizes[num_rx_samps] += 1; - } + if (enable_size_map) { + SizeMap::iterator it = mapSizes.find(num_rx_samps); + if (it == mapSizes.end()) + mapSizes[num_rx_samps] = 0; + mapSizes[num_rx_samps] += 1; + } num_total_samps += num_rx_samps; - if (outfile.is_open()) - outfile.write((const char*)&buff.front(), num_rx_samps*sizeof(samp_type)); - - if (bw_summary){ - last_update_samps += num_rx_samps; - boost::posix_time::time_duration update_diff = now - last_update; - if (update_diff.ticks() > boost::posix_time::time_duration::ticks_per_second()) { - double t = (double)update_diff.ticks() / (double)boost::posix_time::time_duration::ticks_per_second(); - double r = (double)last_update_samps / t; - std::cout << boost::format("\t%f Msps") % (r/1e6) << std::endl; - last_update_samps = 0; - last_update = now; - } - } + if (outfile.is_open()) + outfile.write((const char*)&buff.front(), num_rx_samps*sizeof(samp_type)); + + if (bw_summary) { + last_update_samps += num_rx_samps; + boost::posix_time::time_duration update_diff = now - last_update; + if (update_diff.ticks() > boost::posix_time::time_duration::ticks_per_second()) { + double t = (double)update_diff.ticks() / (double)boost::posix_time::time_duration::ticks_per_second(); + double r = (double)last_update_samps / t; + std::cout << boost::format("\t%f Msps") % (r/1e6) << std::endl; + last_update_samps = 0; + last_update = now; + } + } ticks_diff = now - start; - if (ticks_requested > 0){ - if ((unsigned long long)ticks_diff.ticks() > ticks_requested) - break; - } + if (ticks_requested > 0){ + if ((unsigned long long)ticks_diff.ticks() > ticks_requested) + break; + } } stream_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS; rx_stream->issue_stream_cmd(stream_cmd); if (outfile.is_open()) - outfile.close(); - - if (stats){ - std::cout << std::endl; - - double t = (double)ticks_diff.ticks() / (double)boost::posix_time::time_duration::ticks_per_second(); - std::cout << boost::format("Received %d samples in %f seconds") % num_total_samps % t << std::endl; - double r = (double)num_total_samps / t; - std::cout << boost::format("%f Msps") % (r/1e6) << std::endl; - - if (enable_size_map) { - std::cout << std::endl; - std::cout << "Packet size map (bytes: count)" << std::endl; - for (SizeMap::iterator it = mapSizes.begin(); it != mapSizes.end(); it++) - std::cout << it->first << ":\t" << it->second << std::endl; - } - } + outfile.close(); + + if (stats) { + std::cout << std::endl; + + double t = (double)ticks_diff.ticks() / (double)boost::posix_time::time_duration::ticks_per_second(); + std::cout << boost::format("Received %d samples in %f seconds") % num_total_samps % t << std::endl; + double r = (double)num_total_samps / t; + std::cout << boost::format("%f Msps") % (r/1e6) << std::endl; + + if (enable_size_map) { + std::cout << std::endl; + std::cout << "Packet size map (bytes: count)" << std::endl; + for (SizeMap::iterator it = mapSizes.begin(); it != mapSizes.end(); it++) + std::cout << it->first << ":\t" << it->second << std::endl; + } + } } typedef boost::function<uhd::sensor_value_t (const std::string&)> get_sensor_fn_t; bool check_locked_sensor(std::vector<std::string> sensor_names, const char* sensor_name, get_sensor_fn_t get_sensor_fn, double setup_time){ - if (std::find(sensor_names.begin(), sensor_names.end(), sensor_name) == sensor_names.end()) - return false; - - boost::system_time start = boost::get_system_time(); - boost::system_time first_lock_time; - - std::cout << boost::format("Waiting for \"%s\": ") % sensor_name; - std::cout.flush(); - - while (true){ - if ((not first_lock_time.is_not_a_date_time()) and - (boost::get_system_time() > (first_lock_time + boost::posix_time::seconds(setup_time)))) - { - std::cout << " locked." << std::endl; - break; - } - if (get_sensor_fn(sensor_name).to_bool()){ - if (first_lock_time.is_not_a_date_time()) - first_lock_time = boost::get_system_time(); - std::cout << "+"; - std::cout.flush(); - } - else{ - first_lock_time = boost::system_time(); //reset to 'not a date time' - - if (boost::get_system_time() > (start + boost::posix_time::seconds(setup_time))){ - std::cout << std::endl; - throw std::runtime_error(str(boost::format("timed out waiting for consecutive locks on sensor \"%s\"") % sensor_name)); - } - std::cout << "_"; - std::cout.flush(); - } - boost::this_thread::sleep(boost::posix_time::milliseconds(100)); - } - std::cout << std::endl; - return true; + if (std::find(sensor_names.begin(), sensor_names.end(), sensor_name) == sensor_names.end()) + return false; + + boost::system_time start = boost::get_system_time(); + boost::system_time first_lock_time; + + std::cout << boost::format("Waiting for \"%s\": ") % sensor_name; + std::cout.flush(); + + while (true) { + if ((not first_lock_time.is_not_a_date_time()) and + (boost::get_system_time() > (first_lock_time + boost::posix_time::seconds(setup_time)))) + { + std::cout << " locked." << std::endl; + break; + } + if (get_sensor_fn(sensor_name).to_bool()){ + if (first_lock_time.is_not_a_date_time()) + first_lock_time = boost::get_system_time(); + std::cout << "+"; + std::cout.flush(); + } + else { + first_lock_time = boost::system_time(); //reset to 'not a date time' + + if (boost::get_system_time() > (start + boost::posix_time::seconds(setup_time))){ + std::cout << std::endl; + throw std::runtime_error(str(boost::format("timed out waiting for consecutive locks on sensor \"%s\"") % sensor_name)); + } + std::cout << "_"; + std::cout.flush(); + } + boost::this_thread::sleep(boost::posix_time::milliseconds(100)); + } + std::cout << std::endl; + return true; } int UHD_SAFE_MAIN(int argc, char *argv[]){ @@ -246,8 +246,12 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ po::notify(vm); //print the help message - if (vm.count("help")){ + if (vm.count("help")) { std::cout << boost::format("UHD RX samples to file %s") % desc << std::endl; + std::cout + << std::endl + << "This application streams data from a single channel of a USRP device to a file.\n" + << std::endl; return ~0; } @@ -258,7 +262,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ bool continue_on_bad_packet = vm.count("continue") > 0; if (enable_size_map) - std::cout << "Packet size tracking enabled - will only recv one packet at a time!" << std::endl; + std::cout << "Packet size tracking enabled - will only recv one packet at a time!" << std::endl; //create a usrp device std::cout << std::endl; @@ -283,23 +287,23 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << boost::format("Actual RX Rate: %f Msps...") % (usrp->get_rx_rate()/1e6) << std::endl << std::endl; //set the center frequency - if (vm.count("freq")){ //with default of 0.0 this will always be true - std::cout << boost::format("Setting RX Freq: %f MHz...") % (freq/1e6) << std::endl; + if (vm.count("freq")) { //with default of 0.0 this will always be true + std::cout << boost::format("Setting RX Freq: %f MHz...") % (freq/1e6) << std::endl; uhd::tune_request_t tune_request(freq); if(vm.count("int-n")) tune_request.args = uhd::device_addr_t("mode_n=integer"); - usrp->set_rx_freq(tune_request); - std::cout << boost::format("Actual RX Freq: %f MHz...") % (usrp->get_rx_freq()/1e6) << std::endl << std::endl; - } + usrp->set_rx_freq(tune_request); + std::cout << boost::format("Actual RX Freq: %f MHz...") % (usrp->get_rx_freq()/1e6) << std::endl << std::endl; + } //set the rf gain - if (vm.count("gain")){ + if (vm.count("gain")) { std::cout << boost::format("Setting RX Gain: %f dB...") % gain << std::endl; usrp->set_rx_gain(gain); std::cout << boost::format("Actual RX Gain: %f dB...") % usrp->get_rx_gain() << std::endl << std::endl; } - //set the analog frontend filter bandwidth - if (vm.count("bw")){ + //set the IF filter bandwidth + if (vm.count("bw")) { std::cout << boost::format("Setting RX Bandwidth: %f MHz...") % (bw/1e6) << std::endl; usrp->set_rx_bandwidth(bw); std::cout << boost::format("Actual RX Bandwidth: %f MHz...") % (usrp->get_rx_bandwidth()/1e6) << std::endl << std::endl; @@ -312,12 +316,12 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //check Ref and LO Lock detect if (not vm.count("skip-lo")){ - check_locked_sensor(usrp->get_rx_sensor_names(0), "lo_locked", boost::bind(&uhd::usrp::multi_usrp::get_rx_sensor, usrp, _1, 0), setup_time); - if (ref == "mimo") - check_locked_sensor(usrp->get_mboard_sensor_names(0), "mimo_locked", boost::bind(&uhd::usrp::multi_usrp::get_mboard_sensor, usrp, _1, 0), setup_time); - if (ref == "external") - check_locked_sensor(usrp->get_mboard_sensor_names(0), "ref_locked", boost::bind(&uhd::usrp::multi_usrp::get_mboard_sensor, usrp, _1, 0), setup_time); - } + check_locked_sensor(usrp->get_rx_sensor_names(0), "lo_locked", boost::bind(&uhd::usrp::multi_usrp::get_rx_sensor, usrp, _1, 0), setup_time); + if (ref == "mimo") + check_locked_sensor(usrp->get_mboard_sensor_names(0), "mimo_locked", boost::bind(&uhd::usrp::multi_usrp::get_mboard_sensor, usrp, _1, 0), setup_time); + if (ref == "external") + check_locked_sensor(usrp->get_mboard_sensor_names(0), "ref_locked", boost::bind(&uhd::usrp::multi_usrp::get_mboard_sensor, usrp, _1, 0), setup_time); + } if (total_num_samps == 0){ std::signal(SIGINT, &sig_int_handler); @@ -325,7 +329,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ } #define recv_to_file_args(format) \ - (usrp, format, wirefmt, file, spb, total_num_samps, total_time, bw_summary, stats, null, enable_size_map, continue_on_bad_packet) + (usrp, format, wirefmt, file, spb, total_num_samps, total_time, bw_summary, stats, null, enable_size_map, continue_on_bad_packet) //recv to file if (type == "double") recv_to_file<std::complex<double> >recv_to_file_args("fc64"); else if (type == "float") recv_to_file<std::complex<float> >recv_to_file_args("fc32"); diff --git a/host/examples/rx_timed_samples.cpp b/host/examples/rx_timed_samples.cpp index 30535907f..20abd92fe 100644 --- a/host/examples/rx_timed_samples.cpp +++ b/host/examples/rx_timed_samples.cpp @@ -48,7 +48,6 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("rate", po::value<double>(&rate)->default_value(100e6/16), "rate of incoming samples") ("dilv", "specify to disable inner-loop verbose") ("channels", po::value<std::string>(&channel_list)->default_value("0"), "which channel(s) to use (specify \"0\", \"1\", \"0,1\", etc)") - ; po::variables_map vm; po::store(po::parse_command_line(argc, argv, desc), vm); diff --git a/host/examples/test_pps_input.cpp b/host/examples/test_pps_input.cpp index 889c98a45..3e6c4ba9d 100644 --- a/host/examples/test_pps_input.cpp +++ b/host/examples/test_pps_input.cpp @@ -47,6 +47,11 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //print the help message if (vm.count("help")){ std::cout << boost::format("UHD Test PPS Input %s") % desc << std::endl; + std::cout + << std::endl + << "Tests if the PPS input signal is working. Will throw an error if not." + << std::endl + << std::endl; return ~0; } diff --git a/host/examples/transport_hammer.cpp b/host/examples/transport_hammer.cpp deleted file mode 100644 index 32e344e3e..000000000 --- a/host/examples/transport_hammer.cpp +++ /dev/null @@ -1,280 +0,0 @@ -// -// Copyright 2012 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -#include <uhd/utils/thread_priority.hpp> -#include <uhd/convert.hpp> -#include <uhd/utils/safe_main.hpp> -#include <uhd/usrp/multi_usrp.hpp> -#include <boost/program_options.hpp> -#include <boost/format.hpp> -#include <boost/thread/thread.hpp> -#include <boost/math/special_functions/round.hpp> -#include <iostream> -#include <complex> - -namespace po = boost::program_options; - -/*********************************************************************** - * Test result variables - **********************************************************************/ -unsigned long long num_overflows = 0; -unsigned long long num_underflows = 0; -unsigned long long num_rx_samps = 0; -unsigned long long num_tx_samps = 0; -unsigned long long num_dropped_samps = 0; -unsigned long long num_seq_errors = 0; - -/*********************************************************************** - * RX Hammer - **********************************************************************/ -void rx_hammer(uhd::usrp::multi_usrp::sptr usrp, const std::string &rx_cpu, uhd::rx_streamer::sptr rx_stream){ - uhd::set_thread_priority_safe(); - - //print pre-test summary - std::cout << boost::format( - "Testing receive rate %f Msps" - ) % (usrp->get_rx_rate()/1e6) << std::endl; - - //setup variables and allocate buffer - uhd::rx_metadata_t md; - const size_t max_samps_per_packet = rx_stream->get_max_num_samps(); - std::vector<char> buff(max_samps_per_packet*uhd::convert::get_bytes_per_item(rx_cpu)); - std::vector<void *> buffs; - for (size_t ch = 0; ch < rx_stream->get_num_channels(); ch++) - buffs.push_back(&buff.front()); //same buffer for each channel - bool had_an_overflow = false; - uhd::time_spec_t last_time; - const double rate = usrp->get_rx_rate(); - double timeout = 1; - - uhd::stream_cmd_t cmd(uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE); - cmd.time_spec = usrp->get_time_now() + uhd::time_spec_t(0.05); - cmd.stream_now = (buffs.size() == 1); - srand( time(NULL) ); - - while (not boost::this_thread::interruption_requested()){ - cmd.num_samps = rand() % 100000; - rx_stream->issue_stream_cmd(cmd); - num_rx_samps += rx_stream->recv(buffs, max_samps_per_packet, md, timeout, true); - - //handle the error codes - switch(md.error_code){ - case uhd::rx_metadata_t::ERROR_CODE_NONE: - if (had_an_overflow){ - had_an_overflow = false; - num_dropped_samps += boost::math::iround((md.time_spec - last_time).get_real_secs()*rate); - } - break; - - case uhd::rx_metadata_t::ERROR_CODE_OVERFLOW: - had_an_overflow = true; - last_time = md.time_spec; - if (!md.out_of_sequence) - num_overflows++; - break; - - default: - std::cerr << "Receiver error: " << md.strerror() << std::endl; - std::cerr << "Unexpected error on recv, continuing..." << std::endl; - break; - } - } -} - -/*********************************************************************** - * TX Hammer - **********************************************************************/ -void tx_hammer(uhd::usrp::multi_usrp::sptr usrp, const std::string &tx_cpu, uhd::tx_streamer::sptr tx_stream){ - uhd::set_thread_priority_safe(); - - uhd::tx_metadata_t md; - const size_t max_samps_per_packet = tx_stream->get_max_num_samps(); - std::vector<char> buff(max_samps_per_packet*uhd::convert::get_bytes_per_item(tx_cpu)); - std::vector<void *> buffs; - for (size_t ch = 0; ch < tx_stream->get_num_channels(); ch++) - buffs.push_back(&buff.front()); //same buffer for each channel - - //print pre-test summary - std::cout << boost::format( - "Testing transmit rate %f Msps" - ) % (usrp->get_tx_rate()/1e6) << std::endl; - - //setup variables and allocate buffer - std::srand( time(NULL) ); - while(not boost::this_thread::interruption_requested()){ - size_t total_num_samps = rand() % 100000; - size_t num_acc_samps = 0; - float timeout = 1; - - usrp->set_time_now(uhd::time_spec_t(0.0)); - while(num_acc_samps < total_num_samps){ - - //send a single packet - num_tx_samps += tx_stream->send(buffs, max_samps_per_packet, md, timeout); - - num_acc_samps += std::min(total_num_samps-num_acc_samps, tx_stream->get_max_num_samps()); - } - //send a mini EOB packet - md.end_of_burst = true; - tx_stream->send("", 0, md); - } -} - -void tx_hammer_async_helper(uhd::tx_streamer::sptr tx_stream){ - //setup variables and allocate buffer - uhd::async_metadata_t async_md; - - while (not boost::this_thread::interruption_requested()){ - - if (not tx_stream->recv_async_msg(async_md)) continue; - - //handle the error codes - switch(async_md.event_code){ - case uhd::async_metadata_t::EVENT_CODE_BURST_ACK: - return; - - case uhd::async_metadata_t::EVENT_CODE_UNDERFLOW: - case uhd::async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET: - num_underflows++; - break; - - case uhd::async_metadata_t::EVENT_CODE_SEQ_ERROR: - case uhd::async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST: - num_seq_errors++; - break; - - default: - std::cerr << "Event code: " << async_md.event_code << std::endl; - std::cerr << "Unexpected event on async recv, continuing..." << std::endl; - break; - } - } -} - -/*********************************************************************** - * Main code + dispatcher - **********************************************************************/ -int UHD_SAFE_MAIN(int argc, char *argv[]){ - uhd::set_thread_priority_safe(); - - //variables to be set by po - std::string args; - double duration; - double rx_rate, tx_rate; - std::string rx_otw, tx_otw; - std::string rx_cpu, tx_cpu; - std::string mode; - - //setup the program options - po::options_description desc("Allowed options"); - desc.add_options() - ("help", "help message") - ("args", po::value<std::string>(&args)->default_value(""), "single uhd device address args") - ("duration", po::value<double>(&duration)->default_value(10.0), "if random, specify duration for the test in seconds") - ("rx_rate", po::value<double>(&rx_rate), "specify to perform a RX rate test (sps)") - ("tx_rate", po::value<double>(&tx_rate), "specify to perform a TX rate test (sps)") - ("rx_otw", po::value<std::string>(&rx_otw)->default_value("sc16"), "specify the over-the-wire sample mode for RX") - ("tx_otw", po::value<std::string>(&tx_otw)->default_value("sc16"), "specify the over-the-wire sample mode for TX") - ("rx_cpu", po::value<std::string>(&rx_cpu)->default_value("fc32"), "specify the host/cpu sample mode for RX") - ("tx_cpu", po::value<std::string>(&tx_cpu)->default_value("fc32"), "specify the host/cpu sample mode for TX") - ("mode", po::value<std::string>(&mode)->default_value("none"), "multi-channel sync mode option: none, mimo") - ; - po::variables_map vm; - po::store(po::parse_command_line(argc, argv, desc), vm); - po::notify(vm); - - //print the help message - if (vm.count("help") or (vm.count("rx_rate") + vm.count("tx_rate")) == 0){ - //std::cout << boost::format("UHD Transport Hammer - %s") % desc << std::endl; - std::cout << - "UHD Transport Hammer: a transport layer stress test that continuously\n" - "calls for random amounts of TX and RX samples\n\n"; - std::cout << desc << std::endl << - " Specify --rx_rate for a receive-only test.\n" - " Specify --tx_rate for a transmit-only test.\n" - " Specify both options for a full-duplex test.\n" - << std::endl; - return ~0; - } - - //create a usrp device - std::cout << std::endl; - uhd::device_addrs_t device_addrs = uhd::device::find(args, uhd::device::USRP); - if (not device_addrs.empty() and device_addrs.at(0).get("type", "") == "usrp1"){ - std::cerr << "*** Warning! ***" << std::endl; - std::cerr << "Results will be inaccurate on USRP1 due to insufficient features.\n" << std::endl; - } - std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; - uhd::usrp::multi_usrp::sptr usrp = uhd::usrp::multi_usrp::make(args); - std::cout << boost::format("Using Device: %s") % usrp->get_pp_string() << std::endl; - - if (mode == "mimo"){ - usrp->set_clock_source("mimo", 0); - usrp->set_time_source("mimo", 0); - boost::this_thread::sleep(boost::posix_time::seconds(1)); - } - - boost::thread_group thread_group; - - //spawn the receive test thread - if (vm.count("rx_rate")){ - usrp->set_rx_rate(rx_rate); - //create a receive streamer - uhd::stream_args_t stream_args(rx_cpu, rx_otw); - for (size_t ch = 0; ch < usrp->get_num_mboards(); ch++) //linear channel mapping - stream_args.channels.push_back(ch); - uhd::rx_streamer::sptr rx_stream = usrp->get_rx_stream(stream_args); - thread_group.create_thread(boost::bind(&rx_hammer, usrp, rx_cpu, rx_stream)); - } - - //spawn the transmit test thread - if (vm.count("tx_rate")){ - usrp->set_tx_rate(tx_rate); - //create a transmit streamer - uhd::stream_args_t stream_args(tx_cpu, tx_otw); - for (size_t ch = 0; ch < usrp->get_num_mboards(); ch++) //linear channel mapping - stream_args.channels.push_back(ch); - uhd::tx_streamer::sptr tx_stream = usrp->get_tx_stream(stream_args); - thread_group.create_thread(boost::bind(&tx_hammer, usrp, tx_cpu, tx_stream)); - thread_group.create_thread(boost::bind(&tx_hammer_async_helper, tx_stream)); - } - - //sleep for the required duration - const long secs = long(duration); - const long usecs = long((duration - secs)*1e6); - boost::this_thread::sleep(boost::posix_time::seconds(secs) + boost::posix_time::microseconds(usecs)); - - //interrupt and join the threads - thread_group.interrupt_all(); - thread_group.join_all(); - - //print summary - std::cout << std::endl << boost::format( - "Transport Hammer summary:\n" - " Num received samples: %u\n" - " Num dropped samples: %u\n" - " Num overflows detected: %u\n" - " Num transmitted samples: %u\n" - " Num sequence errors: %u\n" - " Num underflows detected: %u\n" - ) % num_rx_samps % num_dropped_samps % num_overflows % num_tx_samps % num_seq_errors % num_underflows << std::endl; - - //finished - std::cout << std::endl << "Done!" << std::endl << std::endl; - - return EXIT_SUCCESS; -} diff --git a/host/examples/tx_bursts.cpp b/host/examples/tx_bursts.cpp index fec89a0e4..bb71d4581 100644 --- a/host/examples/tx_bursts.cpp +++ b/host/examples/tx_bursts.cpp @@ -148,7 +148,6 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ size_t num_tx_samps = tx_stream->send( buffs, samps_to_send, md, timeout ); - //do not use time spec for subsequent packets md.has_time_spec = false; md.start_of_burst = false; diff --git a/host/examples/tx_waveforms.cpp b/host/examples/tx_waveforms.cpp index d648d2309..942b5df7b 100644 --- a/host/examples/tx_waveforms.cpp +++ b/host/examples/tx_waveforms.cpp @@ -15,6 +15,7 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // +#include "wavetable.hpp" #include <uhd/utils/thread_priority.hpp> #include <uhd/utils/safe_main.hpp> #include <uhd/utils/static.hpp> @@ -28,9 +29,7 @@ #include <boost/lexical_cast.hpp> #include <boost/algorithm/string.hpp> #include <iostream> -#include <complex> #include <csignal> -#include <cmath> namespace po = boost::program_options; @@ -41,52 +40,6 @@ static bool stop_signal_called = false; void sig_int_handler(int){stop_signal_called = true;} /*********************************************************************** - * Waveform generators - **********************************************************************/ -static const size_t wave_table_len = 8192; - -class wave_table_class{ -public: - wave_table_class(const std::string &wave_type, const float ampl): - _wave_table(wave_table_len) - { - //compute real wave table with 1.0 amplitude - std::vector<double> real_wave_table(wave_table_len); - if (wave_type == "CONST"){ - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = 1.0; - } - else if (wave_type == "SQUARE"){ - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = (i < wave_table_len/2)? 0.0 : 1.0; - } - else if (wave_type == "RAMP"){ - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = 2.0*i/(wave_table_len-1) - 1.0; - } - else if (wave_type == "SINE"){ - static const double tau = 2*std::acos(-1.0); - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = std::sin((tau*i)/wave_table_len); - } - else throw std::runtime_error("unknown waveform type: " + wave_type); - - //compute i and q pairs with 90% offset and scale to amplitude - for (size_t i = 0; i < wave_table_len; i++){ - const size_t q = (i+(3*wave_table_len)/4)%wave_table_len; - _wave_table[i] = std::complex<float>(ampl*real_wave_table[i], ampl*real_wave_table[q]); - } - } - - inline std::complex<float> operator()(const size_t index) const{ - return _wave_table[index % wave_table_len]; - } - -private: - std::vector<std::complex<float> > _wave_table; -}; - -/*********************************************************************** * Main function **********************************************************************/ int UHD_SAFE_MAIN(int argc, char *argv[]){ diff --git a/host/examples/txrx_loopback_to_file.cpp b/host/examples/txrx_loopback_to_file.cpp index efa23c410..7dc3bd9c2 100644 --- a/host/examples/txrx_loopback_to_file.cpp +++ b/host/examples/txrx_loopback_to_file.cpp @@ -15,6 +15,7 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // +#include "wavetable.hpp" #include <uhd/types/tune_request.hpp> #include <uhd/utils/thread_priority.hpp> #include <uhd/utils/safe_main.hpp> @@ -31,7 +32,6 @@ #include <iostream> #include <fstream> #include <csignal> -#include <cmath> namespace po = boost::program_options; @@ -61,51 +61,6 @@ std::string generate_out_filename(const std::string &base_fn, size_t n_names, si return base_fn_fp.string(); } -/*********************************************************************** - * Waveform generators - **********************************************************************/ -static const size_t wave_table_len = 8192; - -class wave_table_class{ -public: - wave_table_class(const std::string &wave_type, const float ampl): - _wave_table(wave_table_len) - { - //compute real wave table with 1.0 amplitude - std::vector<double> real_wave_table(wave_table_len); - if (wave_type == "CONST"){ - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = 1.0; - } - else if (wave_type == "SQUARE"){ - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = (i < wave_table_len/2)? 0.0 : 1.0; - } - else if (wave_type == "RAMP"){ - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = 2.0*i/(wave_table_len-1) - 1.0; - } - else if (wave_type == "SINE"){ - static const double tau = 2*std::acos(-1.0); - for (size_t i = 0; i < wave_table_len; i++) - real_wave_table[i] = std::sin((tau*i)/wave_table_len); - } - else throw std::runtime_error("unknown waveform type: " + wave_type); - - //compute i and q pairs with 90% offset and scale to amplitude - for (size_t i = 0; i < wave_table_len; i++){ - const size_t q = (i+(3*wave_table_len)/4)%wave_table_len; - _wave_table[i] = std::complex<float>(ampl*real_wave_table[i], ampl*real_wave_table[q]); - } - } - - inline std::complex<float> operator()(const size_t index) const{ - return _wave_table[index % wave_table_len]; - } - -private: - std::vector<std::complex<float> > _wave_table; -}; /*********************************************************************** * transmit_worker function diff --git a/host/examples/wavetable.hpp b/host/examples/wavetable.hpp new file mode 100644 index 000000000..d7ffc8406 --- /dev/null +++ b/host/examples/wavetable.hpp @@ -0,0 +1,66 @@ +// +// Copyright 2010-2012,2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <string> +#include <cmath> +#include <complex> +#include <vector> +#include <stdexcept> + +static const size_t wave_table_len = 8192; + +class wave_table_class{ +public: + wave_table_class(const std::string &wave_type, const float ampl): + _wave_table(wave_table_len) + { + //compute real wave table with 1.0 amplitude + std::vector<double> real_wave_table(wave_table_len); + if (wave_type == "CONST"){ + for (size_t i = 0; i < wave_table_len; i++) + real_wave_table[i] = 1.0; + } + else if (wave_type == "SQUARE"){ + for (size_t i = 0; i < wave_table_len; i++) + real_wave_table[i] = (i < wave_table_len/2)? 0.0 : 1.0; + } + else if (wave_type == "RAMP"){ + for (size_t i = 0; i < wave_table_len; i++) + real_wave_table[i] = 2.0*i/(wave_table_len-1) - 1.0; + } + else if (wave_type == "SINE"){ + static const double tau = 2*std::acos(-1.0); + for (size_t i = 0; i < wave_table_len; i++) + real_wave_table[i] = std::sin((tau*i)/wave_table_len); + } + else throw std::runtime_error("unknown waveform type: " + wave_type); + + //compute i and q pairs with 90% offset and scale to amplitude + for (size_t i = 0; i < wave_table_len; i++){ + const size_t q = (i+(3*wave_table_len)/4)%wave_table_len; + _wave_table[i] = std::complex<float>(ampl*real_wave_table[i], ampl*real_wave_table[q]); + } + } + + inline std::complex<float> operator()(const size_t index) const{ + return _wave_table[index % wave_table_len]; + } + +private: + std::vector<std::complex<float> > _wave_table; +}; + diff --git a/host/include/uhd/config.hpp b/host/include/uhd/config.hpp index 7ecc4924a..8939cd773 100644 --- a/host/include/uhd/config.hpp +++ b/host/include/uhd/config.hpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2011 Ettus Research LLC +// Copyright 2010-2011,2014-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -56,6 +56,13 @@ typedef ptrdiff_t ssize_t; #define UHD_DEPRECATED __declspec(deprecated) #define UHD_ALIGNED(x) __declspec(align(x)) #define UHD_UNUSED(x) x +#elif defined(__MINGW32__) + #define UHD_EXPORT __declspec(dllexport) + #define UHD_IMPORT __declspec(dllimport) + #define UHD_INLINE inline + #define UHD_DEPRECATED __declspec(deprecated) + #define UHD_ALIGNED(x) __declspec(align(x)) + #define UHD_UNUSED(x) x __attribute__((unused)) #elif defined(__GNUG__) && __GNUG__ >= 4 #define UHD_EXPORT __attribute__((visibility("default"))) #define UHD_IMPORT __attribute__((visibility("default"))) diff --git a/host/include/uhd/convert.hpp b/host/include/uhd/convert.hpp index d740d80fb..e42123b20 100644 --- a/host/include/uhd/convert.hpp +++ b/host/include/uhd/convert.hpp @@ -63,12 +63,13 @@ namespace uhd{ namespace convert{ typedef int priority_type; //! Identify a conversion routine in the registry - struct id_type : boost::equality_comparable<id_type>{ + struct UHD_API id_type : boost::equality_comparable<id_type>{ std::string input_format; size_t num_inputs; std::string output_format; size_t num_outputs; std::string to_pp_string(void) const; + std::string to_string(void) const; }; //! Implement equality_comparable interface diff --git a/host/include/uhd/transport/CMakeLists.txt b/host/include/uhd/transport/CMakeLists.txt index 2118674c6..623c179e9 100644 --- a/host/include/uhd/transport/CMakeLists.txt +++ b/host/include/uhd/transport/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2010-2013 Ettus Research LLC +# Copyright 2010-2014 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,11 +15,11 @@ # along with this program. If not, see <http://www.gnu.org/licenses/>. # - UHD_INSTALL(FILES bounded_buffer.hpp bounded_buffer.ipp buffer_pool.hpp + chdr.hpp if_addrs.hpp udp_constants.hpp udp_simple.hpp diff --git a/host/include/uhd/transport/chdr.hpp b/host/include/uhd/transport/chdr.hpp new file mode 100644 index 000000000..5e8cd58a9 --- /dev/null +++ b/host/include/uhd/transport/chdr.hpp @@ -0,0 +1,113 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_UHD_TRANSPORT_CHDR_HPP +#define INCLUDED_UHD_TRANSPORT_CHDR_HPP + +#include <uhd/transport/vrt_if_packet.hpp> + +namespace uhd{ namespace transport{ namespace vrt{ + +/*! \brief CVITA/CHDR related function + * + * See \ref rtp_chdr for details on the CVITA/CHDR protocol. + * + * All packers take the host format into account. Choose the _le functions + * if the transport uses little endian format (e.g. PCIe) and the _be + * functions if the transport uses big endian format (e.g. Ethernet). + * + * Note 1: All packers assume there to be enough space at the address + * provided by \p packet_buff. See also \ref vrt_pack_contract. + * + * Note 2: All these packers assume the following options without checking them: + * - `if_packet_info.link_type == LINK_TYPE_CHDR` + * - `if_packet_info.has_cid == false` + * - `if_packet_info.has_sid == true` + * - `if_packet_info.has_tsi == false` + * - `if_packet_info.has_tlr == false` + * This relaxes some of \ref vrt_pack_contract, but adds the additional + * constraint that the input data must be CHDR. + * + * In the unpacker, these values will be set accordingly. + */ +namespace chdr{ + + //! The maximum number of 64-bit words in a CVITA header + static const size_t max_if_hdr_words64 = 2; // CHDR + tsf (fractional timestamp) + + /*! + * Pack a CHDR header from metadata (big endian format). + * + * See \ref vrt_pack_contract, but `link_type` is assumed to be + * `LINK_TYPE_CHDR`. + * + * \param packet_buff memory to write the packed vrt header + * \param if_packet_info the if packet info (read/write) + */ + UHD_API void if_hdr_pack_be( + boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info + ); + + /*! + * Unpack a CHDR header to metadata (big endian format). + * + * See \ref vrt_unpack_contract, but `link_type` is assumed to be + * `LINK_TYPE_CHDR`. + * + * \param packet_buff memory to read the packed vrt header + * \param if_packet_info the if packet info (read/write) + */ + UHD_API void if_hdr_unpack_be( + const boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info + ); + + /*! + * Pack a CHDR header from metadata (little endian format). + * + * See \ref vrt_pack_contract, but `link_type` is assumed to be + * `LINK_TYPE_CHDR`. + * + * \param packet_buff memory to write the packed vrt header + * \param if_packet_info the if packet info (read/write) + */ + UHD_API void if_hdr_pack_le( + boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info + ); + + /*! + * Unpack a CHDR header to metadata (little endian format). + * + * See \ref vrt_unpack_contract, but `link_type` is assumed to be + * `LINK_TYPE_CHDR`. + * + * \param packet_buff memory to read the packed vrt header + * \param if_packet_info the if packet info (read/write) + */ + UHD_API void if_hdr_unpack_le( + const boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info + ); + +} //namespace chdr + +}}} //namespace uhd::transport::vrt + +#endif /* INCLUDED_UHD_TRANSPORT_CHDR_HPP */ + diff --git a/host/include/uhd/transport/nirio/nirio_driver_iface.h b/host/include/uhd/transport/nirio/nirio_driver_iface.h index 83afd816a..c562f0ca5 100644 --- a/host/include/uhd/transport/nirio/nirio_driver_iface.h +++ b/host/include/uhd/transport/nirio/nirio_driver_iface.h @@ -1,5 +1,5 @@ // -// Copyright 2013-2014 Ettus Research LLC +// Copyright 2013-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -24,10 +24,14 @@ #include <uhd/transport/nirio/status.h> #include <uhd/config.hpp> #if defined(UHD_PLATFORM_WIN32) - #include <Windows.h> - #pragma warning(disable:4201) // nonstandard extension used : nameless struct/union - #include <WinIoCtl.h> - #pragma warning(default:4201) + #include <windows.h> + #ifdef _MSC_VER + #pragma warning(disable:4201) // nonstandard extension used : nameless struct/union + #endif + #include <winioctl.h> + #ifdef _MSC_VER + #pragma warning(default:4201) + #endif #elif !defined(UHD_PLATFORM_LINUX) #include <IOKit/IOKitLib.h> #endif diff --git a/host/include/uhd/transport/nirio/nirio_fifo.h b/host/include/uhd/transport/nirio/nirio_fifo.h index c424275fc..5a2e29631 100644 --- a/host/include/uhd/transport/nirio/nirio_fifo.h +++ b/host/include/uhd/transport/nirio/nirio_fifo.h @@ -59,8 +59,8 @@ public: inline const std::string& get_name() const { return _name; } inline uint32_t get_channel() const { return _fifo_channel; } - inline uint32_t get_direction() const { return _fifo_direction; } - inline uint32_t get_scalar_type() const { return _datatype_info.scalar_type; } + inline fifo_direction_t get_direction() const { return _fifo_direction; } + inline nirio_scalar_type_t get_scalar_type() const { return _datatype_info.scalar_type; } nirio_status start(); diff --git a/host/include/uhd/transport/usb_device_handle.hpp b/host/include/uhd/transport/usb_device_handle.hpp index fdea9e2be..bf122f549 100644 --- a/host/include/uhd/transport/usb_device_handle.hpp +++ b/host/include/uhd/transport/usb_device_handle.hpp @@ -41,6 +41,7 @@ namespace uhd { namespace transport { class UHD_API usb_device_handle : boost::noncopyable { public: typedef boost::shared_ptr<usb_device_handle> sptr; + typedef std::pair<boost::uint16_t, boost::uint16_t> vid_pid_pair_t; /*! * Return the device's serial number @@ -83,6 +84,8 @@ public: * \return a vector of USB device handles that match vid and pid */ static std::vector<usb_device_handle::sptr> get_device_list(boost::uint16_t vid, boost::uint16_t pid); + static std::vector<usb_device_handle::sptr> get_device_list(const std::vector<usb_device_handle::vid_pid_pair_t>& vid_pid_pair_list); + }; //namespace usb diff --git a/host/include/uhd/transport/vrt_if_packet.hpp b/host/include/uhd/transport/vrt_if_packet.hpp index 362531567..1e54607c1 100644 --- a/host/include/uhd/transport/vrt_if_packet.hpp +++ b/host/include/uhd/transport/vrt_if_packet.hpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2013 Ettus Research LLC +// Copyright 2010-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -52,9 +52,18 @@ namespace vrt{ //packet type enum packet_type_t { + // VRT language: PACKET_TYPE_DATA = 0x0, PACKET_TYPE_IF_EXT = 0x1, - PACKET_TYPE_CONTEXT = 0x2 //extension context: has_sid = true + PACKET_TYPE_CONTEXT = 0x2, //extension context: has_sid = true + + // CVITA language: + //PACKET_TYPE_DATA = 0x0, // Data + PACKET_TYPE_FC = 0x1, // Flow control + PACKET_TYPE_ACK = 0x1, // Flow control (ack) + PACKET_TYPE_CMD = 0x2, // Command + PACKET_TYPE_RESP = 0x3, // Command response + PACKET_TYPE_ERROR = 0x3 // Command response: Error (the EOB bit is raised in this case) } packet_type; //size fields @@ -65,18 +74,46 @@ namespace vrt{ //header fields size_t packet_count; + //! Asserted for start- or end-of-burst bool sob, eob; + //! This is asserted for command responses that are errors (CHDR only) + bool error; //optional fields + //! Stream ID (SID). See uhd::sid_t bool has_sid; boost::uint32_t sid; + //! Class ID. bool has_cid; boost::uint64_t cid; + //! Integer timestamp bool has_tsi; boost::uint32_t tsi; + //! Fractional timestamp bool has_tsf; boost::uint64_t tsf; + //! Trailer bool has_tlr; boost::uint32_t tlr; }; /*! * Pack a vrt header from metadata (big endian format). + * + * \section vrt_pack_contract Packing contract + * + * \subsection Requirements: + * - packet_buff points to a valid address space with enough space to write + * the entire buffer, regardless of its length. At the very least, it must + * be able to hold an entire header. + * - `if_packet_info` has the following members set to correct values: + * - `has_*` members all set accordingly + * - For every true `has_*` member, the corresponding variable holds a valid + * value (e.g. if `has_sid` is true, `sid` contains a valid SID) + * - `num_payload_bytes` and `num_payload_words32` are both set to the correct values + * + * \subsection Result: + * - `packet_buff` now points to a valid header that can be sent over the transport + * without further modification + * - The following members on `if_packet_info` are set: + * - `num_header_words32` + * - `num_packet_words32` + * * \param packet_buff memory to write the packed vrt header * \param if_packet_info the if packet info (read/write) */ @@ -87,6 +124,34 @@ namespace vrt{ /*! * Unpack a vrt header to metadata (big endian format). + * + * \section vrt_unpack_contract Unpacking contract + * + * \subsection Requirements + * - `packet_buff` points to a readable address space with a + * CHDR packet, starting at the header. `packet_buff[0]` *must* always + * point to a valid first word of the header. This implies that num_packet_words32 + * must be at least 1. + * - `if_packet_info` has the following members set to correct values: + * - `num_packet_words32`. This means all values `packet_buff[0]` + * through `packet_buff[if_packet_info.num_packet_words32-1]` are + * readable words from this packet. + * - `link_type` + * + * \subsection Result + * - `if_packet_info` now has the following values set to correct values: + * - `packet_type` + * - `num_payload_bytes` + * - `num_payload_words32` + * - `num_header_words32` + * - `has_*` + * - `sob`, `eob`, `error`, `cid`, `sid` (if applicable) + * - `tsf`, `tsi` (if applicable) + * + * \subsection Exceptions + * - If the header is invalid, but the requirements are still met, + * will throw a uhd::value_error. + * * \param packet_buff memory to read the packed vrt header * \param if_packet_info the if packet info (read/write) */ @@ -97,6 +162,9 @@ namespace vrt{ /*! * Pack a vrt header from metadata (little endian format). + * + * See \ref vrt_pack_contract. + * * \param packet_buff memory to write the packed vrt header * \param if_packet_info the if packet info (read/write) */ @@ -107,6 +175,9 @@ namespace vrt{ /*! * Unpack a vrt header to metadata (little endian format). + * + * See \ref vrt_unpack_contract. + * * \param packet_buff memory to read the packed vrt header * \param if_packet_info the if packet info (read/write) */ @@ -124,6 +195,7 @@ namespace vrt{ num_packet_words32(0), packet_count(0), sob(false), eob(false), + error(false), has_sid(false), sid(0), has_cid(false), cid(0), has_tsi(false), tsi(0), diff --git a/host/include/uhd/types/CMakeLists.txt b/host/include/uhd/types/CMakeLists.txt index 8bb1de381..2a25df35f 100644 --- a/host/include/uhd/types/CMakeLists.txt +++ b/host/include/uhd/types/CMakeLists.txt @@ -17,6 +17,7 @@ UHD_INSTALL(FILES + byte_vector.hpp clock_config.hpp device_addr.hpp dict.ipp @@ -31,11 +32,13 @@ UHD_INSTALL(FILES ref_vector.hpp sensors.hpp serial.hpp + sid.hpp stream_cmd.hpp time_spec.hpp tune_request.hpp tune_result.hpp wb_iface.hpp + filters.hpp DESTINATION ${INCLUDE_DIR}/uhd/types COMPONENT headers ) diff --git a/host/include/uhd/types/byte_vector.hpp b/host/include/uhd/types/byte_vector.hpp new file mode 100644 index 000000000..b7637fb5d --- /dev/null +++ b/host/include/uhd/types/byte_vector.hpp @@ -0,0 +1,48 @@ +// +// Copyright 2015 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_UHD_TYPES_BYTE_VECTOR_HPP +#define INCLUDED_UHD_TYPES_BYTE_VECTOR_HPP + +#include <algorithm> +#include <string> +#include <vector> + +#include <boost/assign.hpp> +#include <boost/cstdint.hpp> + +#include <uhd/config.hpp> + +namespace uhd{ + + //! Byte vector used for I2C data passing and EEPROM parsing. + typedef std::vector<boost::uint8_t> byte_vector_t; + + template<typename RangeSrc, typename RangeDst> UHD_INLINE + void byte_copy(const RangeSrc &src, RangeDst &dst){ + std::copy(boost::begin(src), boost::end(src), boost::begin(dst)); + } + + //! Create a string from a byte vector, terminate when invalid ASCII encountered + UHD_API std::string bytes_to_string(const byte_vector_t &bytes); + + //! Create a byte vector from a string, end at null terminator or max length + UHD_API byte_vector_t string_to_bytes(const std::string &str, size_t max_length); + +} //namespace uhd + +#endif /* INCLUDED_UHD_TYPES_BYTE_VECTOR_HPP */ diff --git a/host/include/uhd/types/dict.hpp b/host/include/uhd/types/dict.hpp index 97fa8f09c..51e3e1814 100644 --- a/host/include/uhd/types/dict.hpp +++ b/host/include/uhd/types/dict.hpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2011 Ettus Research LLC +// Copyright 2010-2011,2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -117,6 +117,23 @@ namespace uhd{ */ Val pop(const Key &key); + /*! Update this dictionary with values from another. + * + * Basically, this copies all the key/value pairs from \p new_dict + * into this dict. When the key is already present in the current + * dict, it either overwrites the current value (if \p fail_on_conflict + * is false) or it throws (if \p fail_on_conflict is true *and* the + * values differ). + * + * With the exception of \p fail_on_conflict, this behaves analogously + * to Python's dict.update() method. + * + * \param new_args The arguments to copy. + * \param fail_on_conflict If true, throws. + * \throws uhd::value_error + */ + void update(const dict<Key, Val> &new_dict, bool fail_on_conflict=true); + private: typedef std::pair<Key, Val> pair_t; std::list<pair_t> _map; //private container diff --git a/host/include/uhd/types/dict.ipp b/host/include/uhd/types/dict.ipp index 5e9cf97ad..5fd4b536e 100644 --- a/host/include/uhd/types/dict.ipp +++ b/host/include/uhd/types/dict.ipp @@ -135,6 +135,20 @@ namespace uhd{ throw key_not_found<Key, Val>(key); } + template <typename Key, typename Val> + void dict<Key, Val>::update(const dict<Key, Val> &new_dict, bool fail_on_conflict) + { + BOOST_FOREACH(const Key &key, new_dict.keys()) { + if (fail_on_conflict and has_key(key) and get(key) != new_dict[key]) { + throw uhd::value_error(str( + boost::format("Option merge conflict: %s:%s != %s:%s") + % key % get(key) % key % new_dict[key] + )); + } + set(key, new_dict[key]); + } + } + } //namespace uhd #endif /* INCLUDED_UHD_TYPES_DICT_IPP */ diff --git a/host/include/uhd/types/direction.hpp b/host/include/uhd/types/direction.hpp index 0f257de44..59ee9b55f 100644 --- a/host/include/uhd/types/direction.hpp +++ b/host/include/uhd/types/direction.hpp @@ -1,5 +1,5 @@ // -// Copyright 2015 Ettus Research LLC +// Copyright 2014-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by diff --git a/host/include/uhd/types/filters.hpp b/host/include/uhd/types/filters.hpp new file mode 100644 index 000000000..976ae233d --- /dev/null +++ b/host/include/uhd/types/filters.hpp @@ -0,0 +1,286 @@ +// +// Copyright 2015 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_UHD_TYPES_FILTERS_HPP +#define INCLUDED_UHD_TYPES_FILTERS_HPP + +#include <uhd/config.hpp> +#include <uhd/utils/log.hpp> +#include <uhd/utils/msg.hpp> +#include <boost/cstdint.hpp> +#include <boost/shared_ptr.hpp> +#include <boost/scoped_array.hpp> +#include <string> +#include <vector> +#include <iostream> +#include <ostream> +#include <sstream> + +namespace uhd{ + + class UHD_API filter_info_base + { + public: + typedef boost::shared_ptr<filter_info_base> sptr; + enum filter_type + { + ANALOG_LOW_PASS, + ANALOG_BAND_PASS, + DIGITAL_I16, + DIGITAL_FIR_I16 + }; + + filter_info_base( + filter_type type, + bool bypass, + size_t position_index + ): + _type(type), _bypass(bypass), + _position_index(position_index) + { + //NOP + } + + inline virtual bool is_bypassed() + { + return _bypass; + } + + inline filter_type get_type() + { + return _type; + } + + virtual ~filter_info_base() + { + //NOP + } + + virtual std::string to_pp_string(); + + protected: + filter_type _type; + bool _bypass; + size_t _position_index; + + }; + + UHD_API std::ostream& operator<<(std::ostream& os, filter_info_base& f); + + class UHD_API analog_filter_base : public filter_info_base + { + std::string _analog_type; + public: + typedef boost::shared_ptr<analog_filter_base> sptr; + analog_filter_base( + filter_type type, + bool bypass, + size_t position_index, + const std::string& analog_type + ): + filter_info_base(type, bypass, position_index), + _analog_type(analog_type) + { + //NOP + } + + inline const std::string& get_analog_type() + { + return _analog_type; + } + + virtual std::string to_pp_string(); + }; + + class UHD_API analog_filter_lp : public analog_filter_base + { + double _cutoff; + double _rolloff; + + public: + typedef boost::shared_ptr<analog_filter_lp> sptr; + analog_filter_lp( + filter_type type, + bool bypass, + size_t position_index, + const std::string& analog_type, + double cutoff, + double rolloff + ): + analog_filter_base(type, bypass, position_index, analog_type), + _cutoff(cutoff), + _rolloff(rolloff) + { + //NOP + } + + inline double get_cutoff() + { + return _cutoff; + } + + inline double get_rolloff() + { + return _cutoff; + } + + inline void set_cutoff(const double cutoff) + { + _cutoff = cutoff; + } + + virtual std::string to_pp_string(); + }; + + template<typename tap_t> + class UHD_API digital_filter_base : public filter_info_base + { + protected: + double _rate; + boost::uint32_t _interpolation; + boost::uint32_t _decimation; + tap_t _tap_full_scale; + boost::uint32_t _max_num_taps; + std::vector<tap_t> _taps; + + public: + typedef boost::shared_ptr<digital_filter_base> sptr; + digital_filter_base( + filter_type type, + bool bypass, + size_t position_index, + double rate, + size_t interpolation, + size_t decimation, + double tap_full_scale, + size_t max_num_taps, + const std::vector<tap_t>& taps + ): + filter_info_base(type, bypass, position_index), + _rate(rate), + _interpolation(interpolation), + _decimation(decimation), + _tap_full_scale(tap_full_scale), + _max_num_taps(max_num_taps), + _taps(taps) + { + //NOP + } + + inline double get_output_rate() + { + return (_bypass ? _rate : (_rate / _decimation * _interpolation)); + } + + inline double get_input_rate() + { + return _rate; + } + + inline double get_interpolation() + { + return _interpolation; + } + + inline double get_decimation() + { + return _decimation; + } + + inline double get_tap_full_scale() + { + return _tap_full_scale; + } + + inline std::vector<tap_t>& get_taps() + { + return _taps; + } + + virtual std::string to_pp_string() + { + std::ostringstream os; + os<<filter_info_base::to_pp_string()<< + "\t[digital_filter_base]"<<std::endl<< + "\tinput rate: "<<_rate<<std::endl<< + "\tinterpolation: "<<_interpolation<<std::endl<< + "\tdecimation: "<<_decimation<<std::endl<< + "\tfull-scale: "<<_tap_full_scale<<std::endl<< + "\tmax num taps: "<<_max_num_taps<<std::endl<< + "\ttaps: "<<std::endl; + + os<<"\t\t"; + for(size_t i = 0; i < _taps.size(); i++) + { + os<<"(tap "<<i<<": "<<_taps[i]<<")"; + if( ((i%10) == 0) && (i != 0)) + { + os<<std::endl<<"\t\t"; + } + } + os<<std::endl; + return std::string(os.str()); + } + + }; + + template<typename tap_t> + class UHD_API digital_filter_fir : public digital_filter_base<tap_t> + { + public: + typedef boost::shared_ptr<digital_filter_fir<tap_t> > sptr; + + digital_filter_fir( + filter_info_base::filter_type type, + bool bypass, size_t position_index, + double rate, + size_t interpolation, + size_t decimation, + size_t tap_bit_width, + size_t max_num_taps, + const std::vector<tap_t>& taps + ): + digital_filter_base<tap_t>(type, bypass, position_index, rate, interpolation, decimation, tap_bit_width, max_num_taps, taps) + { + //NOP + } + + void set_taps(const std::vector<tap_t>& taps) + { + std::size_t num_taps = taps.size(); + if(num_taps < this->_max_num_taps){ + UHD_MSG(warning) << "digital_filter_fir::set_taps not enough coefficients. Appending zeros"; + std::vector<tap_t> coeffs; + for (size_t i = 0; i < this->_max_num_taps; i++) + { + if(i < num_taps) + { + coeffs.push_back(taps[i]); + } else { + coeffs.push_back(0); + } + } + this->_taps = coeffs; + } else { + this->_taps = taps; + } + } + }; + +} //namespace uhd + +#endif /* INCLUDED_UHD_TYPES_FILTERS_HPP */ diff --git a/host/include/uhd/types/sid.hpp b/host/include/uhd/types/sid.hpp new file mode 100644 index 000000000..95034c7a5 --- /dev/null +++ b/host/include/uhd/types/sid.hpp @@ -0,0 +1,238 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_UHD_TYPES_SID_HPP +#define INCLUDED_UHD_TYPES_SID_HPP + +#include <uhd/config.hpp> +#include <boost/cstdint.hpp> +#include <boost/shared_ptr.hpp> +#include <iostream> + +namespace uhd { + /*! + * \brief Represents a stream ID (SID). + * + * A stream ID (SID) is an identifier for data. + * It is a 32-Bit value which consistst of 16 Bits + * for the source address and 16 Bits for the destination + * address. + * Every address is split into two parts: The _address_, which + * identifies the device used, and the _endpoint_, which identifies + * a specific object inside the given device (e.g., a block). + * *Note:* In the case where there are several crossbars on a single + * device, each crossbar gets its own address. + * Both address and endpoint are 8 bits in length. If a 16-bit address + * is required, we use the combination of the 8-bit address and the 8-bit + * endpoint. + * + * \section sid_str_repr String Representation + * + * The string representation of a SID is of the form + * + * 2.3>0.6 + * + * The '>' symbol shows the direction, so in this case, + * data is flowing from address 2.3 to 0.6. + * + * As a convention, ':' is used instead of '.' when giving the + * SID in hexadecimal numbers, and two characters are used for each + * address part. As an example, the following two SIDs are identical: + * + * 2.3>0.16 (decimal) + * 02:03>00:10 (hexadecimal) + * + * The format is: + * SRC_ADDRESS.SRC_ENDPOINT>DST_ADDRESS.DST_ENDPOINT + * + * + * \section sid_block_ports Block Ports + * + * In the special case where a block on a crossbar is addressed, the + * endpoint is further split up into two parts of four bits each: The + * first four bits specify the port number on the crossbar, whereas the + * lower four bits represent the *block port*. As an example, consider + * the following SID, given in hexadecimal: + * + * 00:10>02:A1 + * + * In this example, assume data is flowing from the host computer to an + * X300. The crossbar address is 02. The endpoint is A1, which means we + * are accessing a block on crossbar port A (the tenth port), and are addressing + * block port 1. + * + */ + class UHD_API sid_t + { + public: + //! Create an unset SID + sid_t(); + //! Create a sid_t object from a 32-Bit SID value + sid_t(boost::uint32_t sid); + //! Create a sid_t object from its four components + sid_t(boost::uint8_t src_addr, boost::uint8_t src_ep, boost::uint8_t dst_addr, boost::uint8_t dst_ep); + //! Convert a string representation of a SID into its numerical representation + sid_t(const std::string &); + + //! Return a decimal string representation of the SID. + std::string to_pp_string() const; + //! Return a hexadecimal string representation of the SID. + std::string to_pp_string_hex() const; + + //! Returns true if this actually holds a valid SID + bool is_set() const { return _set; }; + + // Getters + // + //! Alias for get_sid() + UHD_INLINE boost::uint32_t get() const { return get_sid(); }; + //! Returns a 32-Bit representation of the SID if set, or zero otherwise. + UHD_INLINE boost::uint32_t get_sid() const { return _set ? _sid : 0; }; + //! Return the 16-bit source address of this SID + UHD_INLINE boost::uint32_t get_src() const { + return (_sid >> 16) & 0xFFFF; + } + //! Return the 16-bit destination address of this SID + UHD_INLINE boost::uint32_t get_dst() const { + return _sid & 0xFFFF; + } + //! Return 8-bit address of the source + UHD_INLINE boost::uint32_t get_src_addr() const { + return (get_src() >> 8) & 0xFF; + } + //! Return endpoint of the source + UHD_INLINE boost::uint32_t get_src_endpoint() const { + return get_src() & 0xFF; + } + //! Return crossbar port of the source + UHD_INLINE boost::uint32_t get_src_xbarport() const { + return (get_src_endpoint() >> 4) & 0xF; + } + //! Return block port of the source + UHD_INLINE boost::uint32_t get_src_blockport() const { + return (get_src_endpoint()) & 0xF; + } + //! Return 8-bit address of the destination + UHD_INLINE boost::uint32_t get_dst_addr() const { + return (get_dst() >> 8) & 0xFF; + } + //! Return endpoint of the destination + UHD_INLINE boost::uint32_t get_dst_endpoint() const { + return get_dst() & 0xFF; + } + //! Return crossbar port of the source + UHD_INLINE boost::uint32_t get_dst_xbarport() const { + return (get_dst_endpoint() >> 4) & 0xF; + } + //! Return block port of the source + UHD_INLINE boost::uint32_t get_dst_blockport() const { + return (get_dst_endpoint()) & 0xF; + } + + // Setters + + //! Alias for set_sid() + void set(boost::uint32_t new_sid) { set_sid(new_sid); }; + //! Convert a string representation of a SID into a numerical one + // Throws uhd::value_error if the string is not a valid SID + // representation. + void set_from_str(const std::string &); + void set_sid(boost::uint32_t new_sid); + //! Set the source address of this SID + // (the first 16 Bits) + void set_src(boost::uint32_t new_addr); + //! Set the destination address of this SID + // (the last 16 Bits) + void set_dst(boost::uint32_t new_addr); + void set_src_addr(boost::uint32_t new_addr); + void set_src_endpoint(boost::uint32_t new_addr); + void set_dst_addr(boost::uint32_t new_addr); + void set_dst_endpoint(boost::uint32_t new_addr); + void set_dst_xbarport(boost::uint32_t new_xbarport); + void set_dst_blockport(boost::uint32_t new_blockport); + + // Manipulators + + //! Swaps dst and src address and returns the new SID. + sid_t reversed(); + + //! Swaps dst and src in-place. + void reverse(); + + // Overloaded operators + + sid_t operator = (boost::uint32_t new_sid) { + set_sid(new_sid); + return *this; + } + + sid_t operator = (sid_t &sid) { + set_sid(sid.get_sid()); + return *this; + } + + sid_t operator = (const std::string &sid_str) { + set_from_str(sid_str); + return *this; + } + + bool operator == (const sid_t &sid) const { + return (not _set and not sid.is_set()) or (_sid == sid.get_sid()); + } + + bool operator == (boost::uint32_t sid) const { + return _set and _sid == sid; + } + + bool operator == (const std::string &sid_str) const { + sid_t rhs(sid_str); + return *this == rhs; + } + + // overloaded type casts are tricky, but for now we'll need them + // for backward compatibility. consider them deprecated. + + //! If the SID is not set, always returns zero. + // Use is_set() to check if the return value is valid. + operator boost::uint32_t() const { + return get(); + } + + operator bool() const { + return _set; + } + + private: + boost::uint32_t _sid; + bool _set; + }; + + //! Stream output operator. Honors std::ios::hex. + UHD_INLINE std::ostream& operator<< (std::ostream& out, const sid_t &sid) { + std::ios_base::fmtflags ff = out.flags(); + if (ff & std::ios::hex) { + out << sid.to_pp_string_hex(); + } else { + out << sid.to_pp_string(); + } + return out; + } + +} //namespace uhd + +#endif /* INCLUDED_UHD_TYPES_SID_HPP */ +// vim: sw=4 et: diff --git a/host/include/uhd/usrp/multi_usrp.hpp b/host/include/uhd/usrp/multi_usrp.hpp index 7ac38f84b..8d5dc2e5f 100644 --- a/host/include/uhd/usrp/multi_usrp.hpp +++ b/host/include/uhd/usrp/multi_usrp.hpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2012,2014 Ettus Research LLC +// Copyright 2010-2012,2014-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -22,6 +22,7 @@ #define UHD_USRP_MULTI_USRP_REF_SOURCES_API #define UHD_USRP_MULTI_USRP_GET_RATES_API #define UHD_USRP_MULTI_USRP_FRONTEND_CAL_API +#define UHD_USRP_MULTI_USRP_FRONTEND_IQ_AUTO_API #define UHD_USRP_MULTI_USRP_COMMAND_TIME_API #define UHD_USRP_MULTI_USRP_BW_RANGE_API #define UHD_USRP_MULTI_USRP_USER_REGS_API @@ -37,6 +38,7 @@ #include <uhd/types/tune_request.hpp> #include <uhd/types/tune_result.hpp> #include <uhd/types/sensors.hpp> +#include <uhd/types/filters.hpp> #include <uhd/usrp/subdev_spec.hpp> #include <uhd/usrp/dboard_iface.hpp> #include <boost/shared_ptr.hpp> @@ -157,6 +159,11 @@ public: * If the specified rate is not available, this method will throw. * On other devices, this method notifies the software of the rate, * but requires the the user has made the necessary hardware change. + * + * If the device has an 'auto clock rate' setting (e.g. B200, see also + * \ref b200_auto_mcr), this will get disabled and the clock rate will be + * fixed to \p rate. + * * \param rate the new master clock rate in Hz * \param mboard the motherboard index 0 to M-1 */ @@ -492,6 +499,34 @@ public: } /*! + * Set the normalized RX gain value. + * + * The normalized gain is a value in [0, 1], where 0 is the + * smallest gain value available, and 1 is the largest, independent + * of the device. In between, gains are linearly interpolated. + * + * Check the individual device manual for notes on the gain range. + * + * Note that it is not possible to specify a gain name for + * this function, it will always set the overall gain. + * + * \param gain the normalized gain value + * \param chan the channel index 0 to N-1 + * \throws A uhd::runtime_error if the gain value is outside [0, 1]. + */ + virtual void set_normalized_rx_gain(double gain, size_t chan = 0) = 0; + + /*! + * Enable or disable the RX AGC module. + * Once this module is enabled manual gain settings will be ignored. + * The AGC will start in a default configuration which should be good for most use cases. + * Device specific configuration parameters can be found in the property tree. + * \param enable Enable or Disable the AGC + * \param chan the channel index 0 to N-1 + */ + virtual void set_rx_agc(bool enable, size_t chan = 0) = 0; + + /*! * Get the RX gain value for the specified gain element. * For an empty name, sum across all gain elements. * \param name the name of the gain element @@ -506,6 +541,18 @@ public: } /*! + * Return the normalized RX gain value. + * + * See set_normalized_rx_gain() for a discussion of normalized + * gains. + * + * \param chan the channel index 0 to N-1 + * \returns The normalized gain (in [0, 1]) + * \throws A uhd::runtime_error if the gain value is outside [0, 1]. + */ + virtual double get_normalized_rx_gain(size_t chan = 0) = 0; + + /*! * Get the RX gain range for the specified gain element. * For an empty name, calculate the overall gain range. * \param name the name of the gain element @@ -617,6 +664,14 @@ public: virtual void set_rx_dc_offset(const std::complex<double> &offset, size_t chan = ALL_CHANS) = 0; /*! + * Enable/disable the automatic IQ imbalance correction. + * + * \param enb true to enable automatic IQ balance correction + * \param chan the channel index 0 to N-1 + */ + virtual void set_rx_iq_balance(const bool enb, size_t chan) = 0; + + /*! * Set the RX frontend IQ imbalance correction. * Use this to adjust the magnitude and phase of I and Q. * @@ -730,6 +785,18 @@ public: } /*! + * Set the normalized TX gain value. + * + * See set_normalized_rx_gain() for a discussion on normalized + * gains. + * + * \param gain the normalized gain value + * \param chan the channel index 0 to N-1 + * \throws A uhd::runtime_error if the gain value is outside [0, 1]. + */ + virtual void set_normalized_tx_gain(double gain, size_t chan = 0) = 0; + + /*! * Get the TX gain value for the specified gain element. * For an empty name, sum across all gain elements. * \param name the name of the gain element @@ -744,6 +811,18 @@ public: } /*! + * Return the normalized TX gain value. + * + * See set_normalized_rx_gain() for a discussion of normalized + * gains. + * + * \param chan the channel index 0 to N-1 + * \returns The normalized gain (in [0, 1]) + * \throws A uhd::runtime_error if the gain value is outside [0, 1]. + */ + virtual double get_normalized_tx_gain(size_t chan = 0) = 0; + + /*! * Get the TX gain range for the specified gain element. * For an empty name, calculate the overall gain range. * \param name the name of the gain element @@ -895,6 +974,38 @@ public: */ virtual boost::uint32_t get_gpio_attr(const std::string &bank, const std::string &attr, const size_t mboard = 0) = 0; + /******************************************************************* + * Filter API methods + ******************************************************************/ + + /*! + * Enumerate the available filters in the signal path. + * \param search_mask + * \parblock + * Select only certain filter names by specifying this search mask. + * + * E.g. if search mask is set to "rx_frontends/A" only filter names including that string will be returned. + * \endparblock + * \return a vector of strings representing the selected filter names. + */ + virtual std::vector<std::string> get_filter_names(const std::string &search_mask = "") = 0; + + /*! + * Return the filter object for the given name. + * \param path the name of the filter as returned from get_filter_names(). + * \return a filter_info_base::sptr. + */ + virtual filter_info_base::sptr get_filter(const std::string &path) = 0; + + /*! + * Write back a filter obtained by get_filter() to the signal path. + * This filter can be a modified version of the originally returned one. + * The information about Rx or Tx is contained in the path parameter. + * \param path the name of the filter as returned from get_filter_names(). + * \param filter the filter_info_base::sptr of the filter object to be written + */ + virtual void set_filter(const std::string &path, filter_info_base::sptr filter) = 0; + }; }} diff --git a/host/include/uhd/usrp_clock/CMakeLists.txt b/host/include/uhd/usrp_clock/CMakeLists.txt index 7cd5aa9d3..a116e4982 100644 --- a/host/include/uhd/usrp_clock/CMakeLists.txt +++ b/host/include/uhd/usrp_clock/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2014 Ettus Research LLC +# Copyright 2014-2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -18,6 +18,6 @@ UHD_INSTALL(FILES octoclock_eeprom.hpp multi_usrp_clock.hpp - DESTINATION ${INCLUDE_DIR}/uhd/octoclock + DESTINATION ${INCLUDE_DIR}/uhd/usrp_clock COMPONENT headers ) diff --git a/host/include/uhd/utils/math.hpp b/host/include/uhd/utils/math.hpp index 4f88494d6..46a1cf7e4 100644 --- a/host/include/uhd/utils/math.hpp +++ b/host/include/uhd/utils/math.hpp @@ -18,11 +18,11 @@ #ifndef INCLUDED_UHD_UTILS_MATH_HPP #define INCLUDED_UHD_UTILS_MATH_HPP +#include <cmath> #include <uhd/config.hpp> #include <boost/cstdint.hpp> #include <boost/numeric/conversion/bounds.hpp> - namespace uhd { /*! @@ -237,6 +237,16 @@ namespace fp_compare { == fp_compare::fp_compare_delta<double>(rhs, FREQ_COMPARISON_DELTA_HZ)); } + //! Portable log2() + template <typename float_t> UHD_INLINE + float_t log2(float_t x) + { + // C++11 defines std::log2(), when that's universally supported + // we can switch over. + return std::log(x) / std::log(float_t(2)); + } + + } // namespace math } // namespace uhd diff --git a/host/include/uhd/utils/paths.hpp b/host/include/uhd/utils/paths.hpp index 0dbee3446..cc054b019 100644 --- a/host/include/uhd/utils/paths.hpp +++ b/host/include/uhd/utils/paths.hpp @@ -87,7 +87,7 @@ namespace uhd { * The error string will include the full path to the utility to run. * \return the message suggesting the use of the named utility. */ - UHD_API std::string print_utility_error(std::string name); + UHD_API std::string print_utility_error(const std::string &name, const std::string &args=""); } //namespace uhd #endif /* INCLUDED_UHD_UTILS_PATHS_HPP */ diff --git a/host/include/uhd/utils/soft_register.hpp b/host/include/uhd/utils/soft_register.hpp new file mode 100644 index 000000000..d3537a618 --- /dev/null +++ b/host/include/uhd/utils/soft_register.hpp @@ -0,0 +1,312 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_UHD_UTILS_SOFT_REGISTER_HPP +#define INCLUDED_UHD_UTILS_SOFT_REGISTER_HPP + +#include <boost/cstdint.hpp> +#include <boost/noncopyable.hpp> +#include <uhd/types/wb_iface.hpp> +#include <uhd/exception.hpp> +#include <boost/thread/mutex.hpp> +#include <boost/thread/locks.hpp> + +#define UHD_DEFINE_SOFT_REG_FIELD(name, width, shift) \ + static const uhd::soft_reg_field_t name = (((shift & 0xFF) << 8) | (width & 0xFF)) + +namespace uhd { + +/* A register field is defined as a tuple of the mask and the shift. + * It can be used to make read-modify-write operations more convenient + * For efficiency reasons, it is recommended to always use a constant + * of this type because it will get optimized out by the compiler and + * will result in zero memory overhead + */ +typedef boost::uint32_t soft_reg_field_t; + +namespace soft_reg_field { + inline size_t width(const soft_reg_field_t field) { + return (field & 0xFF); + } + + inline size_t shift(const soft_reg_field_t field) { + return ((field >> 8) & 0xFF); + } + + template<typename data_t> + inline size_t mask(const soft_reg_field_t field) { + return ((static_cast<data_t>(1)<<width(field))-1)<<shift(field); + } +} + +/*! + * Soft register object that holds offset, soft-copy and the control iface. + * Methods give convenient field-level access to soft-copy and the ability + * to do read-modify-write operations. + */ +template<typename reg_data_t, bool readable, bool writeable> +class UHD_API soft_register_t : public boost::noncopyable { +public: + typedef boost::shared_ptr< soft_register_t<reg_data_t, readable, writeable> > sptr; + + /*! + * Generic constructor for all soft_register types + */ + soft_register_t(wb_iface::wb_addr_type wr_addr, wb_iface::wb_addr_type rd_addr): + _iface(NULL), _wr_addr(wr_addr), _rd_addr(rd_addr), _soft_copy(0) + {} + + /*! + * Constructor for read-only, write-only registers and read-write registers + * with rd_addr == wr_addr + */ + soft_register_t(wb_iface::wb_addr_type addr): + _iface(NULL), _wr_addr(addr), _rd_addr(addr), _soft_copy(0) + {} + + /*! + * Initialize the register when the underlying bus is usable. + * Can be optionally synced with hardware. + * NOTE: Memory management of the iface is up to the caller + */ + inline void initialize(wb_iface& iface, bool sync = false) + { + _iface = &iface; + + //Synchronize with hardware. For RW register, flush THEN refresh. + if (sync && writeable) flush(); + if (sync && readable) refresh(); + } + + /*! + * Update specified field in the soft-copy with the arg value. + * Performs a read-modify-write operation so all other field are preserved. + * NOTE: This does not write the value to hardware. + */ + inline void set(const soft_reg_field_t field, const reg_data_t value) + { + _soft_copy = (_soft_copy & ~soft_reg_field::mask<reg_data_t>(field)) | + ((value << soft_reg_field::shift(field)) & soft_reg_field::mask<reg_data_t>(field)); + } + + /*! + * Get the value of the specified field from the soft-copy. + * NOTE: This does not read anything from hardware. + */ + inline reg_data_t get(const soft_reg_field_t field) + { + return (_soft_copy & soft_reg_field::mask<reg_data_t>(field)) >> soft_reg_field::shift(field); + } + + /*! + * Write the contents of the soft-copy to hardware. + */ + inline void flush() + { + if (writeable && _iface) { + if (sizeof(reg_data_t) <= 2) { + _iface->poke16(_wr_addr, static_cast<boost::uint16_t>(_soft_copy)); + } else if (sizeof(reg_data_t) <= 4) { + _iface->poke32(_wr_addr, static_cast<boost::uint32_t>(_soft_copy)); + } else if (sizeof(reg_data_t) <= 8) { + _iface->poke64(_wr_addr, static_cast<boost::uint64_t>(_soft_copy)); + } else { + throw uhd::not_implemented_error("soft_register only supports up to 64 bits."); + } + } else { + throw uhd::not_implemented_error("soft_register is not writable."); + } + } + + /*! + * Read the contents of the register from hardware and update the soft copy. + */ + inline void refresh() + { + if (readable && _iface) { + if (sizeof(reg_data_t) <= 2) { + _soft_copy = static_cast<reg_data_t>(_iface->peek16(_rd_addr)); + } else if (sizeof(reg_data_t) <= 4) { + _soft_copy = static_cast<reg_data_t>(_iface->peek32(_rd_addr)); + } else if (sizeof(reg_data_t) <= 8) { + _soft_copy = static_cast<reg_data_t>(_iface->peek64(_rd_addr)); + } else { + throw uhd::not_implemented_error("soft_register only supports up to 64 bits."); + } + } else { + throw uhd::not_implemented_error("soft_register is not readable."); + } + } + + /*! + * Shortcut for a set and a flush. + */ + inline void write(const soft_reg_field_t field, const reg_data_t value) + { + set(field, value); + flush(); + } + + /*! + * Shortcut for refresh and get + */ + inline reg_data_t read(const soft_reg_field_t field) + { + refresh(); + return get(field); + } + +private: + wb_iface* _iface; + const wb_iface::wb_addr_type _wr_addr; + const wb_iface::wb_addr_type _rd_addr; + reg_data_t _soft_copy; +}; + +/*! + * A synchronized soft register object. + * All operations in the synchronized register are serialized. + */ +template<typename reg_data_t, bool readable, bool writeable> +class UHD_API soft_register_sync_t : public soft_register_t<reg_data_t, readable, writeable> { +public: + typedef boost::shared_ptr< soft_register_sync_t<reg_data_t, readable, writeable> > sptr; + + soft_register_sync_t(wb_iface::wb_addr_type wr_addr, wb_iface::wb_addr_type rd_addr): + soft_register_t<reg_data_t, readable, writeable>(wr_addr, rd_addr), _mutex() + {} + + soft_register_sync_t(wb_iface::wb_addr_type addr): + soft_register_t<reg_data_t, readable, writeable>(addr), _mutex() + {} + + inline void initialize(wb_iface& iface, bool sync = false) + { + boost::lock_guard<boost::mutex> lock(_mutex); + soft_register_t<reg_data_t, readable, writeable>::initialize(iface, sync); + } + + inline void set(const soft_reg_field_t field, const reg_data_t value) + { + boost::lock_guard<boost::mutex> lock(_mutex); + soft_register_t<reg_data_t, readable, writeable>::set(field, value); + } + + inline reg_data_t get(const soft_reg_field_t field) + { + boost::lock_guard<boost::mutex> lock(_mutex); + return soft_register_t<reg_data_t, readable, writeable>::get(field); + } + + inline void flush() + { + boost::lock_guard<boost::mutex> lock(_mutex); + soft_register_t<reg_data_t, readable, writeable>::flush(); + } + + inline void refresh() + { + boost::lock_guard<boost::mutex> lock(_mutex); + soft_register_t<reg_data_t, readable, writeable>::refresh(); + } + + inline void write(const soft_reg_field_t field, const reg_data_t value) + { + boost::lock_guard<boost::mutex> lock(_mutex); + soft_register_t<reg_data_t, readable, writeable>::write(field, value); + } + + inline reg_data_t read(const soft_reg_field_t field) + { + boost::lock_guard<boost::mutex> lock(_mutex); + return soft_register_t<reg_data_t, readable, writeable>::read(field); + } + +private: + boost::mutex _mutex; +}; + +/* + * Register Shortcut Formats: + * - soft_reg<bits>_<mode>_t: Soft register object with an unsynchronized soft-copy. + * Thread unsafe but lightweight. Mostly const propagated. + * - soft_reg<bits>_<mode>_sync_t: Soft register object with a synchronized soft-copy. + * Thread safe but with memory/speed overhead. + * where: + * - <bits> = {16, 32 or 64} + * - <mode> = {wo(write-only), rw(read-write) or ro(read-only)} + * + */ + +//16-bit shortcuts +typedef soft_register_t<boost::uint16_t, false, true> soft_reg16_wo_t; +typedef soft_register_t<boost::uint16_t, true, false> soft_reg16_ro_t; +typedef soft_register_t<boost::uint16_t, true, true> soft_reg16_rw_t; +typedef soft_register_sync_t<boost::uint16_t, false, true> soft_reg16_wo_sync_t; +typedef soft_register_sync_t<boost::uint16_t, true, false> soft_reg16_ro_sync_t; +typedef soft_register_sync_t<boost::uint16_t, true, true> soft_reg16_rw_sync_t; +//32-bit shortcuts +typedef soft_register_t<boost::uint32_t, false, true> soft_reg32_wo_t; +typedef soft_register_t<boost::uint32_t, true, false> soft_reg32_ro_t; +typedef soft_register_t<boost::uint32_t, true, true> soft_reg32_rw_t; +typedef soft_register_sync_t<boost::uint32_t, false, true> soft_reg32_wo_sync_t; +typedef soft_register_sync_t<boost::uint32_t, true, false> soft_reg32_ro_sync_t; +typedef soft_register_sync_t<boost::uint32_t, true, true> soft_reg32_rw_sync_t; +//64-bit shortcuts +typedef soft_register_t<boost::uint64_t, false, true> soft_reg64_wo_t; +typedef soft_register_t<boost::uint64_t, true, false> soft_reg64_ro_t; +typedef soft_register_t<boost::uint64_t, true, true> soft_reg64_rw_t; +typedef soft_register_sync_t<boost::uint64_t, false, true> soft_reg64_wo_sync_t; +typedef soft_register_sync_t<boost::uint64_t, true, false> soft_reg64_ro_sync_t; +typedef soft_register_sync_t<boost::uint64_t, true, true> soft_reg64_rw_sync_t; + + +/* + * Usage example + * + //===Define bit width, RW mode, and synchronization using base class=== + class example_reg_t : public soft_reg32_wo_sync_t (or soft_reg32_wo_t) { + public: + //===Define all the fields=== + UHD_DEFINE_SOFT_REG_FIELD(FIELD0, 1, 0); //[0] + UHD_DEFINE_SOFT_REG_FIELD(FIELD1, 15, 1); //[15:1] + UHD_DEFINE_SOFT_REG_FIELD(FIELD2, 16, 16); //[31:16] + + example_reg_t(): //ctor with no args + soft_reg32_wo_t(SR_CORE_EXAMPLE_REG_OFFSET)) //===Bind to offset=== + { + //===Set Initial values=== + set(FIELD0, 0); + set(FIELD1, 1); + set(FIELD2, 0xFFFF); + } + }; //===Full register definition encapsulated in one class=== + + void main() { + example_reg_t reg_obj; + reg_obj.initialize(iface); + reg_obj.write(example_reg_t::FIELD2, 0x1234); + + example_reg_t::sptr reg_sptr = boost::make_shared<example_reg_t>(); + reg_obj->initialize(iface); + reg_obj->write(example_reg_t::FIELD2, 0x1234); + } +*/ + +} //namespace uhd + +#endif /* INCLUDED_UHD_UTILS_SOFT_REGISTER_HPP */ diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index d8c6fad70..3fa8ed22f 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -103,8 +103,24 @@ IF(MSVC) IF(UHD_VERSION_DEVEL) SET(RC_TRIMMED_VERSION_PATCH "999") ENDIF(UHD_VERSION_DEVEL) + + # Allow a custom .rc template file to be used + IF(CUSTOM_RC_FILE) + IF(IS_ABSOLUTE "${CUSTOM_RC_FILE}") + SET(UHD_RC_IN "${CUSTOM_RC_FILE}") + ELSE() + SET(UHD_RC_IN "${CMAKE_BINARY_DIR}/${CUSTOM_RC_FILE}") + ENDIF(IS_ABSOLUTE "${CUSTOM_RC_FILE}") + MESSAGE(STATUS "") + MESSAGE(STATUS "Using custom RC template: ${UHD_RC_IN}") + MESSAGE(STATUS "") + ELSE() + SET(UHD_RC_IN "${CMAKE_CURRENT_SOURCE_DIR}/uhd.rc.in") + ENDIF(CUSTOM_RC_FILE) + SET(UHD_RC_IN ${UHD_RC_IN} CACHE STRING "uhd.rc template filepath") + CONFIGURE_FILE( - ${CMAKE_CURRENT_SOURCE_DIR}/uhd.rc.in + ${UHD_RC_IN} ${CMAKE_CURRENT_BINARY_DIR}/uhd.rc @ONLY) diff --git a/host/lib/convert/CMakeLists.txt b/host/lib/convert/CMakeLists.txt index 5204c29ea..024c2260b 100644 --- a/host/lib/convert/CMakeLists.txt +++ b/host/lib/convert/CMakeLists.txt @@ -22,40 +22,6 @@ INCLUDE(CheckIncludeFileCXX) MESSAGE(STATUS "") ######################################################################## -# Look for Orc support -######################################################################## -FIND_PACKAGE(ORC) - -IF(NOT ORCC_EXECUTABLE) - FIND_PROGRAM(ORCC_EXECUTABLE orcc) -ENDIF() - -LIBUHD_REGISTER_COMPONENT("ORC" ENABLE_ORC ON "ENABLE_LIBUHD;ORC_FOUND;ORCC_EXECUTABLE" OFF) - -IF(ENABLE_ORC) - INCLUDE_DIRECTORIES(${ORC_INCLUDE_DIRS}) - LINK_DIRECTORIES(${ORC_LIBRARY_DIRS}) - ENABLE_LANGUAGE(C) - - SET(orcc_src ${CMAKE_CURRENT_SOURCE_DIR}/convert_orc.orc) - - GET_FILENAME_COMPONENT(orc_file_name_we ${orcc_src} NAME_WE) - SET(orcc_gen ${CMAKE_CURRENT_BINARY_DIR}/${orc_file_name_we}.c) - MESSAGE(STATUS "Orc found, enabling Orc support.") - ADD_CUSTOM_COMMAND( - COMMAND ${ORCC_EXECUTABLE} --implementation -o ${orcc_gen} ${orcc_src} - DEPENDS ${orcc_src} OUTPUT ${orcc_gen} - ) - LIBUHD_APPEND_SOURCES(${orcc_gen}) - LIBUHD_APPEND_SOURCES( - ${CMAKE_CURRENT_SOURCE_DIR}/convert_with_orc.cpp - ) - LIBUHD_APPEND_LIBS(${ORC_LIBRARIES}) -ELSE(ENABLE_ORC) - MESSAGE(STATUS "Orc not found, disabling orc support.") -ENDIF(ENABLE_ORC) - -######################################################################## # Check for SSE2 SIMD headers ######################################################################## IF(CMAKE_COMPILER_IS_GNUCXX) diff --git a/host/lib/convert/convert_common.hpp b/host/lib/convert/convert_common.hpp index 6c2ea9fec..65fdcbea2 100644 --- a/host/lib/convert/convert_common.hpp +++ b/host/lib/convert/convert_common.hpp @@ -65,11 +65,10 @@ static const int PRIORITY_GENERAL = 0; static const int PRIORITY_EMPTY = -1; #ifdef __ARM_NEON__ -static const int PRIORITY_LIBORC = 3; -static const int PRIORITY_SIMD = 2; //neon conversions could be implemented better, orc wins +static const int PRIORITY_SIMD = 2; static const int PRIORITY_TABLE = 1; //tables require large cache, so they are slower on arm #else -static const int PRIORITY_LIBORC = 2; +// We used to have ORC, too, so SIMD is 3 static const int PRIORITY_SIMD = 3; static const int PRIORITY_TABLE = 1; #endif diff --git a/host/lib/convert/convert_impl.cpp b/host/lib/convert/convert_impl.cpp index 329e94a4d..fd6c8497e 100644 --- a/host/lib/convert/convert_impl.cpp +++ b/host/lib/convert/convert_impl.cpp @@ -43,10 +43,10 @@ bool convert::operator==(const convert::id_type &lhs, const convert::id_type &rh std::string convert::id_type::to_pp_string(void) const{ return str(boost::format( "conversion ID\n" - " Input format: %s\n" - " Num inputs: %d\n" + " Input format: %s\n" + " Num inputs: %d\n" " Output format: %s\n" - " Num outputs: %d\n" + " Num outputs: %d\n" ) % this->input_format % this->num_inputs @@ -55,6 +55,15 @@ std::string convert::id_type::to_pp_string(void) const{ ); } +std::string convert::id_type::to_string(void) const{ + return str(boost::format("%s (%d) -> %s (%d)") + % this->input_format + % this->num_inputs + % this->output_format + % this->num_outputs + ); +} + /*********************************************************************** * Setup the table registry **********************************************************************/ @@ -92,7 +101,15 @@ convert::function_type convert::get_converter( //find a matching priority priority_type best_prio = -1; BOOST_FOREACH(priority_type prio_i, get_table()[id].keys()){ - if (prio_i == prio) return get_table()[id][prio]; + if (prio_i == prio) { + //----------------------------------------------------------------// + UHD_LOGV(always) << "get_converter: For converter ID: " << id.to_pp_string() << std::endl + << "Using prio: " << prio << std::endl + << std::endl + ; + //----------------------------------------------------------------// + return get_table()[id][prio]; + } best_prio = std::max(best_prio, prio_i); } @@ -100,6 +117,13 @@ convert::function_type convert::get_converter( if (prio != -1) throw uhd::key_error( "Cannot find a conversion routine [with prio] for " + id.to_pp_string()); + //----------------------------------------------------------------// + UHD_LOGV(always) << "get_converter: For converter ID: " << id.to_pp_string() << std::endl + << "Using prio: " << best_prio << std::endl + << std::endl + ; + //----------------------------------------------------------------// + //otherwise, return best prio return get_table()[id][best_prio]; } diff --git a/host/lib/convert/convert_orc.orc b/host/lib/convert/convert_orc.orc deleted file mode 100644 index ffb298f26..000000000 --- a/host/lib/convert/convert_orc.orc +++ /dev/null @@ -1,79 +0,0 @@ -.function _convert_fc32_1_to_item32_1_nswap_orc -.source 8 src -.dest 4 dst -.floatparam 4 scalar -.temp 8 scaled -.temp 8 converted -.temp 4 short -x2 mulf scaled, src, scalar -x2 convfl converted, scaled -x2 convlw short, converted -swapl short, short -x2 swapw dst, short - -.function _convert_fc32_1_to_item32_1_bswap_orc -.source 8 src -.dest 4 dst -.floatparam 4 scalar -.temp 8 scaled -.temp 8 converted -.temp 4 short -x2 mulf scaled, src, scalar -x2 convfl converted, scaled -x2 convlw short, converted -x2 swapw dst, short - -.function _convert_item32_1_to_fc32_1_nswap_orc -.source 4 src -.dest 8 dst -.floatparam 4 scalar -.temp 4 tmp1 -.temp 8 tmp2 -x2 swapw tmp1, src -swapl tmp1, tmp1 -x2 convswl tmp2, tmp1 -x2 convlf tmp2, tmp2 -x2 mulf dst, tmp2, scalar - -.function _convert_item32_1_to_fc32_1_bswap_orc -.source 4 src -.dest 8 dst -.floatparam 4 scalar -.temp 4 tmp1 -.temp 8 tmp2 -x2 swapw tmp1, src -x2 convswl tmp2, tmp1 -x2 convlf tmp2, tmp2 -x2 mulf dst, tmp2, scalar - -.function _convert_sc16_1_to_item32_1_nswap_orc -.source 4 src -.dest 4 dst -.temp 4 tmp -.floatparam 4 scalar -swapl tmp, src -x2 swapw dst, tmp - -.function _convert_item32_1_to_sc16_1_nswap_orc -.source 4 src -.dest 4 dst -.floatparam 4 scalar -.temp 4 tmp -x2 swapw tmp, src -swapl dst, tmp - -.function _convert_swap_byte_pairs_orc -.source 4 src -.dest 4 dst -swapl dst, src - -.function _convert_fc32_1_to_sc8_1_nswap_orc -.source 8 src -.dest 2 dst -.temp 8 tmp -.temp 4 tmp2 -.floatparam 4 scalar -x2 mulf tmp, src, scalar -x2 convfl tmp, tmp -x2 convlw tmp2, tmp -x2 convwb dst, tmp2 diff --git a/host/lib/convert/convert_with_orc.cpp b/host/lib/convert/convert_with_orc.cpp deleted file mode 100644 index 19755fa44..000000000 --- a/host/lib/convert/convert_with_orc.cpp +++ /dev/null @@ -1,65 +0,0 @@ -// -// Copyright 2011-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -#include "convert_common.hpp" -#include <uhd/utils/byteswap.hpp> - -using namespace uhd::convert; - -extern "C" { -extern void _convert_fc32_1_to_item32_1_nswap_orc(void *, const void *, float, int); -extern void _convert_fc32_1_to_item32_1_bswap_orc(void *, const void *, float, int); -extern void _convert_item32_1_to_fc32_1_nswap_orc(void *, const void *, float, int); -extern void _convert_item32_1_to_fc32_1_bswap_orc(void *, const void *, float, int); -extern void _convert_sc16_1_to_item32_1_nswap_orc(void *, const void *, float, int); -extern void _convert_item32_1_to_sc16_1_nswap_orc(void *, const void *, float, int); -extern void _convert_fc32_1_to_sc8_1_nswap_orc(void *, const void *, float, int); -extern void _convert_swap_byte_pairs_orc(void *, const void *, int); -} - -DECLARE_CONVERTER(fc32, 1, sc16_item32_le, 1, PRIORITY_LIBORC){ - _convert_fc32_1_to_item32_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); -} - -DECLARE_CONVERTER(fc32, 1, sc16_item32_be, 1, PRIORITY_LIBORC){ - _convert_fc32_1_to_item32_1_bswap_orc(outputs[0], inputs[0], scale_factor, nsamps); -} - -DECLARE_CONVERTER(sc16_item32_le, 1, fc32, 1, PRIORITY_LIBORC){ - _convert_item32_1_to_fc32_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); -} - -DECLARE_CONVERTER(sc16_item32_be, 1, fc32, 1, PRIORITY_LIBORC){ - _convert_item32_1_to_fc32_1_bswap_orc(outputs[0], inputs[0], scale_factor, nsamps); -} - -DECLARE_CONVERTER(sc16, 1, sc16_item32_le, 1, PRIORITY_LIBORC){ - _convert_sc16_1_to_item32_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); -} - -DECLARE_CONVERTER(sc16_item32_le, 1, sc16, 1, PRIORITY_LIBORC){ - _convert_item32_1_to_sc16_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); -} - -DECLARE_CONVERTER(fc32, 1, sc8_item32_be, 1, PRIORITY_LIBORC){ - _convert_fc32_1_to_sc8_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); -} - -DECLARE_CONVERTER(fc32, 1, sc8_item32_le, 1, PRIORITY_LIBORC){ - _convert_fc32_1_to_sc8_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); - _convert_swap_byte_pairs_orc(outputs[0], outputs[0], (nsamps + 1)/2); -} diff --git a/host/lib/convert/gen_convert_general.py b/host/lib/convert/gen_convert_general.py index b0790755a..8090f14bd 100644 --- a/host/lib/convert/gen_convert_general.py +++ b/host/lib/convert/gen_convert_general.py @@ -17,92 +17,94 @@ # TMPL_HEADER = """ -#import time +<% + import time +%> /*********************************************************************** - * This file was generated by $file on $time.strftime("%c") + * This file was generated by ${file} on ${time.strftime("%c")} **********************************************************************/ -\#include "convert_common.hpp" -\#include <uhd/utils/byteswap.hpp> +#include "convert_common.hpp" +#include <uhd/utils/byteswap.hpp> using namespace uhd::convert; """ TMPL_CONV_GEN2_ITEM32 = """ -DECLARE_CONVERTER(item32, 1, sc16_item32_$(end), 1, PRIORITY_GENERAL){ +DECLARE_CONVERTER(item32, 1, sc16_item32_${end}, 1, PRIORITY_GENERAL){ const item32_t *input = reinterpret_cast<const item32_t *>(inputs[0]); item32_t *output = reinterpret_cast<item32_t *>(outputs[0]); for (size_t i = 0; i < nsamps; i++){ - output[i] = $(to_wire)(input[i]); + output[i] = ${to_wire}(input[i]); } } -DECLARE_CONVERTER(sc16_item32_$(end), 1, item32, 1, PRIORITY_GENERAL){ +DECLARE_CONVERTER(sc16_item32_${end}, 1, item32, 1, PRIORITY_GENERAL){ const item32_t *input = reinterpret_cast<const item32_t *>(inputs[0]); item32_t *output = reinterpret_cast<item32_t *>(outputs[0]); for (size_t i = 0; i < nsamps; i++){ - output[i] = $(to_host)(input[i]); + output[i] = ${to_host}(input[i]); } } """ TMPL_CONV_USRP1_COMPLEX = """ -DECLARE_CONVERTER($(cpu_type), $(width), sc16_item16_usrp1, 1, PRIORITY_GENERAL){ - #for $w in range($width) - const $(cpu_type)_t *input$(w) = reinterpret_cast<const $(cpu_type)_t *>(inputs[$(w)]); - #end for +DECLARE_CONVERTER(${cpu_type}, ${width}, sc16_item16_usrp1, 1, PRIORITY_GENERAL){ + % for w in range(width): + const ${cpu_type}_t *input${w} = reinterpret_cast<const ${cpu_type}_t *>(inputs[${w}]); + % endfor boost::uint16_t *output = reinterpret_cast<boost::uint16_t *>(outputs[0]); for (size_t i = 0, j = 0; i < nsamps; i++){ - #for $w in range($width) - output[j++] = $(to_wire)(boost::uint16_t(boost::int16_t(input$(w)[i].real()$(do_scale)))); - output[j++] = $(to_wire)(boost::uint16_t(boost::int16_t(input$(w)[i].imag()$(do_scale)))); - #end for + % for w in range(width): + output[j++] = ${to_wire}(boost::uint16_t(boost::int16_t(input${w}[i].real()${do_scale}))); + output[j++] = ${to_wire}(boost::uint16_t(boost::int16_t(input${w}[i].imag()${do_scale}))); + % endfor } } -DECLARE_CONVERTER(sc16_item16_usrp1, 1, $(cpu_type), $(width), PRIORITY_GENERAL){ +DECLARE_CONVERTER(sc16_item16_usrp1, 1, ${cpu_type}, ${width}, PRIORITY_GENERAL){ const boost::uint16_t *input = reinterpret_cast<const boost::uint16_t *>(inputs[0]); - #for $w in range($width) - $(cpu_type)_t *output$(w) = reinterpret_cast<$(cpu_type)_t *>(outputs[$(w)]); - #end for + % for w in range(width): + ${cpu_type}_t *output${w} = reinterpret_cast<${cpu_type}_t *>(outputs[${w}]); + % endfor for (size_t i = 0, j = 0; i < nsamps; i++){ - #for $w in range($width) - output$(w)[i] = $(cpu_type)_t( - boost::int16_t($(to_host)(input[j+0]))$(do_scale), - boost::int16_t($(to_host)(input[j+1]))$(do_scale) + % for w in range(width): + output${w}[i] = ${cpu_type}_t( + boost::int16_t(${to_host}(input[j+0]))${do_scale}, + boost::int16_t(${to_host}(input[j+1]))${do_scale} ); j += 2; - #end for + % endfor } } -DECLARE_CONVERTER(sc8_item16_usrp1, 1, $(cpu_type), $(width), PRIORITY_GENERAL){ +DECLARE_CONVERTER(sc8_item16_usrp1, 1, ${cpu_type}, ${width}, PRIORITY_GENERAL){ const boost::uint16_t *input = reinterpret_cast<const boost::uint16_t *>(inputs[0]); - #for $w in range($width) - $(cpu_type)_t *output$(w) = reinterpret_cast<$(cpu_type)_t *>(outputs[$(w)]); - #end for + % for w in range(width): + ${cpu_type}_t *output${w} = reinterpret_cast<${cpu_type}_t *>(outputs[${w}]); + % endfor for (size_t i = 0, j = 0; i < nsamps; i++){ - #for $w in range($width) + % for w in range(width): { - const boost::uint16_t num = $(to_host)(input[j++]); - output$(w)[i] = $(cpu_type)_t( - boost::int8_t(num)$(do_scale), - boost::int8_t(num >> 8)$(do_scale) + const boost::uint16_t num = ${to_host}(input[j++]); + output${w}[i] = ${cpu_type}_t( + boost::int8_t(num)${do_scale}, + boost::int8_t(num >> 8)${do_scale} ); } - #end for + % endfor } } """ def parse_tmpl(_tmpl_text, **kwargs): - from Cheetah.Template import Template - return str(Template(_tmpl_text, kwargs)) + from mako.template import Template + return Template(_tmpl_text).render(**kwargs) if __name__ == '__main__': import sys, os diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py index 24f5bf8be..5c0cfc109 100644..100755 --- a/host/lib/ic_reg_maps/common.py +++ b/host/lib/ic_reg_maps/common.py @@ -1,5 +1,5 @@ # -# Copyright 2010-2011 Ettus Research LLC +# Copyright 2010-2011,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -18,105 +18,99 @@ import re import sys import math -from Cheetah.Template import Template +from mako.template import Template -COMMON_TMPL = """\ -#import time +COMMON_TMPL = """<% import time %>\ /*********************************************************************** - * This file was generated by $file on $time.strftime("%c") + * This file was generated by ${file} on ${time.strftime("%c")} **********************************************************************/ -\#ifndef INCLUDED_$(name.upper())_HPP -\#define INCLUDED_$(name.upper())_HPP +#ifndef INCLUDED_${name.upper()}_HPP +#define INCLUDED_${name.upper()}_HPP -\#include <uhd/config.hpp> -\#include <uhd/exception.hpp> -\#include <boost/cstdint.hpp> -\#include <set> +#include <uhd/config.hpp> +#include <uhd/exception.hpp> +#include <boost/cstdint.hpp> +#include <set> -class $(name)_t{ +class ${name}_t{ public: - #for $reg in $regs - #if $reg.get_enums() - enum $reg.get_type(){ - #for $i, $enum in enumerate($reg.get_enums()) - #set $end_comma = ',' if $i < len($reg.get_enums())-1 else '' - $(reg.get_name().upper())_$(enum[0].upper()) = $enum[1]$end_comma - #end for + % for reg in regs: + % if reg.get_enums(): + enum ${reg.get_type()}{ + % for i,enum in enumerate(reg.get_enums()): + ${reg.get_name().upper()}_${enum[0].upper()} = ${enum[1]}<% comma = ',' if i != (len(reg.get_enums())-1) else '' %>${comma} + % endfor }; - #end if - $reg.get_type() $reg.get_name(); - #end for + % endif + ${reg.get_type()} ${reg.get_name()}; + % endfor - $(name)_t(void){ + ${name}_t(void){ _state = NULL; - #for $reg in $regs - $reg.get_name() = $reg.get_default(); - #end for + % for reg in regs: + ${reg.get_name()} = ${reg.get_default()}; + % endfor } - ~$(name)_t(void){ + ~${name}_t(void){ delete _state; } - $body + ${body} void save_state(void){ - if (_state == NULL) _state = new $(name)_t(); - #for $reg in $regs - _state->$reg.get_name() = this->$reg.get_name(); - #end for + if (_state == NULL) _state = new ${name}_t(); + % for reg in regs: + _state->${reg.get_name()} = this->${reg.get_name()}; + % endfor } template<typename T> std::set<T> get_changed_addrs(void){ if (_state == NULL) throw uhd::runtime_error("no saved state"); //check each register for changes std::set<T> addrs; - #for $reg in $regs - if(_state->$reg.get_name() != this->$reg.get_name()){ - addrs.insert($reg.get_addr()); + % for reg in regs: + if(_state->${reg.get_name()} != this->${reg.get_name()}){ + addrs.insert(${reg.get_addr()}); } - #end for + % endfor return addrs; } - #for $mreg in $mregs - $mreg.get_type() get_$(mreg.get_name())(void){ - return - #set $shift = 0 - #for $reg in $mreg.get_regs() - ($(mreg.get_type())($reg.get_name() & $reg.get_mask()) << $shift) | - #set $shift = $shift + $reg.get_bit_width() - #end for + % for mreg in mregs: + ${mreg.get_type()} get_${mreg.get_name()}(void){ + return <% shift = 0 %> + % for reg in mreg.get_regs(): + (${mreg.get_type()}(${reg.get_name()} & ${reg.get_mask()}) << ${shift}) |<% shift = shift + reg.get_bit_width() %> + % endfor 0; } - void set_$(mreg.get_name())($mreg.get_type() reg){ - #set $shift = 0 - #for $reg in $mreg.get_regs() - $reg.get_name() = (reg >> $shift) & $reg.get_mask(); - #set $shift = $shift + $reg.get_bit_width() - #end for + void set_${mreg.get_name()}(${mreg.get_type()} reg){<% shift = 0 %> + % for reg in mreg.get_regs(): + ${reg.get_name()} = (reg >> ${shift}) & ${reg.get_mask()};<% shift = shift + reg.get_bit_width() %> + % endfor } - #end for + % endfor private: - $(name)_t *_state; + ${name}_t *_state; }; -\#endif /* INCLUDED_$(name.upper())_HPP */ +#endif /* INCLUDED_${name.upper()}_HPP */ """ def parse_tmpl(_tmpl_text, **kwargs): - return str(Template(_tmpl_text, kwargs)) + return Template(_tmpl_text).render(**kwargs) def to_num(arg): return int(eval(arg)) class reg: def __init__(self, reg_des): try: self.parse(reg_des) - except Exception, e: - raise Exception, 'Error parsing register description: "%s"\nWhat: %s'%(reg_des, e) + except Exception as e: + raise Exception('Error parsing register description: "%s"\nWhat: %s'%(reg_des, e)) def parse(self, reg_des): x = re.match('^(\w*)\s*(\w*)\[(.*)\]\s*(\w*)\s*(.*)$', reg_des) @@ -133,7 +127,8 @@ class reg: self._enums = list() if enums: enum_val = 0 - for enum_str in map(str.strip, enums.split(',')): + for enum_str_unstripped in enums.split(','): + enum_str = enum_str_unstripped.strip() if '=' in enum_str: enum_name, enum_val = enum_str.split('=') enum_val = to_num(enum_val) @@ -146,7 +141,7 @@ class reg: def get_name(self): return self._name def get_default(self): for key, val in self.get_enums(): - if val == self._default: return str.upper('%s_%s'%(self.get_name(), key)) + if val == self._default: return ('%s_%s'%(self.get_name(), key)).upper() return self._default def get_type(self): if self.get_enums(): return '%s_t'%self.get_name() @@ -158,14 +153,14 @@ class reg: class mreg: def __init__(self, mreg_des, regs): try: self.parse(mreg_des, regs) - except Exception, e: - raise Exception, 'Error parsing meta register description: "%s"\nWhat: %s'%(mreg_des, e) + except Exception as e: + raise Exception('Error parsing meta register description: "%s"\nWhat: %s'%(mreg_des, e)) def parse(self, mreg_des, regs): x = re.match('^~(\w*)\s+(.*)\s*$', mreg_des) self._name, reg_names = x.groups() regs_dict = dict([(reg.get_name(), reg) for reg in regs]) - self._regs = [regs_dict[reg_name] for reg_name in map(str.strip, reg_names.split(','))] + self._regs = [regs_dict[reg_name.strip()] for reg_name in reg_names.split(',')] def get_name(self): return self._name def get_regs(self): return self._regs diff --git a/host/lib/ic_reg_maps/gen_ad5623_regs.py b/host/lib/ic_reg_maps/gen_ad5623_regs.py index e653921ba..8b70a9f0a 100755 --- a/host/lib/ic_reg_maps/gen_ad5623_regs.py +++ b/host/lib/ic_reg_maps/gen_ad5623_regs.py @@ -32,9 +32,9 @@ cmd 0[19:21] 0 wr_input_n, up_dac_n, wr_input_n_up_a BODY_TMPL="""\ boost::uint32_t get_reg(void){ boost::uint32_t reg = 0; - #for $reg in filter(lambda r: r.get_addr() == 0, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for reg in filter(lambda r: r.get_addr() == 0, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor return reg; } """ diff --git a/host/lib/ic_reg_maps/gen_ad7922_regs.py b/host/lib/ic_reg_maps/gen_ad7922_regs.py index 5cec1924a..c77991182 100755 --- a/host/lib/ic_reg_maps/gen_ad7922_regs.py +++ b/host/lib/ic_reg_maps/gen_ad7922_regs.py @@ -32,16 +32,16 @@ chn 0[13] 0 BODY_TMPL="""\ boost::uint16_t get_reg(void){ boost::uint16_t reg = 0; - #for $reg in filter(lambda r: r.get_addr() == 0, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for reg in filter(lambda r: r.get_addr() == 0, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor return reg; } void set_reg(boost::uint16_t reg){ - #for $reg in filter(lambda r: r.get_addr() == 0, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for reg in filter(lambda r: r.get_addr() == 0, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor } """ diff --git a/host/lib/ic_reg_maps/gen_ad9510_regs.py b/host/lib/ic_reg_maps/gen_ad9510_regs.py index 6c1e612cc..9f194b5c9 100755 --- a/host/lib/ic_reg_maps/gen_ad9510_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9510_regs.py @@ -54,25 +54,25 @@ lock_detect_disable 0xD[6] 0 enb, dis ######################################################################## ## fine delay adjust ######################################################################## -#for $i, $o in ((5, 0), (6, 4)) -delay_control_out$i $hex(0x34+$o)[0] 0 -ramp_current_out$i $hex(0x35+$o)[0:2] 0 200ua, 400ua, 600ua, 800ua, 1000ua, 1200ua, 1400ua, 1600ua -ramp_capacitor_out$i $hex(0x35+$o)[3:5] 0 4caps=0, 3caps=1, 2caps=3, 1cap=7 -delay_fine_adjust_out$i $hex(0x36+$o)[1:5] 0 -#end for +% for i, o in ((5, 0), (6, 4)): +delay_control_out${i} ${hex(0x34+o)}[0] 0 +ramp_current_out${i} ${hex(0x35+o)}[0:2] 0 200ua, 400ua, 600ua, 800ua, 1000ua, 1200ua, 1400ua, 1600ua +ramp_capacitor_out${i} ${hex(0x35+o)}[3:5] 0 4caps=0, 3caps=1, 2caps=3, 1cap=7 +delay_fine_adjust_out${i} ${hex(0x36+o)}[1:5] 0 +% endfor ######################################################################## ## outputs ######################################################################## -#for $i, $o in ((0, 0), (1, 1), (2, 2), (3, 3)) -power_down_lvpecl_out$i $hex(0x3C+$o)[0:1] 0 normal, test, safe_pd, total_pd -output_level_lvpecl_out$i $hex(0x3C+$o)[2:3] 2 500mv, 340mv, 810mv, 660mv -#end for -#for $i, $o in ((4, 0), (5, 1), (6, 2), (7, 3)) -power_down_lvds_cmos_out$i $hex(0x40+$o)[0] 0 -output_level_lvds_out$i $hex(0x40+$o)[1:2] 1 1_75ma, 3_5ma, 5_25ma, 7ma -lvds_cmos_select_out$i $hex(0x40+$o)[3] 1 lvds, cmos -inverted_cmos_driver_out$i $hex(0x40+$o)[4] 0 dis, enb -#end for +% for i, o in ((0, 0), (1, 1), (2, 2), (3, 3)): +power_down_lvpecl_out${i} ${hex(0x3C+o)}[0:1] 0 normal, test, safe_pd, total_pd +output_level_lvpecl_out${i} ${hex(0x3C+o)}[2:3] 2 500mv, 340mv, 810mv, 660mv +% endfor +% for i, o in ((4, 0), (5, 1), (6, 2), (7, 3)): +power_down_lvds_cmos_out${i} ${hex(0x40+o)}[0] 0 +output_level_lvds_out${i} ${hex(0x40+o)}[1:2] 1 1_75ma, 3_5ma, 5_25ma, 7ma +lvds_cmos_select_out${i} ${hex(0x40+o)}[3] 1 lvds, cmos +inverted_cmos_driver_out${i} ${hex(0x40+o)}[4] 0 dis, enb +% endfor clock_select 0x45[0] 1 clk2_drives, clk1_drives clk1_power_down 0x45[1] 0 clk2_power_down 0x45[2] 0 @@ -82,15 +82,15 @@ all_clock_inputs_pd 0x45[5] 0 ######################################################################## ## dividers ######################################################################## -#for $i, $o in ((0, 0), (1, 2), (2, 4), (3, 6), (4, 8), (5, 10), (6, 12), (7, 14)) -divider_high_cycles_out$i $hex(0x48+$o)[0:3] 0 -divider_low_cycles_out$i $hex(0x48+$o)[4:7] 0 -phase_offset_out$i $hex(0x49+$o)[0:3] 0 -start_out$i $hex(0x49+$o)[4] 0 -force_out$i $hex(0x49+$o)[5] 0 -nosync_out$i $hex(0x49+$o)[6] 0 -bypass_divider_out$i $hex(0x49+$o)[7] 0 -#end for +% for i, o in ((0, 0), (1, 2), (2, 4), (3, 6), (4, 8), (5, 10), (6, 12), (7, 14)): +divider_high_cycles_out${i} ${hex(0x48+o)}[0:3] 0 +divider_low_cycles_out${i} ${hex(0x48+o)}[4:7] 0 +phase_offset_out${i} ${hex(0x49+o)}[0:3] 0 +start_out${i} ${hex(0x49+o)}[4] 0 +force_out${i} ${hex(0x49+o)}[5] 0 +nosync_out${i} ${hex(0x49+o)}[6] 0 +bypass_divider_out${i} ${hex(0x49+o)}[7] 0 +% endfor ######################################################################## ## function ######################################################################## @@ -110,13 +110,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint16_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py index 1512da811..cc906b76c 100755 --- a/host/lib/ic_reg_maps/gen_ad9522_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py @@ -1,6 +1,6 @@ #!/usr/bin/env python # -# Copyright 2010-2011 Ettus Research LLC +# Copyright 2010-2011,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -88,39 +88,38 @@ ref2_freq_gt_thresh 0x01F[2] 0 ref1_freq_gt_thresh 0x01F[1] 0 digital_lock_detect 0x01F[0] 0 ######################################################################## -#for $i in range(12) -#set $addr = ($i + 0x0F0) -out$(i)_format $(addr)[7] 0 lvds, cmos -out$(i)_cmos_configuration $(addr)[6:5] 3 off, a_on, b_on, ab_on -out$(i)_polarity $(addr)[4:3] 0 lvds_a_non_b_inv=0, lvds_a_inv_b_non=1, cmos_ab_non=0, cmos_ab_inv=1, cmos_a_non_b_inv=2, cmos_a_inv_b_non=3 -out$(i)_lvds_diff_voltage $(addr)[2:1] 1 1_75ma, 3_5ma, 5_25ma, 7_0ma -out$(i)_lvds_power_down $(addr)[0] 0 -#end for +% for i in range(12): +<% addr = (i + 0x0F0) %>\ +out${i}_format ${addr}[7] 0 lvds, cmos +out${i}_cmos_configuration ${addr}[6:5] 3 off, a_on, b_on, ab_on +out${i}_polarity ${addr}[4:3] 0 lvds_a_non_b_inv=0, lvds_a_inv_b_non=1, cmos_ab_non=0, cmos_ab_inv=1, cmos_a_non_b_inv=2, cmos_a_inv_b_non=3 +out${i}_lvds_diff_voltage ${addr}[2:1] 1 1_75ma, 3_5ma, 5_25ma, 7_0ma +out${i}_lvds_power_down ${addr}[0] 0 +% endfor ######################################################################## -#for $i in reversed(range(8)) -csdld_en_out_$i 0x0FC[$i] 0 ignore, async -#end for +% for i in reversed(range(8)): +csdld_en_out_${i} 0x0FC[${i}] 0 ignore, async +% endfor ######################################################################## -#for $i in reversed(range(4)) -csdld_en_out_$(8 + $i) 0x0FD[$i] 0 ignore, async -#end for +% for i in reversed(range(4)): +csdld_en_out_${8 + i} 0x0FD[${i}] 0 ignore, async +% endfor ######################################################################## -#set $default_val = 0x7 -#for $i in range(4) -#set $addr0 = hex($i*3 + 0x190) -#set $addr1 = hex($i*3 + 0x191) -#set $addr2 = hex($i*3 + 0x192) -divider$(i)_low_cycles $(addr0)[7:4] $default_val -divider$(i)_high_cycles $(addr0)[3:0] $default_val -divider$(i)_bypass $(addr1)[7] 0 -divider$(i)_ignore_sync $(addr1)[6] 0 -divider$(i)_force_high $(addr1)[5] 0 -divider$(i)_start_high $(addr1)[4] 0 -divider$(i)_phase_offset $(addr1)[3:0] 0 -channel$(i)_power_down $(addr2)[2] 0 -disable_divider$(i)_ddc $(addr2)[0] 0 -#set $default_val /= 2 -#end for +% for i in range(4): +<% default_val = int(0x7 / (2**i)) %>\ +<% addr0 = hex(i*3 + 0x190) %>\ +<% addr1 = hex(i*3 + 0x191) %>\ +<% addr2 = hex(i*3 + 0x192) %>\ +divider${i}_low_cycles ${addr0}[7:4] ${default_val} +divider${i}_high_cycles ${addr0}[3:0] ${default_val} +divider${i}_bypass ${addr1}[7] 0 +divider${i}_ignore_sync ${addr1}[6] 0 +divider${i}_force_high ${addr1}[5] 0 +divider${i}_start_high ${addr1}[4] 0 +divider${i}_phase_offset ${addr1}[3:0] 0 +channel${i}_power_down ${addr2}[2] 0 +disable_divider${i}_ddc ${addr2}[0] 0 +% endfor ######################################################################## vco_divider 0x1E0[2:0] 2 div2, div3, div4, div5, div6, static, div1 power_down_clock_input_sel 0x1E1[4] 0 @@ -145,13 +144,13 @@ BODY_TMPL="""\ boost::uint32_t get_reg(boost::uint16_t addr){ boost::uint32_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } if (addr == 0){ //mirror 4 bits in register 0 reg |= ((reg >> 7) & 0x1) << 0; @@ -164,13 +163,13 @@ boost::uint32_t get_reg(boost::uint16_t addr){ void set_reg(boost::uint16_t addr, boost::uint32_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } diff --git a/host/lib/ic_reg_maps/gen_ad9777_regs.py b/host/lib/ic_reg_maps/gen_ad9777_regs.py index 47b61cf44..514283409 100755 --- a/host/lib/ic_reg_maps/gen_ad9777_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9777_regs.py @@ -91,13 +91,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ad9862_regs.py b/host/lib/ic_reg_maps/gen_ad9862_regs.py index 00340224c..022d97c16 100755 --- a/host/lib/ic_reg_maps/gen_ad9862_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9862_regs.py @@ -41,10 +41,10 @@ all_rx_pd 1[0] 0 ######################################################################## ## Rx A and B ######################################################################## -#for $x, $i in (('a', 2), ('b', 3)) -byp_buffer_$x $(i)[7] 0 -rx_pga_$x $(i)[0:4] 0 -#end for +% for x, i in (('a', 2), ('b', 3)): +byp_buffer_${x} ${i}[7] 0 +rx_pga_${x} ${i}[0:4] 0 +% endfor ######################################################################## ## Rx Misc ######################################################################## @@ -76,13 +76,13 @@ tx_analog_pd 8[0:2] 0 none=0, txb=4, txa=2, both=7 ######################################################################## ## Tx Offset and Gain ######################################################################## -#for $x, $i, $j, $k in (('a', 10, 11, 14), ('b', 12, 13, 15)) -dac_$(x)_offset_1_0 $(i)[6:7] 0 -dac_$(x)_offset_dir $(i)[0] 0 neg_diff, pos_dif -dac_$(x)_offset_9_2 $(j)[0:7] 0 -dac_$(x)_coarse_gain $(k)[6:7] 0 -dac_$(x)_fine_gain $(k)[0:5] 0 -#end for +% for x, i, j, k in (('a', 10, 11, 14), ('b', 12, 13, 15)): +dac_${x}_offset_1_0 ${i}[6:7] 0 +dac_${x}_offset_dir ${i}[0] 0 neg_diff, pos_dif +dac_${x}_offset_9_2 ${j}[0:7] 0 +dac_${x}_coarse_gain ${k}[6:7] 0 +dac_${x}_fine_gain ${k}[0:5] 0 +% endfor tx_pga_gain 16[0:7] 0 ######################################################################## ## Tx Misc @@ -139,20 +139,20 @@ dis1 25[0] 0 enb, dis ######################################################################## ## Aux ADC ######################################################################## -#for $x, $i in (('a2', 26), ('a1', 28), ('b2', 30), ('b1', 32)) -aux_adc_$(x)_1_0 $(i)[6:7] 0 -aux_adc_$(x)_9_2 $int(1+$i)[0:7] 0 -#end for +% for x, i in (('a2', 26), ('a1', 28), ('b2', 30), ('b1', 32)): +aux_adc_${x}_1_0 ${i}[6:7] 0 +aux_adc_${x}_9_2 ${int(1+i)}[0:7] 0 +% endfor ######################################################################## ## Aux ADC Control ######################################################################## aux_spi 34[7] 0 dis, enb sel_bnota 34[6] 0 adc_a, adc_b -#for $x, $i in (('b', 5), ('a', 2)) -refsel_$(x) 34[$i] 0 external, internal -select_$(x) 34[$int($i-1)] 0 aux_adc2, aux_adc1 -start_$(x) 34[$int($i-2)] 0 -#end for +% for x, i in (('b', 5), ('a', 2)): +refsel_${x} 34[${i}] 0 external, internal +select_${x} 34[${int(i-1)}] 0 aux_adc2, aux_adc1 +start_${x} 34[${int(i-2)}] 0 +% endfor ######################################################################## ## Aux ADC Clock ######################################################################## @@ -160,9 +160,9 @@ clk_4 35[0] 0 1_2, 1_4 ######################################################################## ## Aux DAC ######################################################################## -#for $x, $i in (('a', 36), ('b', 37), ('c', 38)) -aux_dac_$x $(i)[0:7] 0 -#end for +% for x, i in (('a', 36), ('b', 37), ('c', 38)): +aux_dac_${x} ${i}[0:7] 0 +% endfor ######################################################################## ## Aux DAC Update ######################################################################## @@ -205,26 +205,26 @@ BODY_TMPL=""" boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in range(0, 63+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint16_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(0, 63+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint16_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } void set_reg(boost::uint8_t addr, boost::uint16_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } diff --git a/host/lib/ic_reg_maps/gen_adf4350_regs.py b/host/lib/ic_reg_maps/gen_adf4350_regs.py index fce2f569b..644654dee 100755 --- a/host/lib/ic_reg_maps/gen_adf4350_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4350_regs.py @@ -43,8 +43,8 @@ power_down 2[5] 0 disabled, enabled pd_polarity 2[6] 1 negative, positive ldp 2[7] 0 10ns, 6ns ldf 2[8] 0 frac_n, int_n -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) -charge_pump_current 2[9:12] 5 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) %>\ +charge_pump_current 2[9:12] 5 ${current_setting_enums} double_buffer 2[13] 0 disabled, enabled r_counter_10_bit 2[14:23] 0 reference_divide_by_2 2[24] 1 disabled, enabled @@ -101,13 +101,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_adf4351_regs.py b/host/lib/ic_reg_maps/gen_adf4351_regs.py index 4b0ef788c..6699e5137 100755 --- a/host/lib/ic_reg_maps/gen_adf4351_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4351_regs.py @@ -44,8 +44,8 @@ power_down 2[5] 0 disabled, enabled pd_polarity 2[6] 1 negative, positive ldp 2[7] 0 10ns, 6ns ldf 2[8] 0 frac_n, int_n -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) -charge_pump_current 2[9:12] 5 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) %>\ +charge_pump_current 2[9:12] 5 ${current_setting_enums} double_buffer 2[13] 0 disabled, enabled r_counter_10_bit 2[14:23] 0 reference_divide_by_2 2[24] 1 disabled, enabled @@ -105,13 +105,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_adf4360_regs.py b/host/lib/ic_reg_maps/gen_adf4360_regs.py index 3fd8707a7..921f014ff 100755 --- a/host/lib/ic_reg_maps/gen_adf4360_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4360_regs.py @@ -32,9 +32,9 @@ charge_pump_output 0[9] 0 normal, 3state cp_gain_0 0[10] 0 set1, set2 mute_till_ld 0[11] 0 dis, enb output_power_level 0[12:13] 0 3_5ma, 5_0ma, 7_5ma, 11_0ma -#set $current_setting_enums = ', '.join(map(lambda x: x+"ma", "0_31 0_62 0_93 1_25 1_56 1_87 2_18 2_50".split())) -current_setting1 0[14:16] 0 $current_setting_enums -current_setting2 0[17:19] 0 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: x+"ma", "0_31 0_62 0_93 1_25 1_56 1_87 2_18 2_50".split())) %>\ +current_setting1 0[14:16] 0 ${current_setting_enums} +current_setting2 0[17:19] 0 ${current_setting_enums} power_down 0[20:21] 0 normal_op=0, async_pd=1, sync_pd=3 prescaler_value 0[22:23] 0 8_9, 16_17, 32_33 ######################################################################## @@ -68,13 +68,13 @@ enum addr_t{ boost::uint32_t get_reg(addr_t addr){ boost::uint32_t reg = addr & 0x3; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ads62p44_regs.py b/host/lib/ic_reg_maps/gen_ads62p44_regs.py index f0a84d940..df5c0c66c 100755 --- a/host/lib/ic_reg_maps/gen_ads62p44_regs.py +++ b/host/lib/ic_reg_maps/gen_ads62p44_regs.py @@ -95,13 +95,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ads62p48_regs.py b/host/lib/ic_reg_maps/gen_ads62p48_regs.py index c38ce8ff1..fa5668d4f 100644..100755 --- a/host/lib/ic_reg_maps/gen_ads62p48_regs.py +++ b/host/lib/ic_reg_maps/gen_ads62p48_regs.py @@ -55,13 +55,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_lmk04816_regs.py b/host/lib/ic_reg_maps/gen_lmk04816_regs.py index e89a82671..d432ac706 100644..100755 --- a/host/lib/ic_reg_maps/gen_lmk04816_regs.py +++ b/host/lib/ic_reg_maps/gen_lmk04816_regs.py @@ -1,4 +1,4 @@ -#Copyright 2010 Ettus Research LLC +#Copyright 2010,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -26,7 +26,7 @@ address0 0[0:4] 0 CLKout0_1_DIV 0[5:15] 25 CLKout0_1_HS 0[16] 0 RESET 0[17] 0 no_reset, reset -CLKout0_1_DDLY 0[18:27] 0 five +CLKout0_1_DDLY 0[18:27] 0 CLKout0_ADLY_SEL 0[28] 0 d_pd, d_ev_x, d_odd_y, d_both CLKout1_ADLY_SEL 0[29] 0 d_pd, d_ev_x, d_odd_y, d_both Required_0 0[30] 0 @@ -94,15 +94,15 @@ CLKout10_11_PD 5[31] 1 normal, power_down ######################################################################## ## address 6 ######################################################################## -#set $CLKoutX_TYPE_ENUMS = "p_down=0, LVDS=1, LVPECL_700mVpp=2, LVPECL_1200mVpp=3, LVPECL_1600mVpp=4, LVPECL_200mVpp=5, LVCMOS=6, LVCMOS_IN=7, LVCMOS_NN=8, LVCMOS_II=9, LVCMOS_LN=10, LVCMOS_LI=11, LVCMOS_NL=12, LVCMOS_IL=13, LVCMOS_LL=1" +<% CLKoutX_TYPE_ENUMS = "p_down=0, LVDS=1, LVPECL_700mVpp=2, LVPECL_1200mVpp=3, LVPECL_1600mVpp=4, LVPECL_200mVpp=5, LVCMOS=6, LVCMOS_IN=7, LVCMOS_NN=8, LVCMOS_II=9, LVCMOS_LN=10, LVCMOS_LI=11, LVCMOS_NL=12, LVCMOS_IL=13, LVCMOS_LL=1" %>\ address6 6[0:4] 6 CLKout0_1_ADLY 6[5:9] 0 Required_6_10 6[10] 0 CLKout2_3_ADLY 6[11:15] 0 -CLKout0_TYPE 6[16:19] 0 $(CLKoutX_TYPE_ENUMS) -CLKout1_TYPE 6[20:23] 0 $(CLKoutX_TYPE_ENUMS) -CLKout2_TYPE 6[24:27] 0 $(CLKoutX_TYPE_ENUMS) -CLKout3_TYPE 6[28:31] 0 $(CLKoutX_TYPE_ENUMS) +CLKout0_TYPE 6[16:19] 0 ${CLKoutX_TYPE_ENUMS} +CLKout1_TYPE 6[20:23] 0 ${CLKoutX_TYPE_ENUMS} +CLKout2_TYPE 6[24:27] 0 ${CLKoutX_TYPE_ENUMS} +CLKout3_TYPE 6[28:31] 0 ${CLKoutX_TYPE_ENUMS} ######################################################################## ## address 7 ######################################################################## @@ -110,21 +110,21 @@ address7 7[0:4] 7 CLKout4_5_ADLY 7[5:9] 0 Required_7_10 7[10] 0 CLKout6_7_ADLY 7[11:15] 0 -CLKout4_TYPE 7[16:19] 0 $(CLKoutX_TYPE_ENUMS) -CLKout5_TYPE 7[20:23] 0 $(CLKoutX_TYPE_ENUMS) -CLKout6_TYPE 7[24:27] 0 $(CLKoutX_TYPE_ENUMS) -CLKout7_TYPE 7[28:31] 0 $(CLKoutX_TYPE_ENUMS) +CLKout4_TYPE 7[16:19] 0 ${CLKoutX_TYPE_ENUMS} +CLKout5_TYPE 7[20:23] 0 ${CLKoutX_TYPE_ENUMS} +CLKout6_TYPE 7[24:27] 0 ${CLKoutX_TYPE_ENUMS} +CLKout7_TYPE 7[28:31] 0 ${CLKoutX_TYPE_ENUMS} ######################################################################## ## address 8 ######################################################################## address8 8[0:4] 8 CLKout8_9_ADLY 8[5:9] 0 Required_8_10 8[10] 0 -CLKout10_11_ADLY 8[11:15] 0 $(CLKoutX_TYPE_ENUMS) -CLKout8_TYPE 8[16:19] 0 $(CLKoutX_TYPE_ENUMS) -CLKout9_TYPE 8[20:23] 0 $(CLKoutX_TYPE_ENUMS) -CLKout10_TYPE 8[24:27] 0 $(CLKoutX_TYPE_ENUMS) -CLKout11_TYPE 8[28:31] 0 $(CLKoutX_TYPE_ENUMS) +CLKout10_11_ADLY 8[11:15] 0 ${CLKoutX_TYPE_ENUMS} +CLKout8_TYPE 8[16:19] 0 ${CLKoutX_TYPE_ENUMS} +CLKout9_TYPE 8[20:23] 0 ${CLKoutX_TYPE_ENUMS} +CLKout10_TYPE 8[24:27] 0 ${CLKoutX_TYPE_ENUMS} +CLKout11_TYPE 8[28:31] 0 ${CLKoutX_TYPE_ENUMS} ######################################################################## ## address 9 ######################################################################## @@ -378,22 +378,18 @@ BODY_TMPL = """\ boost::uint32_t get_reg(int addr){ boost::uint32_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } """ - - - - if __name__ == '__main__': import common; common.generate( name='lmk04816_regs', @@ -402,6 +398,3 @@ if __name__ == '__main__': file=__file__, ) - - - diff --git a/host/lib/ic_reg_maps/gen_max2112_regs.py b/host/lib/ic_reg_maps/gen_max2112_regs.py index c2fc4e3e2..be760ec2e 100755 --- a/host/lib/ic_reg_maps/gen_max2112_regs.py +++ b/host/lib/ic_reg_maps/gen_max2112_regs.py @@ -53,13 +53,14 @@ f_divider_lsb 4[0:7] 0x84 ######################################################################## ## XTAL-Divider R-Divider (5) Write ######################################################################## -#set $xtal_divider_names = ', '.join(map(lambda x: 'div' + str(x), range(1,9))) -xtal_divider 5[5:7] 0 $xtal_divider_names +<% xtal_divider_names = ', '.join(map(lambda x: 'div' + str(x), range(1,9))) %>\ +xtal_divider 5[5:7] 0 ${xtal_divider_names} r_divider 5[0:4] 1 ######################################################################## ## PLL (6) Write ######################################################################## -d24 6[7] 1 div2, div4 ## div2 for LO <= 1125M, div4 > 1125M +## div2 for LO <= 1125M, div4 > 1125M +d24 6[7] 1 div2, div4 cps 6[6] 1 i_cp_from_icp, i_cp_from_vas icp 6[5] 0 i_cp_600ua, i_cp_1200ua ##reserved 6[0:4] 0 @@ -73,7 +74,8 @@ ade 7[0] 1 disabled, enabled ######################################################################## ## LPF (8) Write ######################################################################## -lp 8[0:7] 0x4B ## map(lambda x: "%0.2f"%((4e6 + (x - 12) * 290e3)/1e6), range(255)) in MHz +## map(lambda x: "%0.2f"%((4e6 + (x - 12) * 290e3)/1e6), range(255)) in MHz +lp 8[0:7] 0x4B ######################################################################## ## Control (9) Write ######################################################################## @@ -81,7 +83,8 @@ stby 9[7] 0 normal, disable_sig_and_synth ##reserved 9[6] 0 pwdn 9[5] 0 normal, invalid ##reserved 9[4] 0 -bbg 9[0:3] 0 ## Baseband Gain in dB +## Baseband Gain in dB +bbg 9[0:3] 0 ######################################################################## ## Shutdown (0xA) Write ######################################################################## @@ -118,7 +121,8 @@ ld 0xC[4] 0 unlocked, locked ######################################################################## ## Status Byte-2 (0xD) Read ######################################################################## -vcosbr 0xD[3:7] 0 ## vco band readback +## vco band readback +vcosbr 0xD[3:7] 0 adc 0xD[0:2] 0 ool0, lock0, vaslock0, vaslock1, vaslock2, vaslock3, lock1, ool1 """ @@ -129,41 +133,30 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } void set_reg(boost::uint8_t addr, boost::uint8_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } """ -SPLIT_REGS_HELPER_TMPL="""\ -#for $divname in ['n','f'] -void set_$(divname)_divider(boost::uint32_t $divname){ - #for $regname in sorted(map(lambda r: r.get_name(), filter(lambda r: r.get_name().find(divname + '_divider') == 0, $regs))) - #end for -} -#end for -""" - #$regname = boost::uint8_t($divname & $regs[regname].get_mask()); - #$divname = boost::uint32_t($divname >> $regs[regname].get_shift()); - if __name__ == '__main__': import common; common.generate( name='max2112_write_regs', diff --git a/host/lib/ic_reg_maps/gen_max2118_regs.py b/host/lib/ic_reg_maps/gen_max2118_regs.py index 506fbaec8..01d7615de 100755 --- a/host/lib/ic_reg_maps/gen_max2118_regs.py +++ b/host/lib/ic_reg_maps/gen_max2118_regs.py @@ -38,28 +38,31 @@ n_divider_lsb 1[0:7] 0xB6 ######################################################################## ## R, Charge Pump, and VCO (2) Write ######################################################################## -#set $r_divider_names = ', '.join(map(lambda x: 'div' + str(2**(x+1)), range(0,8))) -r_divider 2[5:7] 1 $r_divider_names -#set $cp_current_bias = ', '.join(map(lambda x: 'i_cp_%dua'%(50*2**x), range(0,4))) -cp_current 2[3:4] 3 $cp_current_bias +<% r_divider_names = ', '.join(map(lambda x: 'div' + str(2**(x+1)), range(0,8))) %>\ +r_divider 2[5:7] 1 ${r_divider_names} +<% cp_current_bias = ', '.join(map(lambda x: 'i_cp_%dua'%(50*2**x), range(0,4))) %>\ +cp_current 2[3:4] 3 ${cp_current_bias} osc_band 2[0:2] 5 ######################################################################## ## I/Q Filter DAC (3) Write ######################################################################## ##unused 3[7] 0 -f_dac 3[0:6] 0x7F ## filter tuning dac, depends on m +## filter tuning dac, depends on m +f_dac 3[0:6] 0x7F ######################################################################## ## LPF Divider DAC (4) Write ######################################################################## adl_vco_adc_latch 4[7] 0 disabled, enabled ade_vco_ade_read 4[6] 0 disabled, enabled dl_output_drive 4[5] 0 iq_590m_vpp, iq_1_vpp -m_divider 4[0:4] 2 ## filter tuning counter +## filter tuning counter +m_divider 4[0:4] 2 ######################################################################## ## GC2 and Diag (5) Write ######################################################################## diag 5[5:7] 0 normal, cp_i_source, cp_i_sink, cp_high_z, unused, n_and_filt, r_and_gc2, m_div -gc2 5[0:4] 0x1F ## Step Size: 0-1: 0dB, 2-22: 1dB, 23-31: 0.5dB +## Step Size: 0-1: 0dB, 2-22: 1dB, 23-31: 0.5dB +gc2 5[0:4] 0x1F """ ######################################################################## @@ -71,11 +74,13 @@ READ_REGS_TMPL="""\ ## Status (0) Read ######################################################################## pwr 0[6] 0 not_reset, reset -adc 0[2:4] 0 ## VCO tuning voltage, Lock Status +## VCO tuning voltage, Lock Status +adc 0[2:4] 0 ######################################################################## ## I/Q Filter DAC (1) Read ######################################################################## -filter_dac 1[0:6] 0 ## I/Q Filter tuning DAC, current +## I/Q Filter tuning DAC, current +filter_dac 1[0:6] 0 """ ######################################################################## @@ -85,26 +90,26 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } void set_reg(boost::uint8_t addr, boost::uint8_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } """ diff --git a/host/lib/ic_reg_maps/gen_max2829_regs.py b/host/lib/ic_reg_maps/gen_max2829_regs.py index 383131c18..dbcb68ec9 100755 --- a/host/lib/ic_reg_maps/gen_max2829_regs.py +++ b/host/lib/ic_reg_maps/gen_max2829_regs.py @@ -112,13 +112,13 @@ BODY_TMPL="""\ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint16_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint16_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint16_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return (boost::uint32_t(reg) << 4) | (addr & 0xf); } diff --git a/host/lib/ic_reg_maps/gen_max2870_regs.py b/host/lib/ic_reg_maps/gen_max2870_regs.py index f26c27281..af4e3c786 100644..100755 --- a/host/lib/ic_reg_maps/gen_max2870_regs.py +++ b/host/lib/ic_reg_maps/gen_max2870_regs.py @@ -28,8 +28,10 @@ REGS_TMPL="""\ ## Write-only, default = 0x007D0000 ######################################################################## int_n_mode 0x00[31] 0 frac_n, int_n -int_16_bit 0x00[15:30] 0x007D ##Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. -frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 +## Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. +int_16_bit 0x00[15:30] 0x007D +## Frac divider: 0-4095 +frac_12_bit 0x00[3:14] 0 ######################################################################## ## Address 0x01 ## Charge pump control @@ -38,8 +40,10 @@ frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 cpoc 0x01[31] 0 disabled, enabled cpl 0x01[29:30] 1 disabled, enabled, res1, res2 cpt 0x01[27:28] 0 normal, reserved, force_source, force_sink -phase_12_bit 0x01[15:26] 1 ##sets phase shift -mod_12_bit 0x01[3:14] 0xFFF ##VCO frac modulus +## sets phase shift +phase_12_bit 0x01[15:26] 1 +## VCO frac modulus +mod_12_bit 0x01[3:14] 0xFFF ######################################################################## ## Address 0x02 ## Misc. control @@ -50,10 +54,11 @@ low_noise_and_spur 0x02[29:30] 3 low_noise, reserved, low_spur_1, muxout 0x02[26:28] 1 tri_state, high, low, rdiv, ndiv, ald, dld, res7 reference_doubler 0x02[25] 0 disabled, enabled reference_divide_by_2 0x02[24] 0 disabled, enabled -r_counter_10_bit 0x02[14:23] 1 ##R divider value, 1-1023 +## R divider value, 1-1023 +r_counter_10_bit 0x02[14:23] 1 double_buffer 0x02[13] 0 disabled, enabled -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) -charge_pump_current 0x02[9:12] 7 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) %>\ +charge_pump_current 0x02[9:12] 7 ${current_setting_enums} ldf 0x02[8] 0 frac_n, int_n ldp 0x02[7] 0 10ns, 6ns pd_polarity 0x02[6] 1 negative, positive @@ -65,18 +70,22 @@ counter_reset 0x02[3] 0 normal, reset ## VCO control ## Write-only, default = 0x0000000B ######################################################################## -vco 0x03[26:31] 0 ##VCO subband selection, used when VAS disabledd -vas 0x03[25] 0 enabled, disabled ##VCO autoselect +## VCO subband selection, used when VAS disabledd +vco 0x03[26:31] 0 +## VCO autoselect +vas 0x03[25] 0 enabled, disabled retune 0x03[24] 1 disabled, enabled clock_div_mode 0x03[15:16] 0 clock_divider_off, fast_lock, phase, reserved -clock_divider_12_bit 0x03[3:14] 1 ##clock divider, 1-4095 +## clock divider, 1-4095 +clock_divider_12_bit 0x03[3:14] 1 ######################################################################## ## Address 0x04 ## RF output control ## Write-only, default = 0x6180B23C ######################################################################## res4 0x04[26:31] 0x18 -bs_msb 0x04[24:25] 0 ##Band select MSBs +## Band select MSBs +bs_msb 0x04[24:25] 0 feedback_select 0x04[23] 1 divided, fundamental rf_divider_select 0x04[20:22] 0 div1, div2, div4, div8, div16, div32, div64, div128 band_select_clock_div 0x04[12:19] 0 @@ -111,13 +120,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_max2871_regs.py b/host/lib/ic_reg_maps/gen_max2871_regs.py index 338a019d8..f591c1636 100644..100755 --- a/host/lib/ic_reg_maps/gen_max2871_regs.py +++ b/host/lib/ic_reg_maps/gen_max2871_regs.py @@ -28,8 +28,10 @@ REGS_TMPL="""\ ## Write-only, default = 0x007D0000 ######################################################################## int_n_mode 0x00[31] 0 frac_n, int_n -int_16_bit 0x00[15:30] 0x007D ##Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. -frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 +## Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. +int_16_bit 0x00[15:30] 0x007D +## Frac divider: 0-4095 +frac_12_bit 0x00[3:14] 0 ######################################################################## ## Address 0x01 ## Charge pump control @@ -38,8 +40,10 @@ frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 res1 0x01[31] 0 cpl 0x01[29:30] 1 disabled, enabled, res1, res2 cpt 0x01[27:28] 0 normal, reserved, force_source, force_sink -phase_12_bit 0x01[15:26] 1 ##sets phase shift -mod_12_bit 0x01[3:14] 0xFFF ##VCO frac modulus +## sets phase shift +phase_12_bit 0x01[15:26] 1 +## VCO frac modulus +mod_12_bit 0x01[3:14] 0xFFF ######################################################################## ## Address 0x02 ## Misc. control @@ -50,10 +54,11 @@ low_noise_and_spur 0x02[29:30] 3 low_noise, reserved, low_spur_1, muxout 0x02[26:28] 0x6 tri_state, high, low, rdiv, ndiv, ald, dld, sync, res8, res9, res10, res11, spi, res13, res14, res15 reference_doubler 0x02[25] 0 disabled, enabled reference_divide_by_2 0x02[24] 0 disabled, enabled -r_counter_10_bit 0x02[14:23] 1 ##R divider value, 1-1023 +## R divider value, 1-1023 +r_counter_10_bit 0x02[14:23] 1 double_buffer 0x02[13] 0 disabled, enabled -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) -charge_pump_current 0x02[9:12] 7 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) %>\ +charge_pump_current 0x02[9:12] 7 ${current_setting_enums} ldf 0x02[8] 0 frac_n, int_n ldp 0x02[7] 0 10ns, 6ns pd_polarity 0x02[6] 1 negative, positive @@ -65,14 +70,17 @@ counter_reset 0x02[3] 0 normal, reset ## VCO control ## Write-only, default = 0x0000000B ######################################################################## -vco 0x03[26:31] 0 ##VCO subband selection, used when VAS disabledd -shutdown_vas 0x03[25] 0 enabled, disabled ##VCO autoselect +## VCO subband selection, used when VAS disabledd +vco 0x03[26:31] 0 +## VCO autoselect +shutdown_vas 0x03[25] 0 enabled, disabled retune 0x03[24] 1 disabled, enabled res3 0x3[19:23] 0 csm 0x3[18] 0 disabled, enabled mutedel 0x3[17] 0 disabled, enabled clock_div_mode 0x03[15:16] 0 clock_divider_off, fast_lock, phase, reserved -clock_divider_12_bit 0x03[3:14] 1 ##clock divider, 1-4095 +## clock divider, 1-4095 +clock_divider_12_bit 0x03[3:14] 1 ######################################################################## ## Address 0x04 ## RF output control @@ -82,7 +90,8 @@ res4 0x04[29:31] 0x3 shutdown_ldo 0x04[28] 0 enabled, disabled shutdown_div 0x04[27] 0 enabled, disabled shutdown_ref 0x04[26] 0 enabled, disabled -bs_msb 0x04[24:25] 0 ##Band select MSBs +## Band select MSBs +bs_msb 0x04[24:25] 0 feedback_select 0x04[23] 1 divided, fundamental rf_divider_select 0x04[20:22] 0 div1, div2, div4, div8, div16, div32, div64, div128 band_select_clock_div 0x04[12:19] 0 @@ -124,13 +133,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py b/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py index 677a201de..308d7d524 100755 --- a/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py +++ b/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py @@ -28,7 +28,7 @@ REGS_TMPL="""\ ######################################################################## ## ID_byte_1 (0x00) Read ######################################################################## -##reserved as 1 0x00[7] 1 +## reserved as 1 0x00[7] 1 ident_14_8 0x00[0:6] 0 ######################################################################## ## ID_byte_2 (0x01) Read @@ -43,23 +43,25 @@ minor_rev 0x02[0:3] 0 ######################################################################## ## Thermo_byte_1 (0x03) Read ######################################################################## -##reserved 0x03[7] 0 -tm_d 0x03[0:6] 0 ## 22-127deg C junction temp +## reserved 0x03[7] 0 +## 22-127deg C junction temp +tm_d 0x03[0:6] 0 ######################################################################## ## Thermo_byte_2 (0x04) Write ######################################################################## -##reserved 0x04[1:7] 0 +## reserved 0x04[1:7] 0 tm_on 0x04[0] 0 sensor_off, sensor_on ######################################################################## ## Power_state_byte_1 (0x05) Read ######################################################################## -##reserved 0x05[2:7] 0 +## reserved 0x05[2:7] 0 por 0x05[1] 0 read, reset lo_lock 0x05[0] 0 unlocked, locked ######################################################################## -## Power_state_byte_2 (0x06) Read/Write ## Standby modes +## Standby modes +## Power_state_byte_2 (0x06) Read/Write ######################################################################## -##reserved 0x06[4:7] 0 +## reserved 0x06[4:7] 0 sm 0x06[3] 0 normal, standby sm_pll 0x06[2] 0 on, off sm_lna 0x06[1] 0 on, off @@ -68,14 +70,15 @@ sm_lna 0x06[1] 0 on, off ######################################################################## ## Input_Power_Level_byte (0x07) Read ######################################################################## -##reserved 0x07[7] 0 -power_level 0x07[0:6] 0 ## 40dB_Vrms to 110dB_Vrms +## reserved 0x07[7] 0 +## 40dB_Vrms to 110dB_Vrms +power_level 0x07[0:6] 0 ## Trigger power level calculation with MSM_byte_1 and MSM_byte_2 ######################################################################## ## IRQ_status (0x08) Read/Write ######################################################################## irq_status 0x08[7] 0 cleared, set -##reserved 0x08[6] 0 +## reserved 0x08[6] 0 irq_xtalcal_end 0x08[5] 0 false, true irq_rssi_end 0x08[4] 0 false, true irq_localc_end 0x08[3] 0 false, true @@ -86,7 +89,7 @@ irq_rccal_end 0x08[0] 0 false, true ## IRQ_enable (0x09) Read/Write ######################################################################## irq_enable 0x09[7] 1 false, true -##reserved 0x09[6] 0 +## reserved 0x09[6] 0 irq_xtalcal_enable 0x09[5] 0 false, true irq_rssi_enable 0x09[4] 0 false, true irq_localc_enable 0x09[3] 0 false, true @@ -97,7 +100,7 @@ irq_rccal_enable 0x09[0] 0 false, true ## IRQ_clear (0x0a) Read/Write ######################################################################## irq_clear 0x0a[7] 0 false, true -##reserved 0x0a[6] 0 +## reserved 0x0a[6] 0 irq_xtalcal_clear 0x0a[5] 0 false, true irq_rssi_clear 0x0a[4] 0 false, true irq_localc_clear 0x0a[3] 0 false, true @@ -108,7 +111,7 @@ irq_rccal_clear 0x0a[0] 0 false, true ## IRQ_set (0x0b) Read ######################################################################## irq_set 0x0b[7] 0 false, true -##reserved 0x0b[6] 0 +## reserved 0x0b[6] 0 irq_xtalcal_set 0x0b[5] 0 false, true irq_rssi_set 0x0b[4] 0 false, true irq_localc_set 0x0b[3] 0 false, true @@ -120,12 +123,12 @@ irq_rccal_set 0x0b[0] 0 false, true ######################################################################## lt_enable 0x0c[7] 0 agc1_6_15db 0x0c[6] 1 -##reserved 0x0c[4:5] 0 +## reserved 0x0c[4:5] 0 agc1_top 0x0c[0:3] 0 ######################################################################## ## AGC2_byte_1 (0x0d) Read ######################################################################## -##reserved 0x0d[5:7] 0 +## reserved 0x0d[5:7] 0 agc2_top 0x0d[0:4] 0xf ######################################################################## ## AGCK_byte_1 (0x0e) Read/Write @@ -141,24 +144,25 @@ agck_mode 0x0e[0:1] 1 analog_tv=1, digital_tv=2 pd_rfagc_adapt 0x0f[7] 0 on, off rfagc_adapt_top 0x0f[5:6] 0 rfagc_low_bw 0x0f[4] 1 -rf_atten_3db 0x0f[3] 0 0db, 3db ## FIXME +## FIXME +rf_atten_3db 0x0f[3] 0 0db, 3db agc3_top 0x0f[0:2] 1 ######################################################################## ## IR_MIXER_byte_1 (0x10) Read/Write ######################################################################## -##reserved 0x10[4:7] 0 +## reserved 0x10[4:7] 0 agc4_top 0x10[0:3] 1 ######################################################################## ## AGC5_byte_1 (0x11) Read/Write ######################################################################## -##reserved 0x11[7] 0 +## reserved 0x11[7] 0 agcs_do_step_assym 0x11[5:6] 2 agc5_hpf 0x11[4] 1 off, on agc5_top 0x11[0:3] 1 ######################################################################## ## IF_AGC_byte (0x12) Read/Write ######################################################################## -##reserved 0x12[3:7] 0 +## reserved 0x12[3:7] 0 if_level 0x12[0:2] 0 0_5vpp=7, 0_6vpp=6, 0_7vpp=5, 0_85vpp=4, 0_8vpp=3, 1_0vpp=2, 1_25vpp=1, 2_0vpp=0 ######################################################################## ## IF_byte_1 (0x13) Read/Write @@ -172,18 +176,19 @@ lp_fc 0x13[0:2] 3 1_7mhz=4, 6_0mhz=0, 7_0mhz=1, 8_0mhz=2, ######################################################################## i2c_clock_mode 0x14[7] 0 digital_clock 0x14[6] 1 spread_off, spread_on -##reserved 0x14[5] 0 +## reserved 0x14[5] 0 xtalosc_anareg_en 0x14[4] 0 -##reserved 0x14[2:3] 0 +## reserved 0x14[2:3] 0 xtout 0x14[0:1] 0 no=0, 16mhz=3 ######################################################################## ## IF_Frequency_byte (0x15) Read/Write ######################################################################## -if_freq 0x15[0:7] 0 ## IF frequency = if_freq*50 (kHz) +## IF frequency = if_freq*50 (kHz) +if_freq 0x15[0:7] 0 ######################################################################## ## RF_Frequency_byte_1 (0x16) Read/Write ######################################################################## -##reserved 0x16[4:7] 0 +## reserved 0x16[4:7] 0 rf_freq_19_16 0x16[0:3] 0 ######################################################################## ## RF_Frequency_byte_2 (0x17) Read/Write @@ -209,7 +214,7 @@ calc_pll 0x19[0] 0 ######################################################################## ## MSM_byte_2 (0x1a) Read ######################################################################## -##reserved 0x1a[2:7] 0 +## reserved 0x1a[2:7] 0 xtalcal_launch 0x1a[1] 0 msm_launch 0x1a[0] 0 ######################################################################## @@ -227,11 +232,11 @@ psm_lodriver 0x1b[0:1] 0 dcc_bypass 0x1c[7] 0 dcc_slow 0x1c[6] 0 dcc_psm 0x1c[5] 0 -##reserved 0x1c[0:4] 0 +## reserved 0x1c[0:4] 0 ######################################################################## ## FLO_Max_byte (0x1d) Read ######################################################################## -##reserved 0x1d[6:7] 0 +## reserved 0x1d[6:7] 0 fmax_lo 0x1d[0:5] 0xA ######################################################################## ## IR_Cal_byte_1 (0x1e) Read @@ -249,12 +254,12 @@ ir_freqlow 0x1f[0:4] 0 ######################################################################## ## IR_Cal_byte_3 (0x20) Read ######################################################################## -##reserved 0x20[5:7] 0 +## reserved 0x20[5:7] 0 ir_freqmid 0x20[0:4] 0 ######################################################################## ## IR_Cal_byte_4 (0x21) Read ######################################################################## -##reserved 0x21[5:7] 0 +## reserved 0x21[5:7] 0 coarse_ir_freqhigh 0x21[4] 0 ir_freqhigh 0x21[0:3] 0 ######################################################################## @@ -270,8 +275,9 @@ agc_ovld_timer 0x22[0:1] 0 ######################################################################## ir_mixer_loop_off 0x23[7] 0 ir_mixer_do_step 0x23[5:6] 0 -##reserved 0x23[2:4] 0 -hi_pass 0x23[1] 0 disable, enable ## FIXME Logic Unclear +## reserved 0x23[2:4] 0 +## FIXME Logic Unclear +hi_pass 0x23[1] 0 disable, enable if_notch 0x23[0] 1 on, off ######################################################################## ## AGC1_byte_2 (0x24) Read @@ -285,9 +291,9 @@ agc1_gain 0x24[0:3] 8 ######################################################################## agc5_loop_off 0x25[7] 0 agc5_do_step 0x25[5:6] 0 -##reserved 0x25[4] 0 +## reserved 0x25[4] 0 force_agc5_gain 0x25[3] 0 -##reserved 0x25[2] 0 +## reserved 0x25[2] 0 agc5_gain 0x25[0:1] 2 ######################################################################## ## RF_Cal_byte_1 (0x26) Read @@ -335,7 +341,7 @@ rfcal_freq11 0x2b[0:1] 0 ## RF_Filter_byte_1 (0x2c) Read ######################################################################## rf_filter_bypass 0x2c[7] 0 -##reserved as 0 0x2c[6] 0 +## reserved as 0 0x2c[6] 0 agc2_loop_off 0x2c[5] 0 force_agc2_gain 0x2c[4] 0 rf_filter_gv 0x2c[2:3] 2 @@ -353,12 +359,12 @@ gain_taper 0x2e[0:5] 0 ## RF_Band_Pass_Filter_byte (0x2f) Read ######################################################################## rf_bpf_bypass 0x2f[7] 0 -##reserved 0x2f[3:6] 0 +## reserved 0x2f[3:6] 0 rf_bpf 0x2f[0:2] 0 ######################################################################## ## CP_Current_byte (0x30) Read ######################################################################## -##reserved 0x30[7] 0 +## reserved 0x30[7] 0 n_cp_current 0x30[0:6] 0x68 ######################################################################## ## AGC_Det_Out_byte (0x31) Read @@ -374,24 +380,26 @@ do_agc1 0x31[0] 0 ######################################################################## ## RF_AGC_Gain_byte_1 (0x32) Read ######################################################################## -#set $lna_gain_names = ', '.join(map(lambda x: {0: '', 1: 'm'}[3*x-12 < 0] + str(abs(3*x-12)) + 'db=' + str(x), range(0,10))) -##reserved 0x32[6:7] 0 +## reserved 0x32[6:7] 0 agc2_gain_read 0x32[4:5] 3 m11db, m8db, m5db, m2db -agc1_gain_read 0x32[0:3] 9 $lna_gain_names +<% lna_gain_names = ', '.join(map(lambda x: {0: '', 1: 'm'}[3*x-12 < 0] + str(abs(3*x-12)) + 'db=' + str(x), range(0,10))) %>\ +agc1_gain_read 0x32[0:3] 9 ${lna_gain_names} ######################################################################## ## RF_AGC_Gain_byte_2 (0x33) Read ######################################################################## -#set $top_agc3_read_names = ', '.join(map(lambda x: str(int(round(1.92*x+94))) + 'dbuvrms=' + str(x), range(0,8))) -##reserved 0x33[3:7] 0 -top_agc3_read 0x33[0:2] 0 $top_agc3_read_names +## reserved 0x33[3:7] 0 +<% top_agc3_read_names = ', '.join(map(lambda x: str(int(round(1.92*x+94))) + 'dbuvrms=' + str(x), range(0,8))) %>\ +top_agc3_read 0x33[0:2] 0 ${top_agc3_read_names} ######################################################################## ## IF_AGC_Gain_byte (0x34) Read ######################################################################## -#set $lpf_gain_names = ', '.join(map(lambda x: str(3*x) + 'db=' + str(x), range(0,4))) -#set $ir_mixer_names = ', '.join(map(lambda x: str(3*x+2) + 'db=' + str(x), range(0,5))) -##reserved 0x34[5:7] 0 -agc5_gain_read 0x34[3:4] 3 $lpf_gain_names -agc4_gain_read 0x34[0:2] 4 $ir_mixer_names +## reserved 0x34[5:7] 0 +<% + lpf_gain_names = ', '.join(map(lambda x: str(3*x) + 'db=' + str(x), range(0,4))) + ir_mixer_names = ', '.join(map(lambda x: str(3*x+2) + 'db=' + str(x), range(0,5))) +%>\ +agc5_gain_read 0x34[3:4] 3 ${lpf_gain_names} +agc4_gain_read 0x34[0:2] 4 ${ir_mixer_names} ######################################################################## ## Power_byte_1 (0x35) Read ######################################################################## @@ -399,9 +407,9 @@ rssi 0x35[0:7] 0 ######################################################################## ## Power_byte_2 (0x36) Read ######################################################################## -##reserved 0x36[6:7] 0 +## reserved 0x36[6:7] 0 rssi_av 0x36[5] 0 -##reserved 0x36[4] 0 +## reserved 0x36[4] 0 rssi_cap_reset_en 0x36[3] 1 rssi_cap_val 0x36[2] 1 rssi_ck_speed 0x36[1] 0 @@ -479,39 +487,30 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } void set_reg(boost::uint8_t addr, boost::uint8_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } """ -SPLIT_REGS_HELPER_TMPL="""\ -#for $divname in ['n','f'] -void set_$(divname)_divider(boost::uint32_t $divname){ - #for $regname in sorted(map(lambda r: r.get_name(), filter(lambda r: r.get_name().find(divname + '_divider') == 0, $regs))) - #end for -} -#end for -""" - if __name__ == '__main__': import common; common.generate( name='tda18272hnm_regs', diff --git a/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py b/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py index 73f7aa3db..9b8e1958f 100644..100755 --- a/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py +++ b/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py @@ -53,13 +53,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } diff --git a/host/lib/transport/CMakeLists.txt b/host/lib/transport/CMakeLists.txt index 5920f3d78..9ec8a5c0b 100644 --- a/host/lib/transport/CMakeLists.txt +++ b/host/lib/transport/CMakeLists.txt @@ -129,6 +129,7 @@ LIBUHD_APPEND_SOURCES( ${CMAKE_CURRENT_SOURCE_DIR}/if_addrs.cpp ${CMAKE_CURRENT_SOURCE_DIR}/udp_simple.cpp ${CMAKE_CURRENT_SOURCE_DIR}/nirio_zero_copy.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/chdr.cpp ) # Verbose Debug output for send/recv diff --git a/host/lib/transport/chdr.cpp b/host/lib/transport/chdr.cpp new file mode 100644 index 000000000..632887e56 --- /dev/null +++ b/host/lib/transport/chdr.cpp @@ -0,0 +1,182 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/transport/chdr.hpp> +#include <uhd/utils/byteswap.hpp> +#include <uhd/exception.hpp> + +//define the endian macros to convert integers +#ifdef BOOST_BIG_ENDIAN + #define BE_MACRO(x) (x) + #define LE_MACRO(x) uhd::byteswap(x) +#else + #define BE_MACRO(x) uhd::byteswap(x) + #define LE_MACRO(x) (x) +#endif + +using namespace uhd::transport::vrt; + +static const boost::uint32_t HDR_FLAG_TSF = (1 << 29); +static const boost::uint32_t HDR_FLAG_EOB = (1 << 28); +static const boost::uint32_t HDR_FLAG_ERROR = (1 << 28); + +/***************************************************************************/ +/* Packing */ +/***************************************************************************/ +/*! Translate the contents of \p if_packet_info into a 32-Bit word and return it. + */ +UHD_INLINE boost::uint32_t _hdr_pack_chdr( + if_packet_info_t &if_packet_info +) { + // Set fields in if_packet_info + if_packet_info.num_header_words32 = 2 + (if_packet_info.has_tsf ? 2 : 0); + if_packet_info.num_packet_words32 = + if_packet_info.num_header_words32 + + if_packet_info.num_payload_words32; + + boost::uint16_t pkt_length = + if_packet_info.num_payload_bytes + (4 * if_packet_info.num_header_words32); + boost::uint32_t chdr = 0 + // 2 Bits: Packet type + | (if_packet_info.packet_type << 30) + // 1 Bit: Has time + | (if_packet_info.has_tsf ? HDR_FLAG_TSF : 0) + // 1 Bit: EOB or Error + | ((if_packet_info.eob or if_packet_info.error) ? HDR_FLAG_EOB : 0) + // 12 Bits: Sequence number + | ((if_packet_info.packet_count & 0xFFF) << 16) + // 16 Bits: Total packet length + | pkt_length; + return chdr; +} + +void chdr::if_hdr_pack_be( + boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info +) { + // Write header and update if_packet_info + packet_buff[0] = BE_MACRO(_hdr_pack_chdr(if_packet_info)); + + // Write SID + packet_buff[1] = BE_MACRO(if_packet_info.sid); + + // Write time + if (if_packet_info.has_tsf) { + packet_buff[2] = BE_MACRO(boost::uint32_t(if_packet_info.tsf >> 32)); + packet_buff[3] = BE_MACRO(boost::uint32_t(if_packet_info.tsf >> 0)); + } +} + +void chdr::if_hdr_pack_le( + boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info +) { + // Write header and update if_packet_info + packet_buff[0] = LE_MACRO(_hdr_pack_chdr(if_packet_info)); + + // Write SID + packet_buff[1] = LE_MACRO(if_packet_info.sid); + + // Write time + if (if_packet_info.has_tsf) { + packet_buff[2] = LE_MACRO(boost::uint32_t(if_packet_info.tsf >> 32)); + packet_buff[3] = LE_MACRO(boost::uint32_t(if_packet_info.tsf >> 0)); + } +} + + +/***************************************************************************/ +/* Unpacking */ +/***************************************************************************/ +UHD_INLINE void _hdr_unpack_chdr( + const boost::uint32_t chdr, + if_packet_info_t &if_packet_info +) { + // Set constant members + if_packet_info.link_type = if_packet_info_t::LINK_TYPE_CHDR; + if_packet_info.has_cid = false; + if_packet_info.has_sid = true; + if_packet_info.has_tsi = false; + if_packet_info.has_tlr = false; + if_packet_info.sob = false; + + // Set configurable members + if_packet_info.has_tsf = (chdr & HDR_FLAG_TSF) > 0; + if_packet_info.packet_type = if_packet_info_t::packet_type_t((chdr >> 30) & 0x3); + if_packet_info.eob = (if_packet_info.packet_type == if_packet_info_t::PACKET_TYPE_DATA) + && ((chdr & HDR_FLAG_EOB) > 0); + if_packet_info.error = (if_packet_info.packet_type == if_packet_info_t::PACKET_TYPE_RESP) + && ((chdr & HDR_FLAG_ERROR) > 0); + if_packet_info.packet_count = (chdr >> 16) & 0xFFF; + + // Set packet length variables + if (if_packet_info.has_tsf) { + if_packet_info.num_header_words32 = 4; + } else { + if_packet_info.num_header_words32 = 2; + } + size_t pkt_size_bytes = (chdr & 0xFFFF); + size_t pkt_size_word32 = (pkt_size_bytes / 4) + ((pkt_size_bytes % 4) ? 1 : 0); + // Check lengths match: + if (pkt_size_word32 < if_packet_info.num_header_words32) { + throw uhd::value_error("Bad CHDR or invalid packet length"); + } + if (if_packet_info.num_packet_words32 < pkt_size_word32) { + throw uhd::value_error("Bad CHDR or packet fragment"); + } + if_packet_info.num_payload_bytes = pkt_size_bytes - (4 * if_packet_info.num_header_words32); + if_packet_info.num_payload_words32 = pkt_size_word32 - if_packet_info.num_header_words32; +} + +void chdr::if_hdr_unpack_be( + const boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info +) { + // Read header and update if_packet_info + boost::uint32_t chdr = BE_MACRO(packet_buff[0]); + _hdr_unpack_chdr(chdr, if_packet_info); + + // Read SID + if_packet_info.sid = BE_MACRO(packet_buff[1]); + + // Read time (has_tsf was updated earlier) + if (if_packet_info.has_tsf) { + if_packet_info.tsf = 0 + | boost::uint64_t(BE_MACRO(packet_buff[2])) << 32 + | BE_MACRO(packet_buff[3]); + } +} + +void chdr::if_hdr_unpack_le( + const boost::uint32_t *packet_buff, + if_packet_info_t &if_packet_info +) { + // Read header and update if_packet_info + boost::uint32_t chdr = LE_MACRO(packet_buff[0]); + _hdr_unpack_chdr(chdr, if_packet_info); + + // Read SID + if_packet_info.sid = LE_MACRO(packet_buff[1]); + + // Read time (has_tsf was updated earlier) + if (if_packet_info.has_tsf) { + if_packet_info.tsf = 0 + | boost::uint64_t(LE_MACRO(packet_buff[2])) << 32 + | LE_MACRO(packet_buff[3]); + } +} + diff --git a/host/lib/transport/gen_vrt_if_packet.py b/host/lib/transport/gen_vrt_if_packet.py index 98f6804ae..6723e3a4b 100644 --- a/host/lib/transport/gen_vrt_if_packet.py +++ b/host/lib/transport/gen_vrt_if_packet.py @@ -1,6 +1,6 @@ #!/usr/bin/env python # -# Copyright 2010-2013 Ettus Research LLC +# Copyright 2010-2013,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -25,26 +25,25 @@ metatdata into vrt headers and vrt headers into metadata. The generated code infers jump tables to speed-up the parsing time. """ -TMPL_TEXT = """ -#import time +TMPL_TEXT = """<% import time %> /*********************************************************************** - * This file was generated by $file on $time.strftime("%c") + * This file was generated by ${file} on ${time.strftime("%c")} **********************************************************************/ -\#include <uhd/exception.hpp> -\#include <uhd/transport/vrt_if_packet.hpp> -\#include <uhd/utils/byteswap.hpp> -\#include <boost/detail/endian.hpp> -\#include <vector> +#include <uhd/exception.hpp> +#include <uhd/transport/vrt_if_packet.hpp> +#include <uhd/utils/byteswap.hpp> +#include <boost/detail/endian.hpp> +#include <vector> //define the endian macros to convert integers -\#ifdef BOOST_BIG_ENDIAN - \#define BE_MACRO(x) (x) - \#define LE_MACRO(x) uhd::byteswap(x) -\#else - \#define BE_MACRO(x) uhd::byteswap(x) - \#define LE_MACRO(x) (x) -\#endif +#ifdef BOOST_BIG_ENDIAN + #define BE_MACRO(x) (x) + #define LE_MACRO(x) uhd::byteswap(x) +#else + #define BE_MACRO(x) uhd::byteswap(x) + #define LE_MACRO(x) (x) +#endif using namespace uhd; using namespace uhd::transport; @@ -59,13 +58,13 @@ static pred_table_type get_pred_unpack_table(void) pred_table_type table(1 << 9, 0); //only 9 bits useful here (20-28) for (size_t i = 0; i < table.size(); i++){ boost::uint32_t vrt_hdr_word = i << 20; - if(vrt_hdr_word & $hex(0x1 << 28)) table[i] |= $hex($sid_p); - if(vrt_hdr_word & $hex(0x1 << 27)) table[i] |= $hex($cid_p); - if(vrt_hdr_word & $hex(0x3 << 22)) table[i] |= $hex($tsi_p); - if(vrt_hdr_word & $hex(0x3 << 20)) table[i] |= $hex($tsf_p); - if(vrt_hdr_word & $hex(0x1 << 26)) table[i] |= $hex($tlr_p); - if(vrt_hdr_word & $hex(0x1 << 24)) table[i] |= $hex($eob_p); - if(vrt_hdr_word & $hex(0x1 << 25)) table[i] |= $hex($sob_p); + if(vrt_hdr_word & ${hex(0x1 << 28)}) table[i] |= ${hex(sid_p)}; + if(vrt_hdr_word & ${hex(0x1 << 27)}) table[i] |= ${hex(cid_p)}; + if(vrt_hdr_word & ${hex(0x3 << 22)}) table[i] |= ${hex(tsi_p)}; + if(vrt_hdr_word & ${hex(0x3 << 20)}) table[i] |= ${hex(tsf_p)}; + if(vrt_hdr_word & ${hex(0x1 << 26)}) table[i] |= ${hex(tlr_p)}; + if(vrt_hdr_word & ${hex(0x1 << 24)}) table[i] |= ${hex(eob_p)}; + if(vrt_hdr_word & ${hex(0x1 << 25)}) table[i] |= ${hex(sob_p)}; } return table; } @@ -105,13 +104,12 @@ UHD_INLINE static boost::uint32_t vrt_to_chdr(const boost::uint32_t vrt, const i } ######################################################################## -#def gen_code($XE_MACRO, $suffix) +<%def name="gen_code(XE_MACRO, suffix)"> ######################################################################## - /*********************************************************************** - * interal impl of packing VRT IF header only + * internal impl of packing VRT IF header only **********************************************************************/ -UHD_INLINE void __if_hdr_pack_$(suffix)( +UHD_INLINE void __if_hdr_pack_${suffix}( boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info, boost::uint32_t &vrt_hdr_word32 @@ -119,72 +117,53 @@ UHD_INLINE void __if_hdr_pack_$(suffix)( boost::uint32_t vrt_hdr_flags = 0; pred_type pred = 0; - if (if_packet_info.has_sid) pred |= $hex($sid_p); - if (if_packet_info.has_cid) pred |= $hex($cid_p); - if (if_packet_info.has_tsi) pred |= $hex($tsi_p); - if (if_packet_info.has_tsf) pred |= $hex($tsf_p); - if (if_packet_info.has_tlr) pred |= $hex($tlr_p); - if (if_packet_info.eob) pred |= $hex($eob_p); - if (if_packet_info.sob) pred |= $hex($sob_p); + if (if_packet_info.has_sid) pred |= ${hex(sid_p)}; + if (if_packet_info.has_cid) pred |= ${hex(cid_p)}; + if (if_packet_info.has_tsi) pred |= ${hex(tsi_p)}; + if (if_packet_info.has_tsf) pred |= ${hex(tsf_p)}; + if (if_packet_info.has_tlr) pred |= ${hex(tlr_p)}; + if (if_packet_info.eob) pred |= ${hex(eob_p)}; + if (if_packet_info.sob) pred |= ${hex(sob_p)}; switch(pred){ - #for $pred in range(2**7) - case $pred: - #set $num_header_words = 1 - #set $flags = 0 + % for pred in range(2**7): + case ${pred}:<% num_header_words = 1 %><% flags = 0 %> ########## Stream ID ########## - #if $pred & $sid_p - packet_buff[$num_header_words] = $(XE_MACRO)(if_packet_info.sid); - #set $num_header_words += 1 - #set $flags |= (0x1 << 28); - #end if + % if pred & sid_p: + packet_buff[${num_header_words}] = ${XE_MACRO}(if_packet_info.sid);<% num_header_words += 1 %><% flags |= (0x1 << 28) %> + % endif ########## Class ID ########## - #if $pred & $cid_p - packet_buff[$num_header_words] = 0; //not implemented - #set $num_header_words += 1 - packet_buff[$num_header_words] = 0; //not implemented - #set $num_header_words += 1 - #set $flags |= (0x1 << 27); - #end if + % if pred & cid_p: + packet_buff[${num_header_words}] = 0; //not implemented<% num_header_words += 1 %> + packet_buff[${num_header_words}] = 0; //not implemented<% num_header_words += 1 %><% flags |= (0x1 << 27) %> + % endif ########## Integer Time ########## - #if $pred & $tsi_p - packet_buff[$num_header_words] = $(XE_MACRO)(if_packet_info.tsi); - #set $num_header_words += 1 - #set $flags |= (0x3 << 22); - #end if + % if pred & tsi_p: + packet_buff[${num_header_words}] = ${XE_MACRO}(if_packet_info.tsi);<% num_header_words += 1 %><% flags |= (0x3 << 22) %> + % endif ########## Fractional Time ########## - #if $pred & $tsf_p - packet_buff[$num_header_words] = $(XE_MACRO)(boost::uint32_t(if_packet_info.tsf >> 32)); - #set $num_header_words += 1 - packet_buff[$num_header_words] = $(XE_MACRO)(boost::uint32_t(if_packet_info.tsf >> 0)); - #set $num_header_words += 1 - #set $flags |= (0x1 << 20); - #end if + % if pred & tsf_p: + packet_buff[${num_header_words}] = ${XE_MACRO}(boost::uint32_t(if_packet_info.tsf >> 32));<% num_header_words += 1 %> + packet_buff[${num_header_words}] = ${XE_MACRO}(boost::uint32_t(if_packet_info.tsf >> 0));<% num_header_words += 1 %><% flags |= (0x1 << 20) %> + % endif ########## Burst Flags ########## - #if $pred & $eob_p - #set $flags |= (0x1 << 24); - #end if - #if $pred & $sob_p - #set $flags |= (0x1 << 25); - #end if +<% if pred & eob_p: flags |= (0x1 << 24) %><% if pred & sob_p: flags |= (0x1 << 25) %> ########## Trailer ########## - #if $pred & $tlr_p + % if pred & tlr_p: { const size_t empty_bytes = if_packet_info.num_payload_words32*sizeof(boost::uint32_t) - if_packet_info.num_payload_bytes; if_packet_info.tlr = (0x3 << 22) | (occ_table[empty_bytes & 0x3] << 10); } - packet_buff[$num_header_words+if_packet_info.num_payload_words32] = $(XE_MACRO)(if_packet_info.tlr); - #set $flags |= (0x1 << 26); - #set $num_trailer_words = 1; - #else - #set $num_trailer_words = 0; - #end if + packet_buff[${num_header_words}+if_packet_info.num_payload_words32] = ${XE_MACRO}(if_packet_info.tlr);<% flags |= (0x1 << 26) %><% num_trailer_words = 1 %> + % else: +<% num_trailer_words = 0 %> + % endif ########## Variables ########## - if_packet_info.num_header_words32 = $num_header_words; - if_packet_info.num_packet_words32 = $($num_header_words + $num_trailer_words) + if_packet_info.num_payload_words32; - vrt_hdr_flags = $hex($flags); + if_packet_info.num_header_words32 = ${num_header_words}; + if_packet_info.num_packet_words32 = ${num_header_words + num_trailer_words} + if_packet_info.num_payload_words32; + vrt_hdr_flags = ${hex(flags)}; break; - #end for + % endfor } //fill in complete header word @@ -197,9 +176,9 @@ UHD_INLINE void __if_hdr_pack_$(suffix)( } /*********************************************************************** - * interal impl of unpacking VRT IF header only + * internal impl of unpacking VRT IF header only **********************************************************************/ -UHD_INLINE void __if_hdr_unpack_$(suffix)( +UHD_INLINE void __if_hdr_unpack_${suffix}( const boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info, const boost::uint32_t vrt_hdr_word32 @@ -219,86 +198,78 @@ UHD_INLINE void __if_hdr_unpack_$(suffix)( size_t empty_bytes = 0; switch(pred){ - #for $pred in range(2**7) - case $pred: - #set $has_time_spec = False - #set $num_header_words = 1 + % for pred in range(2**7): + case ${pred}:<% has_time_spec = False %><% num_header_words = 1 %> ########## Stream ID ########## - #if $pred & $sid_p + % if pred & sid_p: if_packet_info.has_sid = true; - if_packet_info.sid = $(XE_MACRO)(packet_buff[$num_header_words]); - #set $num_header_words += 1 - #else + if_packet_info.sid = ${XE_MACRO}(packet_buff[${num_header_words}]);<% num_header_words += 1 %> + % else: if_packet_info.has_sid = false; - #end if + % endif ########## Class ID ########## - #if $pred & $cid_p + % if pred & cid_p: if_packet_info.has_cid = true; - if_packet_info.cid = 0; //not implemented - #set $num_header_words += 2 - #else + if_packet_info.cid = 0; //not implemented<% num_header_words += 2 %> + % else: if_packet_info.has_cid = false; - #end if + % endif ########## Integer Time ########## - #if $pred & $tsi_p + % if pred & tsi_p: if_packet_info.has_tsi = true; - if_packet_info.tsi = $(XE_MACRO)(packet_buff[$num_header_words]); - #set $num_header_words += 1 - #else + if_packet_info.tsi = ${XE_MACRO}(packet_buff[${num_header_words}]); +<% num_header_words += 1 %> + % else: if_packet_info.has_tsi = false; - #end if + % endif ########## Fractional Time ########## - #if $pred & $tsf_p + % if pred & tsf_p: if_packet_info.has_tsf = true; - if_packet_info.tsf = boost::uint64_t($(XE_MACRO)(packet_buff[$num_header_words])) << 32; - #set $num_header_words += 1 - if_packet_info.tsf |= $(XE_MACRO)(packet_buff[$num_header_words]); - #set $num_header_words += 1 - #else + if_packet_info.tsf = boost::uint64_t(${XE_MACRO}(packet_buff[${num_header_words}])) << 32;<% num_header_words += 1 %> + if_packet_info.tsf |= ${XE_MACRO}(packet_buff[${num_header_words}]);<% num_header_words += 1 %> + % else: if_packet_info.has_tsf = false; - #end if + % endif ########## Burst Flags ########## - #if $pred & $eob_p + % if pred & eob_p: if_packet_info.eob = true; - #else + % else: if_packet_info.eob = false; - #end if - #if $pred & $sob_p + % endif + % if pred & sob_p: if_packet_info.sob = true; - #else + % else: if_packet_info.sob = false; - #end if + % endif ########## Trailer ########## - #if $pred & $tlr_p + % if pred & tlr_p: if_packet_info.has_tlr = true; - if_packet_info.tlr = $(XE_MACRO)(packet_buff[packet_words32-1]); - #set $num_trailer_words = 1; + if_packet_info.tlr = ${XE_MACRO}(packet_buff[packet_words32-1]);<% num_trailer_words = 1 %> { const int indicators = (if_packet_info.tlr >> 20) & (if_packet_info.tlr >> 8); if ((indicators & (1 << 0)) != 0) if_packet_info.eob = true; if ((indicators & (1 << 1)) != 0) if_packet_info.sob = true; empty_bytes = occ_table[(indicators >> 2) & 0x3]; } - #else - if_packet_info.has_tlr = false; - #set $num_trailer_words = 0; - #end if + % else: + if_packet_info.has_tlr = false;<% num_trailer_words = 0 %> + % endif ########## Variables ########## //another failure case - if (packet_words32 < $($num_header_words + $num_trailer_words)) + if (packet_words32 < ${num_header_words + num_trailer_words}) throw uhd::value_error("bad vrt header or invalid packet length"); - if_packet_info.num_header_words32 = $num_header_words; - if_packet_info.num_payload_words32 = packet_words32 - $($num_header_words + $num_trailer_words); + if_packet_info.num_header_words32 = ${num_header_words}; + if_packet_info.num_payload_words32 = packet_words32 - ${num_header_words + num_trailer_words}; if_packet_info.num_payload_bytes = if_packet_info.num_payload_words32*sizeof(boost::uint32_t) - empty_bytes; break; - #end for + % endfor } } /*********************************************************************** * link layer + VRT IF packing **********************************************************************/ -void vrt::if_hdr_pack_$(suffix)( +void vrt::if_hdr_pack_${suffix}( boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info ){ @@ -306,29 +277,29 @@ void vrt::if_hdr_pack_$(suffix)( switch (if_packet_info.link_type) { case if_packet_info_t::LINK_TYPE_NONE: - __if_hdr_pack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); - packet_buff[0] = $(XE_MACRO)(vrt_hdr_word32); + __if_hdr_pack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); + packet_buff[0] = ${XE_MACRO}(vrt_hdr_word32); break; case if_packet_info_t::LINK_TYPE_CHDR: { - __if_hdr_pack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); + __if_hdr_pack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); const boost::uint32_t chdr = vrt_to_chdr(vrt_hdr_word32, if_packet_info); - packet_buff[0] = $(XE_MACRO)(chdr); + packet_buff[0] = ${XE_MACRO}(chdr); break; } case if_packet_info_t::LINK_TYPE_VRLP: - __if_hdr_pack_$(suffix)(packet_buff+2, if_packet_info, vrt_hdr_word32); + __if_hdr_pack_${suffix}(packet_buff+2, if_packet_info, vrt_hdr_word32); if_packet_info.num_header_words32 += 2; if_packet_info.num_packet_words32 += 3; - packet_buff[0] = $(XE_MACRO)(VRLP); - packet_buff[1] = $(XE_MACRO)(boost::uint32_t( + packet_buff[0] = ${XE_MACRO}(VRLP); + packet_buff[1] = ${XE_MACRO}(boost::uint32_t( (if_packet_info.num_packet_words32 & 0xfffff) | ((if_packet_info.packet_count & 0xfff) << 20) )); - packet_buff[2] = $(XE_MACRO)(vrt_hdr_word32); - packet_buff[if_packet_info.num_packet_words32-1] = $(XE_MACRO)(VEND); + packet_buff[2] = ${XE_MACRO}(vrt_hdr_word32); + packet_buff[if_packet_info.num_packet_words32-1] = ${XE_MACRO}(VEND); break; } } @@ -336,7 +307,7 @@ void vrt::if_hdr_pack_$(suffix)( /*********************************************************************** * link layer + VRT IF unpacking **********************************************************************/ -void vrt::if_hdr_unpack_$(suffix)( +void vrt::if_hdr_unpack_${suffix}( const boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info ){ @@ -344,16 +315,16 @@ void vrt::if_hdr_unpack_$(suffix)( switch (if_packet_info.link_type) { case if_packet_info_t::LINK_TYPE_NONE: - vrt_hdr_word32 = $(XE_MACRO)(packet_buff[0]); - __if_hdr_unpack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); + vrt_hdr_word32 = ${XE_MACRO}(packet_buff[0]); + __if_hdr_unpack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); break; case if_packet_info_t::LINK_TYPE_CHDR: { - const boost::uint32_t chdr = $(XE_MACRO)(packet_buff[0]); + const boost::uint32_t chdr = ${XE_MACRO}(packet_buff[0]); vrt_hdr_word32 = chdr_to_vrt(chdr, if_packet_info); size_t packet_count = if_packet_info.packet_count; - __if_hdr_unpack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); + __if_hdr_unpack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); if_packet_info.num_payload_bytes -= (~chdr + 1) & 0x3; if_packet_info.packet_count = packet_count; break; @@ -361,12 +332,12 @@ void vrt::if_hdr_unpack_$(suffix)( case if_packet_info_t::LINK_TYPE_VRLP: { - if ($(XE_MACRO)(packet_buff[0]) != VRLP) throw uhd::value_error("bad vrl header VRLP"); - const boost::uint32_t vrl_hdr = $(XE_MACRO)(packet_buff[1]); - vrt_hdr_word32 = $(XE_MACRO)(packet_buff[2]); + if (${XE_MACRO}(packet_buff[0]) != VRLP) throw uhd::value_error("bad vrl header VRLP"); + const boost::uint32_t vrl_hdr = ${XE_MACRO}(packet_buff[1]); + vrt_hdr_word32 = ${XE_MACRO}(packet_buff[2]); if (if_packet_info.num_packet_words32 < (vrl_hdr & 0xfffff)) throw uhd::value_error("bad vrl header or packet fragment"); - if ($(XE_MACRO)(packet_buff[(vrl_hdr & 0xfffff)-1]) != VEND) throw uhd::value_error("bad vrl trailer VEND"); - __if_hdr_unpack_$(suffix)(packet_buff+2, if_packet_info, vrt_hdr_word32); + if (${XE_MACRO}(packet_buff[(vrl_hdr & 0xfffff)-1]) != VEND) throw uhd::value_error("bad vrl trailer VEND"); + __if_hdr_unpack_${suffix}(packet_buff+2, if_packet_info, vrt_hdr_word32); if_packet_info.num_header_words32 += 2; //add vrl header if_packet_info.packet_count = (vrl_hdr >> 20) & 0xfff; break; @@ -375,16 +346,16 @@ void vrt::if_hdr_unpack_$(suffix)( } ######################################################################## -#end def +</%def> ######################################################################## -$gen_code("BE_MACRO", "be") -$gen_code("LE_MACRO", "le") +${gen_code("BE_MACRO", "be")} +${gen_code("LE_MACRO", "le")} """ def parse_tmpl(_tmpl_text, **kwargs): - from Cheetah.Template import Template - return str(Template(_tmpl_text, kwargs)) + from mako.template import Template + return Template(_tmpl_text).render(**kwargs) if __name__ == '__main__': import sys diff --git a/host/lib/transport/libusb1_base.cpp b/host/lib/transport/libusb1_base.cpp index ae33cc036..0baf8dc76 100644 --- a/host/lib/transport/libusb1_base.cpp +++ b/host/lib/transport/libusb1_base.cpp @@ -345,15 +345,21 @@ libusb::special_handle::sptr libusb::special_handle::make(device::sptr dev){ std::vector<usb_device_handle::sptr> usb_device_handle::get_device_list( boost::uint16_t vid, boost::uint16_t pid ){ - std::vector<usb_device_handle::sptr> handles; + return usb_device_handle::get_device_list(std::vector<usb_device_handle::vid_pid_pair_t>(1,usb_device_handle::vid_pid_pair_t(vid,pid))); +} +std::vector<usb_device_handle::sptr> usb_device_handle::get_device_list(const std::vector<usb_device_handle::vid_pid_pair_t>& vid_pid_pair_list) +{ + std::vector<usb_device_handle::sptr> handles; libusb::device_list::sptr dev_list = libusb::device_list::make(); - for (size_t i = 0; i < dev_list->size(); i++){ - usb_device_handle::sptr handle = libusb::special_handle::make(dev_list->at(i)); - if (handle->get_vendor_id() == vid and handle->get_product_id() == pid){ - handles.push_back(handle); - } + for(size_t iter = 0; iter < vid_pid_pair_list.size(); ++iter) + { + for (size_t i = 0; i < dev_list->size(); i++){ + usb_device_handle::sptr handle = libusb::special_handle::make(dev_list->at(i)); + if (handle->get_vendor_id() == vid_pid_pair_list[iter].first and handle->get_product_id() == vid_pid_pair_list[iter].second){ + handles.push_back(handle); + } + } } - return handles; } diff --git a/host/lib/transport/nirio/lvbitx/process-lvbitx.py b/host/lib/transport/nirio/lvbitx/process-lvbitx.py index ab9625608..7887c3997 100755 --- a/host/lib/transport/nirio/lvbitx/process-lvbitx.py +++ b/host/lib/transport/nirio/lvbitx/process-lvbitx.py @@ -1,6 +1,6 @@ #!/usr/bin/python # -# Copyright 2013-2014 Ettus Research LLC +# Copyright 2013-2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -35,7 +35,7 @@ parser.add_option("--output-src-path", type="string", dest="output_src_path", he # Args if (len(args) < 1): - print 'ERROR: Please specify the input LVBITX file name' + print('ERROR: Please specify the input LVBITX file name') sys.exit(1) lvbitx_filename = args[0] @@ -44,16 +44,16 @@ autogen_src_path = os.path.abspath(options.output_src_path) if (options.output_s class_name = os.path.splitext(os.path.basename(input_filename))[0] if (not os.path.isfile(input_filename)): - print 'ERROR: FPGA File ' + input_filename + ' could not be accessed or is not a file.' + print('ERROR: FPGA File ' + input_filename + ' could not be accessed or is not a file.') sys.exit(1) if (options.merge_bin is not None and not os.path.isfile(os.path.abspath(options.merge_bin))): - print 'ERROR: FPGA Bin File ' + options.merge_bin + ' could not be accessed or is not a file.' + print('ERROR: FPGA Bin File ' + options.merge_bin + ' could not be accessed or is not a file.') sys.exit(1) if (not os.path.exists(autogen_src_path)): - print 'ERROR: Output path ' + autogen_src_path + ' could not be accessed.' + print('ERROR: Output path ' + autogen_src_path + ' could not be accessed.') sys.exit(1) if (options.output_lvbitx_path is not None and input_filename == os.path.join(autogen_src_path, class_name + '.lvbitx')): - print 'ERROR: Input and output LVBITX files were the same. Choose a difference input file or output path.' + print('ERROR: Input and output LVBITX files were the same. Choose a difference input file or output path.') sys.exit(1) # Get XML Tree Node @@ -122,7 +122,7 @@ def map_SubType_to_ScalarType(SubType): elif SubType == 'U64': ScalarType = 'RIO_SCALAR_TYPE_UQ' else: - print 'ERROR: No corresponding nirio_scalar_type_t value for SubType ' + SubType + ' .' + print('ERROR: No corresponding nirio_scalar_type_t value for SubType ' + SubType + ' .') sys.exit(1) return ScalarType; @@ -187,7 +187,7 @@ codegen_transform['lvbitx_signature'] = str.upper(root.find('SignatureRegister') # Write BIN file bitstream = base64.b64decode(root.find('Bitstream').text) if (options.output_lvbitx_path is not None and hashlib.md5(bitstream).hexdigest() != root.find('BitstreamMD5').text): - print 'ERROR: The MD5 sum for the output LVBITX was incorrect. Make sure that the bitstream in the input LVBITX or BIN file is valid.' + print('ERROR: The MD5 sum for the output LVBITX was incorrect. Make sure that the bitstream in the input LVBITX or BIN file is valid.') sys.exit(1) if (options.output_bin): fpga_bin_file = open(os.path.join(options.output_lvbitx_path, class_name + '.bin'), 'w') diff --git a/host/lib/transport/nirio/rpc/rpc_client.cpp b/host/lib/transport/nirio/rpc/rpc_client.cpp index cf8e9c1a9..48f47cfae 100644 --- a/host/lib/transport/nirio/rpc/rpc_client.cpp +++ b/host/lib/transport/nirio/rpc/rpc_client.cpp @@ -52,7 +52,7 @@ rpc_client::rpc_client ( //- address_configured: Only return addresses if a non-loopback address is configured for the system. //- numeric_host: No name resolution should be attempted for host //- numeric_service: No name resolution should be attempted for service - tcp::resolver::query::flags query_flags; + tcp::resolver::query::flags query_flags = tcp::resolver::query::passive; tcp::resolver::query query(tcp::v4(), server, port, query_flags); tcp::resolver::iterator iterator = resolver.resolve(query); diff --git a/host/lib/transport/super_recv_packet_handler.hpp b/host/lib/transport/super_recv_packet_handler.hpp index 5c84327a4..c3c2b8e97 100644 --- a/host/lib/transport/super_recv_packet_handler.hpp +++ b/host/lib/transport/super_recv_packet_handler.hpp @@ -147,7 +147,7 @@ public: */ void set_xport_chan_get_buff(const size_t xport_chan, const get_buff_type &get_buff, const bool flush = false){ if (flush){ - while (get_buff(0.0)); + while (get_buff(0.0)) {}; } _props.at(xport_chan).get_buff = get_buff; } diff --git a/host/lib/types/CMakeLists.txt b/host/lib/types/CMakeLists.txt index f19043c1e..5e97628f0 100644 --- a/host/lib/types/CMakeLists.txt +++ b/host/lib/types/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2011-2013 Ettus Research LLC +# Copyright 2011-2013,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -86,8 +86,11 @@ LIBUHD_APPEND_SOURCES( ${CMAKE_CURRENT_SOURCE_DIR}/ranges.cpp ${CMAKE_CURRENT_SOURCE_DIR}/sensors.cpp ${CMAKE_CURRENT_SOURCE_DIR}/serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/sid.cpp ${CMAKE_CURRENT_SOURCE_DIR}/time_spec.cpp ${CMAKE_CURRENT_SOURCE_DIR}/tune.cpp ${CMAKE_CURRENT_SOURCE_DIR}/types.cpp ${CMAKE_CURRENT_SOURCE_DIR}/wb_iface.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filters.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/byte_vector.cpp ) diff --git a/host/lib/types/byte_vector.cpp b/host/lib/types/byte_vector.cpp new file mode 100644 index 000000000..071cdb8cb --- /dev/null +++ b/host/lib/types/byte_vector.cpp @@ -0,0 +1,42 @@ +// +// Copyright 2015 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <boost/foreach.hpp> + +#include <uhd/types/byte_vector.hpp> + +namespace uhd{ + +std::string bytes_to_string(const byte_vector_t &bytes){ + std::string out; + BOOST_FOREACH(boost::uint8_t byte, bytes){ + if (byte < 32 or byte > 127) return out; + out += byte; + } + return out; +} + +byte_vector_t string_to_bytes(const std::string &str, size_t max_length){ + byte_vector_t bytes; + for (size_t i = 0; i < std::min(str.size(), max_length); i++){ + bytes.push_back(str[i]); + } + if (bytes.size() < max_length - 1) bytes.push_back('\0'); + return bytes; +} + +} /* namespace uhd */ diff --git a/host/lib/types/filters.cpp b/host/lib/types/filters.cpp new file mode 100644 index 000000000..4ee06491f --- /dev/null +++ b/host/lib/types/filters.cpp @@ -0,0 +1,74 @@ +// +// Copyright 2015 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/types/filters.hpp> + +using namespace uhd; + +std::ostream& uhd::operator<<(std::ostream& os, filter_info_base& f) +{ + return os << f.to_pp_string(); +} + +std::string filter_info_base::to_pp_string() +{ + std::ostringstream os; + os << "[filter_info_base]" << std::endl; + switch(_type){ + case ANALOG_LOW_PASS: + os << "type: " << "Analog Low-pass" << std::endl; + break; + case ANALOG_BAND_PASS: + os << "type: " << "Analog Band-pass" << std::endl; + break; + case DIGITAL_I16: + os << "type: " << "Digital (i16)" << std::endl; + break; + case DIGITAL_FIR_I16: + os << "type: " << "Digital FIR (i16)" << std::endl; + break; + default: + os << "type: " << "Unknown type!" << std::endl; + break; + } + + os << "bypass enable: " << _bypass << std::endl + <<"position index: " << _position_index << std::endl; + + std::string str = os.str(); + return str; +} + +std::string analog_filter_base::to_pp_string() +{ + std::ostringstream os; + os << filter_info_base::to_pp_string() << + "\t[analog_filter_base]" << std::endl << + "\tdesc: " << _analog_type << std::endl; + return std::string(os.str()); + +} + +std::string analog_filter_lp::to_pp_string() +{ + std::ostringstream os; + os << analog_filter_base::to_pp_string() << + "\t\t[analog_filter_lp]" << std::endl << + "\t\tcutoff: " << _cutoff << std::endl << + "\t\trolloff: " << _rolloff << std::endl; + return std::string(os.str()); +} diff --git a/host/lib/types/sid.cpp b/host/lib/types/sid.cpp new file mode 100644 index 000000000..2fc3781cf --- /dev/null +++ b/host/lib/types/sid.cpp @@ -0,0 +1,153 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <boost/format.hpp> +#include <boost/regex.hpp> +#include <boost/lexical_cast.hpp> +#include <uhd/exception.hpp> +#include <uhd/types/sid.hpp> +#include <uhd/utils/cast.hpp> + +using namespace uhd; + +sid_t::sid_t() + : _sid(0x0000), _set(false) +{ +} + +sid_t::sid_t(boost::uint32_t sid) + : _sid(sid), _set(true) +{ +} + +sid_t::sid_t(boost::uint8_t src_addr, boost::uint8_t src_ep, boost::uint8_t dst_addr, boost::uint8_t dst_ep) + : _sid(0x0000), _set(true) +{ + set_src_addr(src_addr); + set_src_endpoint(src_ep); + set_dst_addr(dst_addr); + set_dst_endpoint(dst_ep); +} + +sid_t::sid_t(const std::string &sid_str) + : _sid(0x0000), _set(false) +{ + set_from_str(sid_str); +} + +std::string sid_t::to_pp_string() const +{ + if (not _set) { + return "x.x>x.x"; + } + return str(boost::format("%d.%d>%d.%d") + % get_src_addr() + % get_src_endpoint() + % get_dst_addr() + % get_dst_endpoint() + ); +} + +std::string sid_t::to_pp_string_hex() const +{ + if (not _set) { + return "xx:xx>xx:xx"; + } + return str(boost::format("%02x:%02x>%02x:%02x") + % get_src_addr() + % get_src_endpoint() + % get_dst_addr() + % get_dst_endpoint() + ); +} + + +void sid_t::set_sid(boost::uint32_t new_sid) +{ + _set = true; + _sid = new_sid; +} + +void sid_t::set_from_str(const std::string &sid_str) +{ + const std::string dec_regex = "(\\d{1,3})\\.(\\d{1,3})[.:/><](\\d{1,3})\\.(\\d{1,3})"; + const std::string hex_regex = "([[:xdigit:]]{2}):([[:xdigit:]]{2})[.:/><]([[:xdigit:]]{2}):([[:xdigit:]]{2})"; + + boost::cmatch matches; + if (boost::regex_match(sid_str.c_str(), matches, boost::regex(dec_regex))) { + set_src_addr(boost::lexical_cast<size_t>(matches[1])); + set_src_endpoint(boost::lexical_cast<size_t>(matches[2])); + set_dst_addr(boost::lexical_cast<size_t>(matches[3])); + set_dst_endpoint(boost::lexical_cast<size_t>(matches[4])); + return; + } + + if (boost::regex_match(sid_str.c_str(), matches, boost::regex(hex_regex))) { + set_src_addr(uhd::cast::hexstr_cast<size_t>(matches[1])); + set_src_endpoint(uhd::cast::hexstr_cast<size_t>(matches[2])); + set_dst_addr(uhd::cast::hexstr_cast<size_t>(matches[3])); + set_dst_endpoint(uhd::cast::hexstr_cast<size_t>(matches[4])); + return; + } + + throw uhd::value_error(str(boost::format("Invalid SID representation: %s") % sid_str)); +} + +void sid_t::set_src(boost::uint32_t new_addr) { + set_sid((_sid & 0x0000FFFF) | ((new_addr & 0xFFFF) << 16)); +} + +void sid_t::set_dst(boost::uint32_t new_addr) { + set_sid((_sid & 0xFFFF0000) | (new_addr & 0xFFFF)); +} + +void sid_t::set_src_addr(boost::uint32_t new_addr) { + set_sid((_sid & 0x00FFFFFF) | ((new_addr & 0xFF) << 24)); +} + +void sid_t::set_src_endpoint(boost::uint32_t new_addr) { + set_sid((_sid & 0xFF00FFFF) | ((new_addr & 0xFF) << 16)); +} + +void sid_t::set_dst_addr(boost::uint32_t new_addr) { + set_sid((_sid & 0xFFFF00FF) | ((new_addr & 0xFF) << 8)); +} + +void sid_t::set_dst_endpoint(boost::uint32_t new_addr) { + set_sid((_sid & 0xFFFFFF00) | ((new_addr & 0xFF) << 0)); +} + +void sid_t::set_dst_xbarport(boost::uint32_t new_xbarport) +{ + set_sid((_sid & 0xFFFFFF0F) | ((new_xbarport & 0xF) << 4)); +} + +void sid_t::set_dst_blockport(boost::uint32_t new_blockport) +{ + set_sid((_sid & 0xFFFFFFF0) | ((new_blockport & 0xF) << 0)); +} + +sid_t sid_t::reversed() +{ + return sid_t((get_dst() << 16) | get_src()); +} + +void sid_t::reverse() +{ + set_sid((get_dst() << 16) | get_src()); +} + diff --git a/host/lib/usrp/b200/b200_impl.cpp b/host/lib/usrp/b200/b200_impl.cpp index 0409adf30..7c672fd46 100644 --- a/host/lib/usrp/b200/b200_impl.cpp +++ b/host/lib/usrp/b200/b200_impl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2012-2014 Ettus Research LLC +// Copyright 2012-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -104,14 +104,16 @@ static device_addrs_t b200_find(const device_addr_t &hint) if (hint_i.has_key("addr") || hint_i.has_key("resource")) return b200_addrs; } - boost::uint16_t vid, pid; + size_t found = 0; + std::vector<usb_device_handle::vid_pid_pair_t> vid_pid_pair_list;//vid pid pair search list for devices. if(hint.has_key("vid") && hint.has_key("pid") && hint.has_key("type") && hint["type"] == "b200") { - vid = uhd::cast::hexstr_cast<boost::uint16_t>(hint.get("vid")); - pid = uhd::cast::hexstr_cast<boost::uint16_t>(hint.get("pid")); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(uhd::cast::hexstr_cast<boost::uint16_t>(hint.get("vid")), + uhd::cast::hexstr_cast<boost::uint16_t>(hint.get("pid")))); } else { - vid = B200_VENDOR_ID; - pid = B200_PRODUCT_ID; + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_ID, B200_PRODUCT_ID)); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_NI_ID, B200_PRODUCT_NI_ID)); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_NI_ID, B210_PRODUCT_NI_ID)); } // Important note: @@ -121,8 +123,9 @@ static device_addrs_t b200_find(const device_addr_t &hint) // This requirement is a courtesy of libusb1.0 on windows. //find the usrps and load firmware - size_t found = 0; - BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { + std::vector<usb_device_handle::sptr> uhd_usb_device_vector = usb_device_handle::get_device_list(vid_pid_pair_list); + + BOOST_FOREACH(usb_device_handle::sptr handle, uhd_usb_device_vector) { //extract the firmware path for the b200 std::string b200_fw_image; try{ @@ -153,7 +156,7 @@ static device_addrs_t b200_find(const device_addr_t &hint) //search for the device until found or timeout while (boost::get_system_time() < timeout_time and b200_addrs.empty() and found != 0) { - BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) + BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid_pid_pair_list)) { usb_control::sptr control; try{control = usb_control::make(handle, 0);} @@ -213,13 +216,50 @@ b200_impl::b200_impl(const device_addr_t &device_addr) : //try to match the given device address with something on the USB bus boost::uint16_t vid = B200_VENDOR_ID; boost::uint16_t pid = B200_PRODUCT_ID; + bool specified_vid = false; + bool specified_pid = false; + if (device_addr.has_key("vid")) + { vid = uhd::cast::hexstr_cast<boost::uint16_t>(device_addr.get("vid")); + specified_vid = true; + } + if (device_addr.has_key("pid")) + { pid = uhd::cast::hexstr_cast<boost::uint16_t>(device_addr.get("pid")); + specified_pid = true; + } + + std::vector<usb_device_handle::vid_pid_pair_t> vid_pid_pair_list;//search list for devices. + + // Search only for specified VID and PID if both specified + if (specified_vid && specified_pid) + { + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(vid,pid)); + } + // Search for all supported PIDs limited to specified VID if only VID specified + else if (specified_vid) + { + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(vid,B200_PRODUCT_ID)); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(vid,B200_PRODUCT_NI_ID)); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(vid,B210_PRODUCT_NI_ID)); + } + // Search for all supported VIDs limited to specified PID if only PID specified + else if (specified_pid) + { + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_ID,pid)); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_NI_ID,pid)); + } + // Search for all supported devices if neither VID nor PID specified + else + { + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_ID,B200_PRODUCT_ID)); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_NI_ID,B200_PRODUCT_NI_ID)); + vid_pid_pair_list.push_back(usb_device_handle::vid_pid_pair_t(B200_VENDOR_NI_ID,B210_PRODUCT_NI_ID)); + } - std::vector<usb_device_handle::sptr> device_list = - usb_device_handle::get_device_list(vid, pid); + std::vector<usb_device_handle::sptr> device_list = usb_device_handle::get_device_list(vid_pid_pair_list); //locate the matching handle in the device list usb_device_handle::sptr handle; @@ -447,6 +487,7 @@ b200_impl::b200_impl(const device_addr_t &device_addr) : .publish(boost::bind(&b200_impl::get_tick_rate, this)) .subscribe(boost::bind(&b200_impl::update_tick_rate, this, _1)); _tree->create<time_spec_t>(mb_path / "time" / "cmd"); + _tree->create<bool>(mb_path / "auto_tick_rate").set(false); //////////////////////////////////////////////////////////////////// // and do the misc mboard sensors @@ -512,6 +553,19 @@ b200_impl::b200_impl(const device_addr_t &device_addr) : _tree->create<std::vector<std::string> >(mb_path / "clock_source" / "options").set(clock_sources); //////////////////////////////////////////////////////////////////// + // front panel gpio + //////////////////////////////////////////////////////////////////// + _radio_perifs[0].fp_gpio = gpio_core_200::make(_radio_perifs[0].ctrl, TOREG(SR_FP_GPIO), RB32_FP_GPIO); + BOOST_FOREACH(const gpio_attr_map_t::value_type attr, gpio_attr_map) + { + _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / attr.second) + .set(0) + .subscribe(boost::bind(&b200_impl::set_fp_gpio, this, _radio_perifs[0].fp_gpio, attr.first, _1)); + } + _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / "READBACK") + .publish(boost::bind(&b200_impl::get_fp_gpio, this, _radio_perifs[0].fp_gpio)); + + //////////////////////////////////////////////////////////////////// // dboard eeproms but not really //////////////////////////////////////////////////////////////////// dboard_eeprom_t db_eeprom; @@ -549,6 +603,11 @@ b200_impl::b200_impl(const device_addr_t &device_addr) : _radio_perifs[i].ddc->set_host_rate(default_tick_rate / B200_DEFAULT_DECIM); _radio_perifs[i].duc->set_host_rate(default_tick_rate / B200_DEFAULT_INTERP); } + // We can automatically choose a master clock rate, but not if the user specifies one + _tree->access<bool>(mb_path / "auto_tick_rate").set(not device_addr.has_key("master_clock_rate")); + if (not device_addr.has_key("master_clock_rate")) { + UHD_MSG(status) << "Setting master clock rate selection to 'automatic'." << std::endl; + } //GPS installed: use external ref, time, and init time spec if (_gps and _gps->gps_detected()) @@ -613,7 +672,7 @@ void b200_impl::setup_radio(const size_t dspno) .publish(boost::bind(&rx_dsp_core_3000::get_host_rates, perif.ddc)); _tree->create<double>(rx_dsp_path / "rate" / "value") .set(0.0) // We can only load a sensible value after the tick rate was set - .coerce(boost::bind(&rx_dsp_core_3000::set_host_rate, perif.ddc, _1)) + .coerce(boost::bind(&b200_impl::coerce_rx_samp_rate, this, perif.ddc, dspno, _1)) .subscribe(boost::bind(&b200_impl::update_rx_samp_rate, this, dspno, _1)) ; _tree->create<double>(rx_dsp_path / "freq" / "value") @@ -638,7 +697,7 @@ void b200_impl::setup_radio(const size_t dspno) .publish(boost::bind(&tx_dsp_core_3000::get_host_rates, perif.duc)); _tree->create<double>(tx_dsp_path / "rate" / "value") .set(0.0) // We can only load a sensible value after the tick rate was set - .coerce(boost::bind(&tx_dsp_core_3000::set_host_rate, perif.duc, _1)) + .coerce(boost::bind(&b200_impl::coerce_tx_samp_rate, this, perif.duc, dspno, _1)) .subscribe(boost::bind(&b200_impl::update_tx_samp_rate, this, dspno, _1)) ; _tree->create<double>(tx_dsp_path / "freq" / "value") @@ -682,7 +741,7 @@ void b200_impl::setup_radio(const size_t dspno) _tree->create<bool>(rf_fe_path / "use_lo_offset").set(false); _tree->create<double>(rf_fe_path / "bandwidth" / "value") .coerce(boost::bind(&ad9361_ctrl::set_bw_filter, _codec_ctrl, key, _1)) - .set(40e6); + .set(56e6); _tree->create<meta_range_t>(rf_fe_path / "bandwidth" / "range") .publish(boost::bind(&ad9361_ctrl::get_bw_filter_range, key)); _tree->create<double>(rf_fe_path / "freq" / "value") @@ -692,8 +751,29 @@ void b200_impl::setup_radio(const size_t dspno) .set(B200_DEFAULT_FREQ); _tree->create<meta_range_t>(rf_fe_path / "freq" / "range") .publish(boost::bind(&ad9361_ctrl::get_rf_freq_range)); + _tree->create<sensor_value_t>(rf_fe_path / "sensors" / "temp") + .publish(boost::bind(&ad9361_ctrl::get_temperature, _codec_ctrl)); //setup RX related stuff + if(direction) + { + _tree->create<bool>(rf_fe_path / "dc_offset" / "enable" ) + .subscribe(boost::bind(&ad9361_ctrl::set_dc_offset_auto, _codec_ctrl, key, _1)).set(true); + + _tree->create<bool>(rf_fe_path / "iq_balance" / "enable" ) + .subscribe(boost::bind(&ad9361_ctrl::set_iq_balance_auto, _codec_ctrl, key, _1)).set(true); + } + + //add all frontend filters + std::vector<std::string> filter_names = _codec_ctrl->get_filter_names(key); + for(size_t i = 0;i < filter_names.size(); i++) + { + _tree->create<filter_info_base::sptr>(rf_fe_path / "filters" / filter_names[i] / "value" ) + .publish(boost::bind(&ad9361_ctrl::get_filter, _codec_ctrl, key, filter_names[i])) + .subscribe(boost::bind(&ad9361_ctrl::set_filter, _codec_ctrl, key, filter_names[i], _1)); + } + + //setup antenna stuff if (key[0] == 'R') { static const std::vector<std::string> ants = boost::assign::list_of("TX/RX")("RX2"); @@ -703,6 +783,16 @@ void b200_impl::setup_radio(const size_t dspno) .set("RX2"); _tree->create<sensor_value_t>(rf_fe_path / "sensors" / "rssi") .publish(boost::bind(&ad9361_ctrl::get_rssi, _codec_ctrl, key)); + + //AGC setup + const std::list<std::string> mode_strings = boost::assign::list_of("slow")("fast"); + _tree->create<bool>(rf_fe_path / "gain" / "agc" / "enable") + .subscribe(boost::bind((&ad9361_ctrl::set_agc), _codec_ctrl, key, _1)) + .set(false); + _tree->create<std::string>(rf_fe_path / "gain" / "agc" / "mode" / "value") + .subscribe(boost::bind((&ad9361_ctrl::set_agc_mode), _codec_ctrl, key, _1)).set(mode_strings.front()); + _tree->create<std::list<std::string> >(rf_fe_path / "gain" / "agc" / "mode" / "options") + .set(mode_strings); } if (key[0] == 'T') { @@ -760,7 +850,7 @@ void b200_impl::codec_loopback_self_test(wb_iface::sptr iface) /*********************************************************************** * Sample and tick rate comprehension below **********************************************************************/ -void b200_impl::enforce_tick_rate_limits(size_t chan_count, double tick_rate, const char* direction /*= NULL*/) +void b200_impl::enforce_tick_rate_limits(size_t chan_count, double tick_rate, const std::string &direction /*= ""*/) { const size_t max_chans = 2; if (chan_count > max_chans) @@ -768,7 +858,7 @@ void b200_impl::enforce_tick_rate_limits(size_t chan_count, double tick_rate, co throw uhd::value_error(boost::str( boost::format("cannot not setup %d %s channels (maximum is %d)") % chan_count - % (direction ? direction : "data") + % (direction.empty() ? "data" : direction) % max_chans )); } @@ -782,20 +872,26 @@ void b200_impl::enforce_tick_rate_limits(size_t chan_count, double tick_rate, co % (tick_rate/1e6) % (max_tick_rate/1e6) % chan_count - % (direction ? direction : "data") + % (direction.empty() ? "data" : direction) )); } } } -double b200_impl::set_tick_rate(const double rate) +double b200_impl::set_tick_rate(const double new_tick_rate) { - UHD_MSG(status) << (boost::format("Asking for clock rate %.6f MHz\n") % (rate/1e6)); - - check_tick_rate_with_current_streamers(rate); // Defined in b200_io_impl.cpp + UHD_MSG(status) << (boost::format("Asking for clock rate %.6f MHz... ") % (new_tick_rate/1e6)) << std::flush; + check_tick_rate_with_current_streamers(new_tick_rate); // Defined in b200_io_impl.cpp + + // Make sure the clock rate is actually changed before doing + // the full Monty of setting regs and loopback tests etc. + if (std::abs(new_tick_rate - _tick_rate) < 1.0) { + UHD_MSG(status) << "OK" << std::endl; + return _tick_rate; + } - _tick_rate = _codec_ctrl->set_clock_rate(rate); - UHD_MSG(status) << (boost::format("Actually got clock rate %.6f MHz\n") % (_tick_rate/1e6)); + _tick_rate = _codec_ctrl->set_clock_rate(new_tick_rate); + UHD_MSG(status) << std::endl << (boost::format("Actually got clock rate %.6f MHz.") % (_tick_rate/1e6)) << std::endl; //reset after clock rate change this->reset_codec_dcm(); @@ -856,6 +952,26 @@ void b200_impl::set_mb_eeprom(const uhd::usrp::mboard_eeprom_t &mb_eeprom) } +boost::uint32_t b200_impl::get_fp_gpio(gpio_core_200::sptr gpio) +{ + return boost::uint32_t(gpio->read_gpio(dboard_iface::UNIT_RX)); +} + +void b200_impl::set_fp_gpio(gpio_core_200::sptr gpio, const gpio_attr_t attr, const boost::uint32_t value) +{ + switch (attr) + { + case GPIO_CTRL: return gpio->set_pin_ctrl(dboard_iface::UNIT_RX, value); + case GPIO_DDR: return gpio->set_gpio_ddr(dboard_iface::UNIT_RX, value); + case GPIO_OUT: return gpio->set_gpio_out(dboard_iface::UNIT_RX, value); + case GPIO_ATR_0X: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, value); + case GPIO_ATR_RX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, value); + case GPIO_ATR_TX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, value); + case GPIO_ATR_XX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, value); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + /*********************************************************************** * Reference time and clock **********************************************************************/ diff --git a/host/lib/usrp/b200/b200_impl.hpp b/host/lib/usrp/b200/b200_impl.hpp index 65796d1a4..11c3da0d9 100644 --- a/host/lib/usrp/b200/b200_impl.hpp +++ b/host/lib/usrp/b200/b200_impl.hpp @@ -1,5 +1,5 @@ // -// Copyright 2012-2013 Ettus Research LLC +// Copyright 2012-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -45,9 +45,9 @@ #include <uhd/transport/bounded_buffer.hpp> #include <boost/weak_ptr.hpp> #include "recv_packet_demuxer_3000.hpp" -static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 7; +static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 8; static const boost::uint8_t B200_FW_COMPAT_NUM_MINOR = 0; -static const boost::uint16_t B200_FPGA_COMPAT_NUM = 8; +static const boost::uint16_t B200_FPGA_COMPAT_NUM = 9; static const double B200_BUS_CLOCK_RATE = 100e6; static const double B200_DEFAULT_TICK_RATE = 32e6; static const double B200_DEFAULT_FREQ = 100e6; // Hz @@ -98,7 +98,13 @@ public: uhd::rx_streamer::sptr get_rx_stream(const uhd::stream_args_t &args); uhd::tx_streamer::sptr get_tx_stream(const uhd::stream_args_t &args); bool recv_async_msg(uhd::async_metadata_t &, double); - void check_streamer_args(const uhd::stream_args_t &args, double tick_rate, const char* direction = NULL); + + //! Check that the combination of stream args and tick rate are valid. + // + // Basically figures out the arguments for enforce_tick_rate_limits() + // and calls said method. If arguments are invalid, throws a + // uhd::value_error. + void check_streamer_args(const uhd::stream_args_t &args, double tick_rate, const std::string &direction = ""); private: b200_type_t _b200_type; @@ -154,6 +160,7 @@ private: { radio_ctrl_core_3000::sptr ctrl; gpio_core_200_32wo::sptr atr; + gpio_core_200::sptr fp_gpio; time_core_3000::sptr time64; rx_vita_core_3000::sptr framer; rx_dsp_core_3000::sptr ddc; @@ -200,14 +207,63 @@ private: void update_enables(void); void update_atrs(void); + boost::uint32_t get_fp_gpio(gpio_core_200::sptr); + void set_fp_gpio(gpio_core_200::sptr, const gpio_attr_t, const boost::uint32_t); + double _tick_rate; double get_tick_rate(void){return _tick_rate;} double set_tick_rate(const double rate); + + /*! \brief Choose a tick rate (master clock rate) that works well for the given sampling rate. + * + * This function will try and choose a master clock rate automatically. + * See the function definition for details on the algorithm. + * + * The chosen tick rate is the largest multiple of two that is smaler + * than the max tick rate. + * The base rate is either given explicitly, or is the lcm() of the tx + * and rx sampling rates. In that case, it reads the rates directly + * from the property tree. It also tries to guess the number of channels + * (for the max possible tick rate) by checking the available streamers. + * This value, too, can explicitly be given. + * + * \param rate If this is given, it will be used as a minimum rate, or + * argument to lcm(). + * \param tree_dsp_path The sampling rate from this property tree path + * will be ignored. + * \param num_chans If given, specifies the number of channels. + */ + void set_auto_tick_rate( + const double rate=0, + const uhd::fs_path &tree_dsp_path="", + size_t num_chans=0 + ); + void update_tick_rate(const double); - void enforce_tick_rate_limits(size_t chan_count, double tick_rate, const char* direction = NULL); + + /*! Check if \p tick_rate works with \p chan_count channels. + * + * Throws a uhd::value_error if not. + */ + void enforce_tick_rate_limits(size_t chan_count, double tick_rate, const std::string &direction = ""); void check_tick_rate_with_current_streamers(double rate); + /*! Return the max number of channels on active rx_streamer or tx_streamer objects associated with this device. + * + * \param direction Set to "TX" to only check tx_streamers, "RX" to only check + * rx_streamers. Any other value will check if \e any active + * streamers are available. + * \return Return the number of tx streamers (direction=="TX"), the number of rx + * streamers (direction=="RX") or the total number of streamers. + */ + size_t max_chan_count(const std::string &direction=""); + + //! Coercer, attached to the "rate/value" property on the rx dsps. + double coerce_rx_samp_rate(rx_dsp_core_3000::sptr, size_t, const double); void update_rx_samp_rate(const size_t, const double); + + //! Coercer, attached to the "rate/value" property on the tx dsps. + double coerce_tx_samp_rate(tx_dsp_core_3000::sptr, size_t, const double); void update_tx_samp_rate(const size_t, const double); }; diff --git a/host/lib/usrp/b200/b200_io_impl.cpp b/host/lib/usrp/b200/b200_io_impl.cpp index 1e11e7ff6..c4e04f70a 100644 --- a/host/lib/usrp/b200/b200_io_impl.cpp +++ b/host/lib/usrp/b200/b200_io_impl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2012-2013 Ettus Research LLC +// Copyright 2012-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -21,8 +21,10 @@ #include "../../transport/super_recv_packet_handler.hpp" #include "../../transport/super_send_packet_handler.hpp" #include "async_packet_handler.hpp" +#include <uhd/utils/math.hpp> #include <boost/bind.hpp> #include <boost/make_shared.hpp> +#include <boost/math/common_factor.hpp> #include <set> using namespace uhd; @@ -34,30 +36,32 @@ using namespace uhd::transport; **********************************************************************/ void b200_impl::check_tick_rate_with_current_streamers(double rate) { - size_t max_tx_chan_count = 0, max_rx_chan_count = 0; + // Defined in b200_impl.cpp + enforce_tick_rate_limits(max_chan_count("RX"), rate, "RX"); + enforce_tick_rate_limits(max_chan_count("TX"), rate, "TX"); +} + +// direction can either be "TX", "RX", or empty (default) +size_t b200_impl::max_chan_count(const std::string &direction /* = "" */) +{ + size_t max_count = 0; BOOST_FOREACH(radio_perifs_t &perif, _radio_perifs) { - { + if ((direction == "RX" or direction.empty()) and not perif.rx_streamer.expired()) { boost::shared_ptr<sph::recv_packet_streamer> rx_streamer = boost::dynamic_pointer_cast<sph::recv_packet_streamer>(perif.rx_streamer.lock()); - if (rx_streamer) - max_rx_chan_count = std::max(max_rx_chan_count, rx_streamer->get_num_channels()); + max_count = std::max(max_count, rx_streamer->get_num_channels()); } - - { + if ((direction == "TX" or direction.empty()) and not perif.tx_streamer.expired()) { boost::shared_ptr<sph::send_packet_streamer> tx_streamer = boost::dynamic_pointer_cast<sph::send_packet_streamer>(perif.tx_streamer.lock()); - if (tx_streamer) - max_tx_chan_count = std::max(max_tx_chan_count, tx_streamer->get_num_channels()); + max_count = std::max(max_count, tx_streamer->get_num_channels()); } } - - // Defined in b200_impl.cpp - enforce_tick_rate_limits(max_rx_chan_count, rate, "RX"); - enforce_tick_rate_limits(max_tx_chan_count, rate, "TX"); + return max_count; } -void b200_impl::check_streamer_args(const uhd::stream_args_t &args, double tick_rate, const char* direction /*= NULL*/) +void b200_impl::check_streamer_args(const uhd::stream_args_t &args, double tick_rate, const std::string &direction /*= ""*/) { std::set<size_t> chans_set; for (size_t stream_i = 0; stream_i < args.channels.size(); stream_i++) @@ -69,26 +73,145 @@ void b200_impl::check_streamer_args(const uhd::stream_args_t &args, double tick_ enforce_tick_rate_limits(chans_set.size(), tick_rate, direction); // Defined in b200_impl.cpp } -void b200_impl::update_tick_rate(const double rate) +void b200_impl::set_auto_tick_rate( + const double rate, + const fs_path &tree_dsp_path, + size_t num_chans +) { + if (num_chans == 0) { // Divine them + num_chans = std::max(size_t(1), max_chan_count()); + } + const double max_tick_rate = ad9361_device_t::AD9361_MAX_CLOCK_RATE/num_chans; + if (rate != 0.0 and + (uhd::math::fp_compare::fp_compare_delta<double>(rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) > + uhd::math::fp_compare::fp_compare_delta<double>(max_tick_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ))) { + throw uhd::value_error(str( + boost::format("Requested sampling rate (%.2f Msps) exceeds maximum tick rate of %.2f MHz.") + % (rate / 1e6) % (max_tick_rate / 1e6) + )); + } + + // See also the doxygen documentation for these steps in b200_impl.hpp + // Step 1: Obtain LCM and max rate from all relevant dsps + boost::uint32_t lcm_rate = (rate == 0) ? 1 : static_cast<boost::uint32_t>(floor(rate + 0.5)); + for (int i = 0; i < 2; i++) { // Loop through rx and tx + std::string dir = (i == 0) ? "tx" : "rx"; + // We have no way of knowing which DSPs are used, so we check them all. + BOOST_FOREACH(const std::string &dsp_no, _tree->list(str(boost::format("/mboards/0/%s_dsps") % dir))) { + fs_path dsp_path = str(boost::format("/mboards/0/%s_dsps/%s") % dir % dsp_no); + if (dsp_path == tree_dsp_path) { + continue; + } + double this_dsp_rate = _tree->access<double>(dsp_path / "rate/value").get(); + // Check if the user selected something completely unreasonable: + if (uhd::math::fp_compare::fp_compare_delta<double>(this_dsp_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) > + uhd::math::fp_compare::fp_compare_delta<double>(max_tick_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ)) { + throw uhd::value_error(str( + boost::format("Requested sampling rate (%.2f Msps) exceeds maximum tick rate of %.2f MHz.") + % (this_dsp_rate / 1e6) % (max_tick_rate / 1e6) + )); + } + // If this_dsp_rate == 0.0, the sampling rate for this DSP hasn't been set, so + // we don't take that into consideration. + if (this_dsp_rate == 0.0) { + continue; + } + lcm_rate = boost::math::lcm<boost::uint32_t>( + lcm_rate, + static_cast<boost::uint32_t>(floor(this_dsp_rate + 0.5)) + ); + } + } + if (lcm_rate == 1) { + // In this case, no one has ever set a sampling rate. + return; + } + + // Step 2: Check if the lcm_rate is within available limits: + double base_rate = static_cast<double>(lcm_rate); + if (uhd::math::fp_compare::fp_compare_delta<double>(base_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) > + uhd::math::fp_compare::fp_compare_delta<double>(max_tick_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ)) { + UHD_MSG(warning) + << "Cannot automatically determine an appropriate tick rate for these sampling rates." << std::endl + << "Consider using different sampling rates, or manually specify a suitable master clock rate." << std::endl; + return; // Let the others handle this + } + + // Step 3: Choose the new rate + // Rules for choosing the tick rate: + // Choose a rate that is a power of 2 larger than the sampling rate, + // but at least 4. Cannot exceed the max tick rate, of course, but must + // be larger than the minimum tick rate. + // An equation that does all that is: + // + // f_auto = r * 2^floor(log2(f_max/r)) + // = base_rate * multiplier + // + // where r is the base rate and f_max is the maximum tick rate. The case + // where floor() yields 1 must be caught. + const double min_tick_rate = _codec_ctrl->get_clock_rate_range().start(); + // We use shifts here instead of 2^x because exp2() is not available in all compilers, + // also this guarantees no rounding issues. The type cast to int32_t serves as floor(): + boost::int32_t multiplier = (1 << boost::int32_t(uhd::math::log2(max_tick_rate / base_rate))); + if (multiplier == 2 and base_rate >= min_tick_rate) { + // Don't bother (see above) + multiplier = 1; + } + double new_rate = base_rate * multiplier; + UHD_ASSERT_THROW( + uhd::math::fp_compare::fp_compare_delta<double>(new_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) >= + uhd::math::fp_compare::fp_compare_delta<double>(min_tick_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) + ); + UHD_ASSERT_THROW( + uhd::math::fp_compare::fp_compare_delta<double>(new_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) <= + uhd::math::fp_compare::fp_compare_delta<double>(max_tick_rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) + ); + + if (!uhd::math::frequencies_are_equal(_tree->access<double>("/mboards/0/tick_rate").get(), new_rate)) { + _tree->access<double>("/mboards/0/tick_rate").set(new_rate); + } +} + +void b200_impl::update_tick_rate(const double new_tick_rate) { - check_tick_rate_with_current_streamers(rate); + check_tick_rate_with_current_streamers(new_tick_rate); BOOST_FOREACH(radio_perifs_t &perif, _radio_perifs) { boost::shared_ptr<sph::recv_packet_streamer> my_streamer = boost::dynamic_pointer_cast<sph::recv_packet_streamer>(perif.rx_streamer.lock()); - if (my_streamer) my_streamer->set_tick_rate(rate); - perif.framer->set_tick_rate(_tick_rate); + if (my_streamer) my_streamer->set_tick_rate(new_tick_rate); + perif.framer->set_tick_rate(new_tick_rate); } BOOST_FOREACH(radio_perifs_t &perif, _radio_perifs) { boost::shared_ptr<sph::send_packet_streamer> my_streamer = boost::dynamic_pointer_cast<sph::send_packet_streamer>(perif.tx_streamer.lock()); - if (my_streamer) my_streamer->set_tick_rate(rate); - perif.deframer->set_tick_rate(_tick_rate); + if (my_streamer) my_streamer->set_tick_rate(new_tick_rate); + perif.deframer->set_tick_rate(new_tick_rate); } } +#define CHECK_RATE_AND_THROW(rate) \ + if (uhd::math::fp_compare::fp_compare_delta<double>(rate, uhd::math::FREQ_COMPARISON_DELTA_HZ) > \ + uhd::math::fp_compare::fp_compare_delta<double>(ad9361_device_t::AD9361_MAX_CLOCK_RATE, uhd::math::FREQ_COMPARISON_DELTA_HZ)) { \ + throw uhd::value_error(str( \ + boost::format("Requested sampling rate (%.2f Msps) exceeds maximum tick rate.") \ + % (rate / 1e6) \ + )); \ + } + +double b200_impl::coerce_rx_samp_rate(rx_dsp_core_3000::sptr ddc, size_t dspno, const double rx_rate) +{ + // Have to set tick rate first, or the ddc will change the requested rate based on default tick rate + if (_tree->access<bool>("/mboards/0/auto_tick_rate").get()) { + CHECK_RATE_AND_THROW(rx_rate); + const std::string dsp_path = (boost::format("/mboards/0/rx_dsps/%s") % dspno).str(); + set_auto_tick_rate(rx_rate, dsp_path); + } + return ddc->set_host_rate(rx_rate); +} + #define CHECK_BANDWIDTH(dir) \ if (rate > _codec_ctrl->get_bw_filter_range(dir).stop()) { \ UHD_MSG(warning) \ @@ -108,6 +231,17 @@ void b200_impl::update_rx_samp_rate(const size_t dspno, const double rate) CHECK_BANDWIDTH("Rx"); } +double b200_impl::coerce_tx_samp_rate(tx_dsp_core_3000::sptr duc, size_t dspno, const double tx_rate) +{ + // Have to set tick rate first, or the duc will change the requested rate based on default tick rate + if (_tree->access<bool>("/mboards/0/auto_tick_rate").get()) { + CHECK_RATE_AND_THROW(tx_rate); + const std::string dsp_path = (boost::format("/mboards/0/tx_dsps/%s") % dspno).str(); + set_auto_tick_rate(tx_rate, dsp_path); + } + return duc->set_host_rate(tx_rate); +} + void b200_impl::update_tx_samp_rate(const size_t dspno, const double rate) { boost::shared_ptr<sph::send_packet_streamer> my_streamer = @@ -276,6 +410,9 @@ rx_streamer::sptr b200_impl::get_rx_stream(const uhd::stream_args_t &args_) if (args.otw_format.empty()) args.otw_format = "sc16"; args.channels = args.channels.empty()? std::vector<size_t>(1, 0) : args.channels; + if (_tree->access<bool>("/mboards/0/auto_tick_rate").get()) { + set_auto_tick_rate(0, "", args.channels.size()); + } check_streamer_args(args, this->get_tick_rate(), "RX"); boost::shared_ptr<sph::recv_packet_streamer> my_streamer; @@ -383,7 +520,10 @@ tx_streamer::sptr b200_impl::get_tx_stream(const uhd::stream_args_t &args_) if (args.otw_format.empty()) args.otw_format = "sc16"; args.channels = args.channels.empty()? std::vector<size_t>(1, 0) : args.channels; - check_streamer_args(args, this->get_tick_rate(), "TX"); + if (_tree->access<bool>("/mboards/0/auto_tick_rate").get()) { + set_auto_tick_rate(0, "", args.channels.size()); + } + check_streamer_args(args, this->get_tick_rate(), "RX"); boost::shared_ptr<sph::send_packet_streamer> my_streamer; for (size_t stream_i = 0; stream_i < args.channels.size(); stream_i++) diff --git a/host/lib/usrp/b200/b200_regs.hpp b/host/lib/usrp/b200/b200_regs.hpp index 900651f94..8f2dd03f3 100644 --- a/host/lib/usrp/b200/b200_regs.hpp +++ b/host/lib/usrp/b200/b200_regs.hpp @@ -46,11 +46,13 @@ localparam SR_TX_DSP = 184; localparam SR_TIME = 128; localparam SR_RX_FMT = 136; localparam SR_TX_FMT = 138; +localparam SR_FP_GPIO = 200; localparam RB32_TEST = 0; localparam RB64_TIME_NOW = 8; localparam RB64_TIME_PPS = 16; localparam RB64_CODEC_READBACK = 24; +localparam RB32_FP_GPIO = 32; //pll constants static const int AD9361_SLAVENO = (1 << 0); diff --git a/host/lib/usrp/common/ad9361_ctrl.cpp b/host/lib/usrp/common/ad9361_ctrl.cpp index 65e8e2df9..2d9f297b3 100644 --- a/host/lib/usrp/common/ad9361_ctrl.cpp +++ b/host/lib/usrp/common/ad9361_ctrl.cpp @@ -16,7 +16,6 @@ // #include "ad9361_ctrl.hpp" -#include <uhd/exception.hpp> #include <uhd/types/ranges.hpp> #include <uhd/utils/msg.hpp> #include <uhd/types/serial.hpp> @@ -108,6 +107,27 @@ public: return _device.set_gain(direction, chain, value); } + void set_agc(const std::string &which, bool enable) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + ad9361_device_t::chain_t chain =_get_chain_from_antenna(which); + _device.set_agc(chain, enable); + } + + void set_agc_mode(const std::string &which, const std::string &mode) + { + boost::lock_guard<boost::mutex> lock(_mutex); + ad9361_device_t::chain_t chain =_get_chain_from_antenna(which); + if(mode == "slow") { + _device.set_agc_mode(chain, ad9361_device_t::GAIN_MODE_SLOW_AGC); + } else if (mode == "fast"){ + _device.set_agc_mode(chain, ad9361_device_t::GAIN_MODE_FAST_AGC); + } else { + throw uhd::runtime_error("ad9361_ctrl got an invalid AGC option."); + } + } + //! set a new clock rate, return the exact value double set_clock_rate(const double rate) { @@ -175,6 +195,62 @@ public: return sensor_value_t("RSSI", _device.get_rssi(chain), "dB"); } + //! read the internal temp sensor. Average over 3 results + sensor_value_t get_temperature() + { + return sensor_value_t("temp", _device.get_average_temperature(), "C"); + } + + void set_dc_offset_auto(const std::string &which, const bool on) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + _device.set_dc_offset_auto(direction,on); + } + + void set_iq_balance_auto(const std::string &which, const bool on) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + _device.set_iq_balance_auto(direction,on); + } + + double set_bw_filter(const std::string &which, const double bw) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + return _device.set_bw_filter(direction, bw); + } + + std::vector<std::string> get_filter_names(const std::string &which) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + return _device.get_filter_names(direction); + } + + filter_info_base::sptr get_filter(const std::string &which, const std::string &filter_name) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + ad9361_device_t::chain_t chain =_get_chain_from_antenna(which); + return _device.get_filter(direction, chain, filter_name); + } + + void set_filter(const std::string &which, const std::string &filter_name, const filter_info_base::sptr filter) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + ad9361_device_t::chain_t chain = _get_chain_from_antenna(which); + _device.set_filter(direction, chain, filter_name, filter); + } + private: static ad9361_device_t::direction_t _get_direction_from_antenna(const std::string& antenna) { diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp index b7d7b8e26..ac0404b24 100644 --- a/host/lib/usrp/common/ad9361_ctrl.hpp +++ b/host/lib/usrp/common/ad9361_ctrl.hpp @@ -22,9 +22,13 @@ #include <uhd/types/ranges.hpp> #include <uhd/types/serial.hpp> #include <uhd/types/sensors.hpp> +#include <uhd/exception.hpp> #include <boost/shared_ptr.hpp> #include <ad9361_device.h> #include <string> +#include <complex> +#include <uhd/types/filters.hpp> +#include <vector> namespace uhd { namespace usrp { @@ -77,15 +81,18 @@ public: return uhd::meta_range_t(5e6, ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end } - //! set the filter bandwidth for the frontend - double set_bw_filter(const std::string &/*which*/, const double /*bw*/) - { - return 56e6; //TODO - } + //! set the filter bandwidth for the frontend's analog low pass + virtual double set_bw_filter(const std::string &/*which*/, const double /*bw*/) = 0; //! set the gain for a particular gain element virtual double set_gain(const std::string &which, const double value) = 0; + //! Enable or disable the AGC module + virtual void set_agc(const std::string &which, bool enable) = 0; + + //! configure the AGC module to slow or fast mode + virtual void set_agc_mode(const std::string &which, const std::string &mode) = 0; + //! set a new clock rate, return the exact value virtual double set_clock_rate(const double rate) = 0; @@ -95,14 +102,46 @@ public: //! tune the given frontend, return the exact value virtual double tune(const std::string &which, const double value) = 0; + //! set the DC offset for I and Q manually + void set_dc_offset(const std::string &, const std::complex<double>) + { + //This feature should not be used according to Analog Devices + throw uhd::runtime_error("ad9361_ctrl::set_dc_offset this feature is not supported on this device."); + } + + //! enable or disable the BB/RF DC tracking feature + virtual void set_dc_offset_auto(const std::string &which, const bool on) = 0; + + //! set the IQ correction value manually + void set_iq_balance(const std::string &, const std::complex<double>) + { + //This feature should not be used according to Analog Devices + throw uhd::runtime_error("ad9361_ctrl::set_iq_balance this feature is not supported on this device."); + } + + //! enable or disable the quadrature calibration + virtual void set_iq_balance_auto(const std::string &which, const bool on) = 0; + //! get the current frequency for the given frontend virtual double get_freq(const std::string &which) = 0; - //! turn on/off data port loopback + //! turn on/off Catalina's data port loopback virtual void data_port_loopback(const bool on) = 0; //! read internal RSSI sensor virtual sensor_value_t get_rssi(const std::string &which) = 0; + + //! read the internal temp sensor + virtual sensor_value_t get_temperature() = 0; + + //! List all available filters by name + virtual std::vector<std::string> get_filter_names(const std::string &which) = 0; + + //! Return a list of all filters + virtual filter_info_base::sptr get_filter(const std::string &which, const std::string &filter_name) = 0; + + //! Write back a filter + virtual void set_filter(const std::string &which, const std::string &filter_name, const filter_info_base::sptr) = 0; }; }} diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp index db5de52d0..00534c305 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -11,6 +11,7 @@ #include <cmath> #include <uhd/exception.hpp> #include <uhd/utils/log.hpp> +#include <uhd/utils/msg.hpp> #include <boost/cstdint.hpp> #include <boost/date_time/posix_time/posix_time.hpp> #include <boost/thread/thread.hpp> @@ -78,6 +79,7 @@ int get_num_taps(int max_num_taps) { const double ad9361_device_t::AD9361_MAX_GAIN = 89.75; const double ad9361_device_t::AD9361_MAX_CLOCK_RATE = 61.44e6; +const double ad9361_device_t::AD9361_CAL_VALID_WINDOW = 100e6; // Max bandwdith is due to filter rolloff in analog filter stage const double ad9361_device_t::AD9361_RECOMMENDED_MAX_BANDWIDTH = 56e6; @@ -87,7 +89,7 @@ const double ad9361_device_t::AD9361_RECOMMENDED_MAX_BANDWIDTH = 56e6; * how many taps are in the filter, and given a vector of the taps * themselves. */ -void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs) +void ad9361_device_t::_program_fir_filter(direction_t direction, chain_t chain, int num_taps, boost::uint16_t *coeffs) { boost::uint16_t base; @@ -102,8 +104,20 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, b /* Encode number of filter taps for programming register */ boost::uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5; + boost::uint8_t reg_chain = 0; + switch (chain) { + case CHAIN_1: + reg_chain = 0x01 << 3; + break; + case CHAIN_2: + reg_chain = 0x02 << 3; + break; + default: + reg_chain = 0x03 << 3; + } + /* Turn on the filter clock. */ - _io_iface->poke8(base + 5, reg_numtaps | 0x1a); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain | 0x02); boost::this_thread::sleep(boost::posix_time::milliseconds(1)); /* Zero the unused taps just in case they have stale data */ @@ -112,7 +126,7 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, b _io_iface->poke8(base + 0, addr); _io_iface->poke8(base + 1, 0x0); _io_iface->poke8(base + 2, 0x0); - _io_iface->poke8(base + 5, reg_numtaps | 0x1e); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain | (1 << 1) | (1 << 2)); _io_iface->poke8(base + 4, 0x00); _io_iface->poke8(base + 4, 0x00); } @@ -122,7 +136,7 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, b _io_iface->poke8(base + 0, addr); _io_iface->poke8(base + 1, (coeffs[addr]) & 0xff); _io_iface->poke8(base + 2, (coeffs[addr] >> 8) & 0xff); - _io_iface->poke8(base + 5, reg_numtaps | 0x1e); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain | (1 << 1) | (1 << 2)); _io_iface->poke8(base + 4, 0x00); _io_iface->poke8(base + 4, 0x00); } @@ -133,9 +147,9 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, b before the clock stops. Wait 4 sample clock periods after setting D2 high while that data writes into the table" */ - _io_iface->poke8(base + 5, reg_numtaps | 0x1A); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain | (1 << 1)); if (direction == RX) { - _io_iface->poke8(base + 5, reg_numtaps | 0x18); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain ); /* Rx Gain, set to prevent digital overflow/saturation in filters 0:+6dB, 1:0dB, 2:-6dB, 3:-12dB page 35 of UG-671 */ @@ -144,7 +158,7 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, b /* Tx Gain. bit[0]. set to prevent digital overflow/saturation in filters 0: 0dB, 1:-6dB page 25 of UG-671 */ - _io_iface->poke8(base + 5, reg_numtaps | 0x18); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain ); } } @@ -175,7 +189,7 @@ void ad9361_device_t::_setup_rx_fir(size_t num_taps, boost::int32_t decimation) } } - _program_fir_filter(RX, num_taps, coeffs.get()); + _program_fir_filter(RX, CHAIN_BOTH, num_taps, coeffs.get()); } /* Program the TX FIR Filter. */ @@ -207,7 +221,7 @@ void ad9361_device_t::_setup_tx_fir(size_t num_taps, boost::int32_t interpolatio } } - _program_fir_filter(TX, num_taps, coeffs.get()); + _program_fir_filter(TX, CHAIN_BOTH, num_taps, coeffs.get()); } /*********************************************************************** @@ -282,16 +296,24 @@ void ad9361_device_t::_calibrate_synth_charge_pumps() * * Note that the filter calibration depends heavily on the baseband * bandwidth, so this must be re-done after any change to the RX sample - * rate. */ -double ad9361_device_t::_calibrate_baseband_rx_analog_filter() + * rate. + * UG570 Page 33 states that this filter should be calibrated to 1.4 * bbbw*/ +double ad9361_device_t::_calibrate_baseband_rx_analog_filter(double req_rfbw) { - /* For filter tuning, baseband BW is half the complex BW, and must be - * between 28e6 and 0.2e6. */ - double bbbw = _baseband_bw / 2.0; + double bbbw = req_rfbw / 2.0; + if(bbbw > _baseband_bw / 2.0) + { + UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + bbbw = _baseband_bw / 2.0; + } + + /* Baseband BW must be between 28e6 and 0.143e6. + * Max filter BW is 39.2 MHz. 39.2 / 1.4 = 28 + * Min filter BW is 200kHz. 200 / 1.4 = 143 */ if (bbbw > 28e6) { bbbw = 28e6; - } else if (bbbw < 0.20e6) { - bbbw = 0.20e6; + } else if (bbbw < 0.143e6) { + bbbw = 0.143e6; } double rxtune_clk = ((1.4 * bbbw * 2 * M_PI) / M_LN2); @@ -340,16 +362,25 @@ double ad9361_device_t::_calibrate_baseband_rx_analog_filter() * * Note that the filter calibration depends heavily on the baseband * bandwidth, so this must be re-done after any change to the TX sample - * rate. */ -double ad9361_device_t::_calibrate_baseband_tx_analog_filter() + * rate. + * UG570 Page 32 states that this filter should be calibrated to 1.6 * bbbw*/ +double ad9361_device_t::_calibrate_baseband_tx_analog_filter(double req_rfbw) { - /* For filter tuning, baseband BW is half the complex BW, and must be - * between 28e6 and 0.2e6. */ - double bbbw = _baseband_bw / 2.0; + double bbbw = req_rfbw / 2.0; + + if(bbbw > _baseband_bw / 2.0) + { + UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + bbbw = _baseband_bw / 2.0; + } + + /* Baseband BW must be between 20e6 and 0.391e6. + * Max filter BW is 32 MHz. 32 / 1.6 = 20 + * Min filter BW is 625 kHz. 625 / 1.6 = 391 */ if (bbbw > 20e6) { bbbw = 20e6; - } else if (bbbw < 0.625e6) { - bbbw = 0.625e6; + } else if (bbbw < 0.391e6) { + bbbw = 0.391e6; } double txtune_clk = ((1.6 * bbbw * 2 * M_PI) / M_LN2); @@ -386,16 +417,25 @@ double ad9361_device_t::_calibrate_baseband_tx_analog_filter() /* Calibrate the secondary TX filter. * * This filter also depends on the TX sample rate, so if a rate change is - * made, the previous calibration will no longer be valid. */ -void ad9361_device_t::_calibrate_secondary_tx_filter() + * made, the previous calibration will no longer be valid. + * UG570 Page 32 states that this filter should be calibrated to 5 * bbbw*/ +double ad9361_device_t::_calibrate_secondary_tx_filter(double req_rfbw) { - /* For filter tuning, baseband BW is half the complex BW, and must be - * between 20e6 and 0.53e6. */ - double bbbw = _baseband_bw / 2.0; + double bbbw = req_rfbw / 2.0; + + if(bbbw > _baseband_bw / 2.0) + { + UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + bbbw = _baseband_bw / 2.0; + } + + /* Baseband BW must be between 20e6 and 0.54e6. + * Max filter BW is 100 MHz. 100 / 5 = 20 + * Min filter BW is 2.7 MHz. 2.7 / 5 = 0.54 */ if (bbbw > 20e6) { bbbw = 20e6; - } else if (bbbw < 0.53e6) { - bbbw = 0.53e6; + } else if (bbbw < 0.54e6) { + bbbw = 0.54e6; } double bbbw_mhz = bbbw / 1e6; @@ -456,13 +496,17 @@ void ad9361_device_t::_calibrate_secondary_tx_filter() _io_iface->poke8(0x0d2, reg0d2); _io_iface->poke8(0x0d1, reg0d1); _io_iface->poke8(0x0d0, reg0d0); + + return bbbw; } /* Calibrate the RX TIAs. * * Note that the values in the TIA register, after calibration, vary with - * the RX gain settings. */ -void ad9361_device_t::_calibrate_rx_TIAs() + * the RX gain settings. + * We do not really program the BW here. Most settings are taken form the BB LPF registers + * UG570 page 33 states that this filter should be calibrated to 2.5 * bbbw */ +double ad9361_device_t::_calibrate_rx_TIAs(double req_rfbw) { boost::uint8_t reg1eb = _io_iface->peek8(0x1eb) & 0x3F; boost::uint8_t reg1ec = _io_iface->peek8(0x1ec) & 0x7F; @@ -473,13 +517,21 @@ void ad9361_device_t::_calibrate_rx_TIAs() boost::uint8_t reg1de = 0x00; boost::uint8_t reg1df = 0x00; - /* For calibration, baseband BW is half the complex BW, and must be - * between 28e6 and 0.2e6. */ - double bbbw = _baseband_bw / 2.0; - if (bbbw > 20e6) { - bbbw = 20e6; - } else if (bbbw < 0.20e6) { - bbbw = 0.20e6; + double bbbw = req_rfbw / 2.0; + + if(bbbw > _baseband_bw / 2.0) + { + UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + bbbw = _baseband_bw / 2.0; + } + + /* Baseband BW must be between 28e6 and 0.4e6. + * Max filter BW is 70 MHz. 70 / 2.5 = 28 + * Min filter BW is 1 MHz. 1 / 2.5 = 0.4*/ + if (bbbw > 28e6) { + bbbw = 28e6; + } else if (bbbw < 0.40e6) { + bbbw = 0.40e6; } double ceil_bbbw_mhz = std::ceil(bbbw / 1e6); @@ -520,6 +572,8 @@ void ad9361_device_t::_calibrate_rx_TIAs() _io_iface->poke8(0x1df, reg1df); _io_iface->poke8(0x1dc, reg1dc); _io_iface->poke8(0x1de, reg1de); + + return bbbw; } /* Setup the AD9361 ADC. @@ -651,11 +705,12 @@ void ad9361_device_t::_setup_adc() } /* Calibrate the baseband DC offset. - * - * Note that this function is called from within the TX quadrature - * calibration function! */ + * Disables tracking + */ void ad9361_device_t::_calibrate_baseband_dc_offset() { + _io_iface->poke8(0x18b, 0x83); //Reset RF DC tracking flag + _io_iface->poke8(0x193, 0x3f); // Calibration settings _io_iface->poke8(0x190, 0x0f); // Set tracking coefficient //write_ad9361_reg(device, 0x190, /*0x0f*//*0xDF*/0x80*1 | 0x40*1 | (16+8/*+4*/)); // Set tracking coefficient: don't *4 counter, do decim /4, increased gain shift @@ -675,9 +730,8 @@ void ad9361_device_t::_calibrate_baseband_dc_offset() } /* Calibrate the RF DC offset. - * - * Note that this function is called from within the TX quadrature - * calibration function. */ + * Disables tracking + */ void ad9361_device_t::_calibrate_rf_dc_offset() { /* Some settings are frequency-dependent. */ @@ -692,7 +746,7 @@ void ad9361_device_t::_calibrate_rf_dc_offset() } _io_iface->poke8(0x185, 0x20); // RF DC Offset wait count - _io_iface->poke8(0x18b, 0x83); + _io_iface->poke8(0x18b, 0x83); // Disable tracking _io_iface->poke8(0x189, 0x30); /* Run the calibration! */ @@ -708,6 +762,16 @@ void ad9361_device_t::_calibrate_rf_dc_offset() } } +void ad9361_device_t::_configure_bb_rf_dc_tracking(const bool on) +{ + if(on) + { + _io_iface->poke8(0x18b, 0xad); // Enable BB and RF DC tracking + } else { + _io_iface->poke8(0x18b, 0x83); // Disable BB and RF DC tracking + } +} + /* Start the RX quadrature calibration. * * Note that we are using AD9361's 'tracking' feature for RX quadrature @@ -719,17 +783,21 @@ void ad9361_device_t::_calibrate_rx_quadrature() _io_iface->poke8(0x168, 0x03); // Set tone level for cal _io_iface->poke8(0x16e, 0x25); // RX Gain index to use for cal _io_iface->poke8(0x16a, 0x75); // Set Kexp phase - _io_iface->poke8(0x16b, 0x15); // Set Kexp amplitude - _io_iface->poke8(0x169, 0xcf); // Continuous tracking mode - _io_iface->poke8(0x18b, 0xad); + _io_iface->poke8(0x16b, 0x95); // Set Kexp amplitude + + if(_use_iq_balance_correction) + { + _io_iface->poke8(0x169, 0xcf); // Continuous tracking mode. Gets disabled in _tx_quadrature_cal_routine! + } } -/* TX quadtrature calibration routine. +/* TX quadrature calibration routine. * * The TX quadrature needs to be done twice, once for each TX chain, with * only one register change in between. Thus, this function enacts the * calibrations, and it is called from calibrate_tx_quadrature. */ void ad9361_device_t::_tx_quadrature_cal_routine() { + /* This is a weird process, but here is how it works: * 1) Read the calibrated NCO frequency bits out of 0A3. * 2) Write the two bits to the RX NCO freq part of 0A0. @@ -765,7 +833,7 @@ void ad9361_device_t::_tx_quadrature_cal_routine() { /* The gain table index used for calibration must be adjusted for the * mid-table to get a TIA index = 1 and LPF index = 0. */ - if ((_rx_freq >= 1300e6) && (_rx_freq < 4000e6)) { + if (_rx_freq < 1300e6) { _io_iface->poke8(0x0aa, 0x22); // Cal gain table index } else { _io_iface->poke8(0x0aa, 0x25); // Cal gain table index @@ -774,12 +842,6 @@ void ad9361_device_t::_tx_quadrature_cal_routine() { _io_iface->poke8(0x0a4, 0xf0); // Cal setting conut _io_iface->poke8(0x0ae, 0x00); // Cal LPF gain index (split mode) - /* First, calibrate the baseband DC offset. */ - _calibrate_baseband_dc_offset(); - - /* Second, calibrate the RF DC offset. */ - _calibrate_rf_dc_offset(); - /* Now, calibrate the TX quadrature! */ size_t count = 0; _io_iface->poke8(0x016, 0x10); @@ -794,9 +856,7 @@ void ad9361_device_t::_tx_quadrature_cal_routine() { } /* Run the TX quadrature calibration. - * - * Note that from within this function we are also triggering the baseband - * and RF DC calibrations. */ + */ void ad9361_device_t::_calibrate_tx_quadrature() { /* Make sure we are, in fact, in the ALERT state. If not, something is @@ -880,7 +940,7 @@ void ad9361_device_t::_program_mixer_gm_subtable() void ad9361_device_t::_program_gain_table() { /* Figure out which gain table we should be using for our current * frequency band. */ - boost::uint8_t (*gain_table)[5] = NULL; + boost::uint8_t (*gain_table)[3] = NULL; boost::uint8_t new_gain_table; if (_rx_freq < 1300e6) { gain_table = gain_table_sub_1300mhz; @@ -911,9 +971,9 @@ void ad9361_device_t::_program_gain_table() { boost::uint8_t index = 0; for (; index < 77; index++) { _io_iface->poke8(0x130, index); - _io_iface->poke8(0x131, gain_table[index][1]); - _io_iface->poke8(0x132, gain_table[index][2]); - _io_iface->poke8(0x133, gain_table[index][3]); + _io_iface->poke8(0x131, gain_table[index][0]); + _io_iface->poke8(0x132, gain_table[index][1]); + _io_iface->poke8(0x133, gain_table[index][2]); _io_iface->poke8(0x137, 0x1E); _io_iface->poke8(0x134, 0x00); _io_iface->poke8(0x134, 0x00); @@ -939,28 +999,58 @@ void ad9361_device_t::_program_gain_table() { /* Setup gain control registers. * - * This really only needs to be done once, at initialization. */ -void ad9361_device_t::_setup_gain_control() + * This really only needs to be done once, at initialization. + * If AGC is used the mode select bits (Reg 0x0FA) must be written manually */ +void ad9361_device_t::_setup_gain_control(bool agc) { - _io_iface->poke8(0x0FA, 0xE0); // Gain Control Mode Select - _io_iface->poke8(0x0FB, 0x08); // Table, Digital Gain, Man Gain Ctrl - _io_iface->poke8(0x0FC, 0x23); // Incr Step Size, ADC Overrange Size - _io_iface->poke8(0x0FD, 0x4C); // Max Full/LMT Gain Table Index - _io_iface->poke8(0x0FE, 0x44); // Decr Step Size, Peak Overload Time - _io_iface->poke8(0x100, 0x6F); // Max Digital Gain - _io_iface->poke8(0x104, 0x2F); // ADC Small Overload Threshold - _io_iface->poke8(0x105, 0x3A); // ADC Large Overload Threshold - _io_iface->poke8(0x107, 0x31); // Large LMT Overload Threshold - _io_iface->poke8(0x108, 0x39); // Small LMT Overload Threshold - _io_iface->poke8(0x109, 0x23); // Rx1 Full/LMT Gain Index - _io_iface->poke8(0x10A, 0x58); // Rx1 LPF Gain Index - _io_iface->poke8(0x10B, 0x00); // Rx1 Digital Gain Index - _io_iface->poke8(0x10C, 0x23); // Rx2 Full/LMT Gain Index - _io_iface->poke8(0x10D, 0x18); // Rx2 LPF Gain Index - _io_iface->poke8(0x10E, 0x00); // Rx2 Digital Gain Index - _io_iface->poke8(0x114, 0x30); // Low Power Threshold - _io_iface->poke8(0x11A, 0x27); // Initial LMT Gain Limit - _io_iface->poke8(0x081, 0x00); // Tx Symbol Gain Control + /* The AGC mode configuration should be good for all cases. + * However, non AGC configuration still used for backward compatibility. */ + if (agc) { + /*mode select bits must be written before hand!*/ + _io_iface->poke8(0x0FB, 0x08); // Table, Digital Gain, Man Gain Ctrl + _io_iface->poke8(0x0FC, 0x23); // Incr Step Size, ADC Overrange Size + _io_iface->poke8(0x0FD, 0x4C); // Max Full/LMT Gain Table Index + _io_iface->poke8(0x0FE, 0x44); // Decr Step Size, Peak Overload Time + _io_iface->poke8(0x100, 0x6F); // Max Digital Gain + _io_iface->poke8(0x101, 0x0A); // Max Digital Gain + _io_iface->poke8(0x103, 0x08); // Max Digital Gain + _io_iface->poke8(0x104, 0x2F); // ADC Small Overload Threshold + _io_iface->poke8(0x105, 0x3A); // ADC Large Overload Threshold + _io_iface->poke8(0x106, 0x22); // Max Digital Gain + _io_iface->poke8(0x107, 0x2B); // Large LMT Overload Threshold + _io_iface->poke8(0x108, 0x31); + _io_iface->poke8(0x111, 0x0A); + _io_iface->poke8(0x11A, 0x1C); + _io_iface->poke8(0x120, 0x0C); + _io_iface->poke8(0x121, 0x44); + _io_iface->poke8(0x122, 0x44); + _io_iface->poke8(0x123, 0x11); + _io_iface->poke8(0x124, 0xF5); + _io_iface->poke8(0x125, 0x3B); + _io_iface->poke8(0x128, 0x03); + _io_iface->poke8(0x129, 0x56); + _io_iface->poke8(0x12A, 0x22); + } else { + _io_iface->poke8(0x0FA, 0xE0); // Gain Control Mode Select + _io_iface->poke8(0x0FB, 0x08); // Table, Digital Gain, Man Gain Ctrl + _io_iface->poke8(0x0FC, 0x23); // Incr Step Size, ADC Overrange Size + _io_iface->poke8(0x0FD, 0x4C); // Max Full/LMT Gain Table Index + _io_iface->poke8(0x0FE, 0x44); // Decr Step Size, Peak Overload Time + _io_iface->poke8(0x100, 0x6F); // Max Digital Gain + _io_iface->poke8(0x104, 0x2F); // ADC Small Overload Threshold + _io_iface->poke8(0x105, 0x3A); // ADC Large Overload Threshold + _io_iface->poke8(0x107, 0x31); // Large LMT Overload Threshold + _io_iface->poke8(0x108, 0x39); // Small LMT Overload Threshold + _io_iface->poke8(0x109, 0x23); // Rx1 Full/LMT Gain Index + _io_iface->poke8(0x10A, 0x58); // Rx1 LPF Gain Index + _io_iface->poke8(0x10B, 0x00); // Rx1 Digital Gain Index + _io_iface->poke8(0x10C, 0x23); // Rx2 Full/LMT Gain Index + _io_iface->poke8(0x10D, 0x18); // Rx2 LPF Gain Index + _io_iface->poke8(0x10E, 0x00); // Rx2 Digital Gain Index + _io_iface->poke8(0x114, 0x30); // Low Power Threshold + _io_iface->poke8(0x11A, 0x27); // Initial LMT Gain Limit + _io_iface->poke8(0x081, 0x00); // Tx Symbol Gain Control + } } /* Setup the RX or TX synthesizers. @@ -1257,6 +1347,7 @@ double ad9361_device_t::_setup_rates(const double rate) int divfactor = 0; _tfir_factor = 0; _rfir_factor = 0; + if (rate < 0.33e6) { // RX1 + RX2 enabled, 3, 2, 2, 4 _regs.rxfilt = B8(11101111); @@ -1412,6 +1503,19 @@ void ad9361_device_t::initialize() _rx2_gain = 0; _tx1_gain = 0; _tx2_gain = 0; + _use_dc_offset_correction = true; + _use_iq_balance_correction = true; + _rx1_agc_mode = GAIN_MODE_SLOW_AGC; + _rx2_agc_mode = GAIN_MODE_SLOW_AGC; + _rx1_agc_enable = false; + _rx2_agc_enable = false; + _last_calibration_freq = -AD9361_CAL_VALID_WINDOW; + _rx_analog_bw = 0; + _tx_analog_bw = 0; + _rx_tia_lp_bw = 0; + _tx_sec_lp_bw = 0; + _rx_bb_lp_bw = 0; + _tx_bb_lp_bw = 0; /* Reset the device. */ _io_iface->poke8(0x000, 0x01); @@ -1490,7 +1594,6 @@ void ad9361_device_t::initialize() _io_iface->poke8(0x019, 0x00); // AuxDAC2 Word[9:2] _io_iface->poke8(0x01A, 0x00); // AuxDAC1 Config and Word[1:0] _io_iface->poke8(0x01B, 0x00); // AuxDAC2 Config and Word[1:0] - _io_iface->poke8(0x022, 0x4A); // Invert Bypassed LNA _io_iface->poke8(0x023, 0xFF); // AuxDAC Manaul/Auto Control _io_iface->poke8(0x026, 0x00); // AuxDAC Manual Select Bit/GPO Manual Select _io_iface->poke8(0x030, 0x00); // AuxDAC1 Rx Delay @@ -1498,10 +1601,18 @@ void ad9361_device_t::initialize() _io_iface->poke8(0x032, 0x00); // AuxDAC2 Rx Delay _io_iface->poke8(0x033, 0x00); // AuxDAC2 Tx Delay + /* LNA bypass polarity inversion + * According to the register map, we should invert the bypass path to + * match LNA phase. Extensive testing, however, shows otherwise and that + * to align bypass and LNA phases, the bypass inversion switch should be + * turned off. + */ + _io_iface->poke8(0x022, 0x0A); + /* Setup AuxADC */ _io_iface->poke8(0x00B, 0x00); // Temp Sensor Setup (Offset) _io_iface->poke8(0x00C, 0x00); // Temp Sensor Setup (Temp Window) - _io_iface->poke8(0x00D, 0x03); // Temp Sensor Setup (Periodic Measure) + _io_iface->poke8(0x00D, 0x00); // Temp Sensor Setup (Manual Measure) _io_iface->poke8(0x00F, 0x04); // Temp Sensor Setup (Decimation) _io_iface->poke8(0x01C, 0x10); // AuxADC Setup (Clock Div) _io_iface->poke8(0x01D, 0x01); // AuxADC Setup (Decimation/Enable) @@ -1555,17 +1666,18 @@ void ad9361_device_t::initialize() _program_mixer_gm_subtable(); _program_gain_table(); - _setup_gain_control(); + _setup_gain_control(false); - _calibrate_baseband_rx_analog_filter(); - _calibrate_baseband_tx_analog_filter(); - _calibrate_rx_TIAs(); - _calibrate_secondary_tx_filter(); + set_bw_filter(RX, _baseband_bw); + set_bw_filter(TX, _baseband_bw); _setup_adc(); + _calibrate_baseband_dc_offset(); + _calibrate_rf_dc_offset(); _calibrate_tx_quadrature(); _calibrate_rx_quadrature(); + _configure_bb_rf_dc_tracking(_use_dc_offset_correction); // cals done, set PPORT config switch (_client_params->get_digital_interface_mode()) { @@ -1680,18 +1792,19 @@ double ad9361_device_t::set_clock_rate(const double req_rate) _program_mixer_gm_subtable(); _program_gain_table(); - _setup_gain_control(); + _setup_gain_control(false); _reprogram_gains(); - _calibrate_baseband_rx_analog_filter(); - _calibrate_baseband_tx_analog_filter(); - _calibrate_rx_TIAs(); - _calibrate_secondary_tx_filter(); + set_bw_filter(RX, _baseband_bw); + set_bw_filter(TX, _baseband_bw); _setup_adc(); + _calibrate_baseband_dc_offset(); + _calibrate_rf_dc_offset(); _calibrate_tx_quadrature(); _calibrate_rx_quadrature(); + _configure_bb_rf_dc_tracking(_use_dc_offset_correction); // cals done, set PPORT config switch (_client_params->get_digital_interface_mode()) { @@ -1843,9 +1956,16 @@ double ad9361_device_t::tune(direction_t direction, const double value) /* Update the gain settings. */ _reprogram_gains(); - /* Run the calibration algorithms. */ - _calibrate_tx_quadrature(); - _calibrate_rx_quadrature(); + /* Only run the following calibrations if we are more than 100MHz away + * from the previous calibration point. */ + if (std::abs(_last_calibration_freq - tune_freq) > AD9361_CAL_VALID_WINDOW) { + /* Run the calibration algorithms. */ + _calibrate_rf_dc_offset(); + _calibrate_tx_quadrature(); + _calibrate_rx_quadrature(); + _configure_bb_rf_dc_tracking(_use_dc_offset_correction); + _last_calibration_freq = tune_freq; + } /* If we were in the FDD state, return it now. */ if (not_in_alert) { @@ -1960,4 +2080,678 @@ double ad9361_device_t::get_rssi(chain_t chain) return rssi; } +/* + * Returns the reading of the internal temperature sensor. + * One point calibration of the sensor was done according to datasheet + * leading to the given default constant correction factor. + */ +double ad9361_device_t::_get_temperature(const double cal_offset, const double timeout) +{ + //set 0x01D[0] to 1 to disable AuxADC GPIO reading + boost::uint8_t tmp = 0; + tmp = _io_iface->peek8(0x01D); + _io_iface->poke8(0x01D, (tmp | 0x01)); + _io_iface->poke8(0x00B, 0); //set offset to 0 + + _io_iface->poke8(0x00C, 0x01); //start reading, clears bit 0x00C[1] + boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time(); + boost::posix_time::time_duration elapsed; + //wait for valid data (toggle of bit 1 in 0x00C) + while(((_io_iface->peek8(0x00C) >> 1) & 0x01) == 0) { + boost::this_thread::sleep(boost::posix_time::microseconds(100)); + elapsed = boost::posix_time::microsec_clock::local_time() - start_time; + if(elapsed.total_milliseconds() > (timeout*1000)) + { + throw uhd::runtime_error("[ad9361_device_t] timeout while reading temperature"); + } + } + _io_iface->poke8(0x00C, 0x00); //clear read flag + + boost::uint8_t temp = _io_iface->peek8(0x00E); //read temperature. + double tmp_temp = temp/1.140f; //according to ADI driver + tmp_temp = tmp_temp + cal_offset; //Constant offset acquired by one point calibration. + + return tmp_temp; +} + +double ad9361_device_t::get_average_temperature(const double cal_offset, const size_t num_samples) +{ + double d_temp = 0; + for(size_t i = 0; i < num_samples; i++) { + double tmp_temp = _get_temperature(cal_offset); + d_temp += (tmp_temp/num_samples); + } + return d_temp; +} + +void ad9361_device_t::set_dc_offset_auto(direction_t direction, const bool on) +{ + if(direction == RX) + { + _use_dc_offset_correction = on; + _configure_bb_rf_dc_tracking(_use_dc_offset_correction); + if(on) + { + _io_iface->poke8(0x182, (_io_iface->peek8(0x182) & (~((1 << 7) | (1 << 6) | (1 << 3) | (1 << 2))))); //Clear force bits + //Do a single shot DC offset cal before enabling tracking (Not possible if not in ALERT state. Is it necessary?) + } else { + //clear current config values + _io_iface->poke8(0x182, (_io_iface->peek8(0x182) | ((1 << 7) | (1 << 6) | (1 << 3) | (1 << 2)))); //Set input A and input B&C force enable bits + _io_iface->poke8(0x174, 0x00); + _io_iface->poke8(0x175, 0x00); + _io_iface->poke8(0x176, 0x00); + _io_iface->poke8(0x177, 0x00); + _io_iface->poke8(0x178, 0x00); + _io_iface->poke8(0x17D, 0x00); + _io_iface->poke8(0x17E, 0x00); + _io_iface->poke8(0x17F, 0x00); + _io_iface->poke8(0x180, 0x00); + _io_iface->poke8(0x181, 0x00); + } + } else { + // DC offset is removed during TX quad cal + throw uhd::runtime_error("[ad9361_device_t] [set_iq_balance_auto] INVALID_CODE_PATH"); + } +} + +void ad9361_device_t::set_iq_balance_auto(direction_t direction, const bool on) +{ + if(direction == RX) + { + _use_iq_balance_correction = on; + if(on) + { + //disable force registers and enable tracking + _io_iface->poke8(0x182, (_io_iface->peek8(0x182) & (~ ( (1<<1) | (1<<0) | (1<<5) | (1<<4) )))); + _calibrate_rx_quadrature(); + } else { + //disable IQ tracking + _io_iface->poke8(0x169, 0xc0); + //clear current config values + _io_iface->poke8(0x182, (_io_iface->peek8(0x182) | ((1 << 1) | (1 << 0) | (1 << 5) | (1 << 4)))); //Set Rx2 input B&C force enable bit + _io_iface->poke8(0x17B, 0x00); + _io_iface->poke8(0x17C, 0x00); + _io_iface->poke8(0x179, 0x00); + _io_iface->poke8(0x17A, 0x00); + _io_iface->poke8(0x170, 0x00); + _io_iface->poke8(0x171, 0x00); + _io_iface->poke8(0x172, 0x00); + _io_iface->poke8(0x173, 0x00); + } + } else { + throw uhd::runtime_error("[ad9361_device_t] [set_iq_balance_auto] INVALID_CODE_PATH"); + } +} + +/* Sets the RX gain mode to be used. + * If a transition from an AGC to an non AGC mode occurs (or vice versa) + * the gain configuration will be reloaded. */ +void ad9361_device_t::_setup_agc(chain_t chain, gain_mode_t gain_mode) +{ + boost::uint8_t gain_mode_reg = 0; + boost::uint8_t gain_mode_prev = 0; + boost::uint8_t gain_mode_bits_pos = 0; + + gain_mode_reg = _io_iface->peek8(0x0FA); + gain_mode_prev = (gain_mode_reg & 0x0F); + + if (chain == CHAIN_1) { + gain_mode_bits_pos = 0; + } else if (chain == CHAIN_2) { + gain_mode_bits_pos = 2; + } else + { + throw uhd::runtime_error("[ad9361_device_t] Wrong value for chain"); + } + + gain_mode_reg = (gain_mode_reg & (~(0x03<<gain_mode_bits_pos))); //clear mode bits + switch (gain_mode) { + case GAIN_MODE_MANUAL: + //leave bits cleared + break; + case GAIN_MODE_SLOW_AGC: + gain_mode_reg = (gain_mode_reg | (0x02<<gain_mode_bits_pos)); + break; + case GAIN_MODE_FAST_AGC: + gain_mode_reg = (gain_mode_reg | (0x01<<gain_mode_bits_pos)); + break; + default: + throw uhd::runtime_error("[ad9361_device_t] Gain mode does not exist"); + } + _io_iface->poke8(0x0FA, gain_mode_reg); + boost::uint8_t gain_mode_status = _io_iface->peek8(0x0FA); + gain_mode_status = (gain_mode_status & 0x0F); + /*Check if gain mode configuration needs to be reprogrammed*/ + if (((gain_mode_prev == 0) && (gain_mode_status != 0)) || ((gain_mode_prev != 0) && (gain_mode_status == 0))) { + if (gain_mode_status == 0) { + /*load manual mode config*/ + _setup_gain_control(false); + } else { + /*load agc mode config*/ + _setup_gain_control(true); + } + } +} + +void ad9361_device_t::set_agc(chain_t chain, bool enable) +{ + if(chain == CHAIN_1) { + _rx1_agc_enable = enable; + if(enable) { + _setup_agc(chain, _rx1_agc_mode); + } else { + _setup_agc(chain, GAIN_MODE_MANUAL); + } + } else if (chain == CHAIN_2){ + _rx2_agc_enable = enable; + if(enable) { + _setup_agc(chain, _rx2_agc_mode); + } else { + _setup_agc(chain, GAIN_MODE_MANUAL); + } + } else + { + throw uhd::runtime_error("[ad9361_device_t] Wrong value for chain"); + } +} + +void ad9361_device_t::set_agc_mode(chain_t chain, gain_mode_t gain_mode) +{ + if(chain == CHAIN_1) { + _rx1_agc_mode = gain_mode; + if(_rx1_agc_enable) { + _setup_agc(chain, _rx1_agc_mode); + } + } else if(chain == CHAIN_2){ + _rx2_agc_mode = gain_mode; + if(_rx2_agc_enable) { + _setup_agc(chain, _rx2_agc_mode); + } + } else + { + throw uhd::runtime_error("[ad9361_device_t] Wrong value for chain"); + } +} + +std::vector<std::string> ad9361_device_t::get_filter_names(direction_t direction) +{ + std::vector<std::string> ret; + if(direction == RX) { + for(std::map<std::string, filter_query_helper>::iterator it = _rx_filters.begin(); it != _rx_filters.end(); ++it) { + ret.push_back(it->first); + } + } else if (direction == TX) + { + for(std::map<std::string, filter_query_helper>::iterator it = _tx_filters.begin(); it != _tx_filters.end(); ++it) { + ret.push_back(it->first); + } + } + return ret; +} + +filter_info_base::sptr ad9361_device_t::get_filter(direction_t direction, chain_t chain, const std::string &name) +{ + if(direction == RX) { + if (not _rx_filters[name].get) + { + throw uhd::runtime_error("ad9361_device_t::get_filter this filter can not be read."); + } + return _rx_filters[name].get(direction, chain); + } else if (direction == TX) { + if (not _tx_filters[name].get) + { + throw uhd::runtime_error("ad9361_device_t::get_filter this filter can not be read."); + } + return _tx_filters[name].get(direction, chain); + } + + throw uhd::runtime_error("ad9361_device_t::get_filter wrong direction parameter."); +} + +void ad9361_device_t::set_filter(direction_t direction, chain_t chain, const std::string &name, filter_info_base::sptr filter) +{ + + if(direction == RX) { + if(not _rx_filters[name].set) + { + throw uhd::runtime_error("ad9361_device_t::set_filter this filter can not be written."); + } + _rx_filters[name].set(direction, chain, filter); + } else if (direction == TX) { + if(not _tx_filters[name].set) + { + throw uhd::runtime_error("ad9361_device_t::set_filter this filter can not be written."); + } + _tx_filters[name].set(direction, chain, filter); + } + +} + +double ad9361_device_t::set_bw_filter(direction_t direction, const double rf_bw) +{ + //both low pass filters are programmed to the same bw. However, their cutoffs will differ. + //Together they should create the requested bb bw. + double set_analog_bb_bw = 0; + if(direction == RX) + { + _rx_bb_lp_bw = _calibrate_baseband_rx_analog_filter(rf_bw); //returns bb bw + _rx_tia_lp_bw = _calibrate_rx_TIAs(rf_bw); + _rx_analog_bw = _rx_bb_lp_bw; + set_analog_bb_bw = _rx_analog_bw; + } else { + _tx_bb_lp_bw = _calibrate_baseband_tx_analog_filter(rf_bw); //returns bb bw + _tx_sec_lp_bw = _calibrate_secondary_tx_filter(rf_bw); + _tx_analog_bw = _tx_bb_lp_bw; + set_analog_bb_bw = _tx_analog_bw; + } + return (2.0 * set_analog_bb_bw); +} + +void ad9361_device_t::_set_fir_taps(direction_t direction, chain_t chain, const std::vector<boost::int16_t>& taps) +{ + size_t num_taps = taps.size(); + size_t num_taps_avail = _get_num_fir_taps(direction); + if(num_taps == num_taps_avail) + { + boost::scoped_array<boost::uint16_t> coeffs(new boost::uint16_t[num_taps_avail]); + for (size_t i = 0; i < num_taps_avail; i++) + { + coeffs[i] = boost::uint16_t(taps[i]); + } + _program_fir_filter(direction, chain, num_taps_avail, coeffs.get()); + } else if(num_taps < num_taps_avail){ + throw uhd::runtime_error("ad9361_device_t::_set_fir_taps not enough coefficients."); + } else { + throw uhd::runtime_error("ad9361_device_t::_set_fir_taps too many coefficients."); + } +} + +size_t ad9361_device_t::_get_num_fir_taps(direction_t direction) +{ + boost::uint8_t num = 0; + if(direction == RX) + num = _io_iface->peek8(0x0F5); + else + num = _io_iface->peek8(0x065); + num = ((num >> 5) & 0x07); + return ((num + 1) * 16); +} + +size_t ad9361_device_t::_get_fir_dec_int(direction_t direction) +{ + boost::uint8_t dec_int = 0; + if(direction == RX) + dec_int = _io_iface->peek8(0x003); + else + dec_int = _io_iface->peek8(0x002); + /* + * 0 = dec/int by 1 and bypass filter + * 1 = dec/int by 1 + * 2 = dec/int by 2 + * 3 = dec/int by 4 */ + dec_int = (dec_int & 0x03); + if(dec_int == 3) + { + return 4; + } + return dec_int; +} + +std::vector<boost::int16_t> ad9361_device_t::_get_fir_taps(direction_t direction, chain_t chain) +{ + int base; + size_t num_taps = _get_num_fir_taps(direction); + boost::uint8_t config; + boost::uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5; + config = reg_numtaps | 0x02; //start the programming clock + + if(chain == CHAIN_1) + { + config = config | (1 << 3); + } else if (chain == CHAIN_2){ + config = config | (1 << 4); + } else { + throw uhd::runtime_error("[ad9361_device_t] Can not read both chains synchronously"); + } + + if(direction == RX) + { + base = 0xF0; + } else { + base = 0x60; + } + + _io_iface->poke8(base+5,config); + + std::vector<boost::int16_t> taps; + boost::uint8_t lower_val; + boost::uint8_t higher_val; + boost::uint16_t coeff; + for(size_t i = 0;i < num_taps;i++) + { + _io_iface->poke8(base,0x00+i); + lower_val = _io_iface->peek8(base+3); + higher_val = _io_iface->peek8(base+4); + coeff = ((higher_val << 8) | lower_val); + taps.push_back(boost::int16_t(coeff)); + } + + config = (config & (~(1 << 1))); //disable filter clock + _io_iface->poke8(base+5,config); + return taps; +} + +/* + * Returns either RX TIA LPF or TX Secondary LPF + * depending on the direction. + * See UG570 for details on used scaling factors. */ +filter_info_base::sptr ad9361_device_t::_get_filter_lp_tia_sec(direction_t direction) +{ + double cutoff = 0; + + if(direction == RX) + { + cutoff = 2.5 * _rx_tia_lp_bw; + } else { + cutoff = 5 * _tx_sec_lp_bw; + } + + filter_info_base::sptr lp(new analog_filter_lp(filter_info_base::ANALOG_LOW_PASS, false, 0, "single-pole", cutoff, 20)); + return lp; +} + +/* + * Returns RX/TX BB LPF. + * See UG570 for details on used scaling factors. */ +filter_info_base::sptr ad9361_device_t::_get_filter_lp_bb(direction_t direction) +{ + double cutoff = 0; + if(direction == RX) + { + cutoff = 1.4 * _rx_bb_lp_bw; + } else { + cutoff = 1.6 * _tx_bb_lp_bw; + } + + filter_info_base::sptr bb_lp(new analog_filter_lp(filter_info_base::ANALOG_LOW_PASS, false, 1, "third-order Butterworth", cutoff, 60)); + return bb_lp; +} + +/* + * For RX direction the DEC3 is returned. + * For TX direction the INT3 is returned. */ +filter_info_base::sptr ad9361_device_t::_get_filter_dec_int_3(direction_t direction) +{ + boost::uint8_t enable = 0; + double rate = _adcclock_freq; + double full_scale; + size_t dec = 0; + size_t interpol = 0; + filter_info_base::filter_type type = filter_info_base::DIGITAL_I16; + std::string name; + boost::int16_t taps_array_rx[] = {55, 83, 0, -393, -580, 0, 1914, 4041, 5120, 4041, 1914, 0, -580, -393, 0, 83, 55}; + boost::int16_t taps_array_tx[] = {36, -19, 0, -156, -12, 0, 479, 233, 0, -1215, -993, 0, 3569, 6277, 8192, 6277, 3569, 0, -993, -1215, 0, 223, 479, 0, -12, -156, 0, -19, 36}; + std::vector<boost::int16_t> taps; + + filter_info_base::sptr ret; + + if(direction == RX) + { + full_scale = 16384; + dec = 3; + interpol = 1; + + enable = _io_iface->peek8(0x003); + enable = ((enable >> 4) & 0x03); + taps.assign(taps_array_rx, taps_array_rx + sizeof(taps_array_rx) / sizeof(boost::int16_t) ); + + } else { + full_scale = 8192; + dec = 1; + interpol = 3; + + boost::uint8_t use_dac_clk_div = _io_iface->peek8(0x00A); + use_dac_clk_div = ((use_dac_clk_div >> 3) & 0x01); + if(use_dac_clk_div == 1) + { + rate = rate / 2; + } + + enable = _io_iface->peek8(0x002); + enable = ((enable >> 4) & 0x03); + if(enable == 2) //0 => int. by 1, 1 => int. by 2 (HB3), 2 => int. by 3 + { + rate /= 3; + } + + taps.assign(taps_array_tx, taps_array_tx + sizeof(taps_array_tx) / sizeof(boost::int16_t) ); + } + + ret = filter_info_base::sptr(new digital_filter_base<boost::int16_t>(type, (enable != 2) ? true : false, 2, rate, interpol, dec, full_scale, taps.size(), taps)); + return ret; +} + +filter_info_base::sptr ad9361_device_t::_get_filter_hb_3(direction_t direction) +{ + boost::uint8_t enable = 0; + double rate = _adcclock_freq; + double full_scale = 0; + size_t dec = 1; + size_t interpol = 1; + filter_info_base::filter_type type = filter_info_base::DIGITAL_I16; + boost::int16_t taps_array_rx[] = {1, 4, 6, 4, 1}; + boost::int16_t taps_array_tx[] = {1, 2, 1}; + std::vector<boost::int16_t> taps; + + if(direction == RX) + { + full_scale = 16; + dec = 2; + + enable = _io_iface->peek8(0x003); + enable = ((enable >> 4) & 0x03); + taps.assign(taps_array_rx, taps_array_rx + sizeof(taps_array_rx) / sizeof(boost::int16_t) ); + } else { + full_scale = 2; + interpol = 2; + + boost::uint8_t use_dac_clk_div = _io_iface->peek8(0x00A); + use_dac_clk_div = ((use_dac_clk_div >> 3) & 0x01); + if(use_dac_clk_div == 1) + { + rate = rate / 2; + } + + enable = _io_iface->peek8(0x002); + enable = ((enable >> 4) & 0x03); + if(enable == 1) + { + rate /= 2; + } + taps.assign(taps_array_tx, taps_array_tx + sizeof(taps_array_tx) / sizeof(boost::int16_t) ); + } + + filter_info_base::sptr hb = filter_info_base::sptr(new digital_filter_base<boost::int16_t>(type, (enable != 1) ? true : false, 2, rate, interpol, dec, full_scale, taps.size(), taps)); + return hb; +} + +filter_info_base::sptr ad9361_device_t::_get_filter_hb_2(direction_t direction) +{ + boost::uint8_t enable = 0; + double rate = _adcclock_freq; + double full_scale = 0; + size_t dec = 1; + size_t interpol = 1; + filter_info_base::filter_type type = filter_info_base::DIGITAL_I16; + boost::int16_t taps_array[] = {-9, 0, 73, 128, 73, 0, -9}; + std::vector<boost::int16_t> taps(taps_array, taps_array + sizeof(taps_array) / sizeof(boost::int16_t) ); + + digital_filter_base<boost::int16_t>::sptr hb_3 = boost::dynamic_pointer_cast<digital_filter_base<boost::int16_t> >(_get_filter_hb_3(direction)); + digital_filter_base<boost::int16_t>::sptr dec_int_3 = boost::dynamic_pointer_cast<digital_filter_base<boost::int16_t> >(_get_filter_dec_int_3(direction)); + + if(direction == RX) + { + full_scale = 256; + dec = 2; + enable = _io_iface->peek8(0x003); + } else { + full_scale = 128; + interpol = 2; + enable = _io_iface->peek8(0x002); + } + + enable = ((enable >> 3) & 0x01); + + if(!(hb_3->is_bypassed())) + { + if(direction == RX) + { + rate = hb_3->get_output_rate(); + }else if (direction == TX) { + rate = hb_3->get_input_rate(); + if(enable) + { + rate /= 2; + } + } + } else { //else dec3/int3 or none of them is used. + if(direction == RX) + { + rate = dec_int_3->get_output_rate(); + }else if (direction == TX) { + rate = dec_int_3->get_input_rate(); + if(enable) + { + rate /= 2; + } + } + } + + filter_info_base::sptr hb(new digital_filter_base<boost::int16_t>(type, (enable == 0) ? true : false, 3, rate, interpol, dec, full_scale, taps.size(), taps)); + return hb; +} + +filter_info_base::sptr ad9361_device_t::_get_filter_hb_1(direction_t direction) +{ + boost::uint8_t enable = 0; + double rate = 0; + double full_scale = 0; + size_t dec = 1; + size_t interpol = 1; + filter_info_base::filter_type type = filter_info_base::DIGITAL_I16; + + std::vector<boost::int16_t> taps; + boost::int16_t taps_rx_array[] = {-8, 0, 42, 0, -147, 0, 619, 1013, 619, 0, -147, 0, 42, 0, -8}; + boost::int16_t taps_tx_array[] = {-53, 0, 313, 0, -1155, 0, 4989, 8192, 4989, 0, -1155, 0, 313, 0, -53}; + + digital_filter_base<boost::int16_t>::sptr hb_2 = boost::dynamic_pointer_cast<digital_filter_base<boost::int16_t> >(_get_filter_hb_2(direction)); + + if(direction == RX) + { + full_scale = 2048; + dec = 2; + enable = _io_iface->peek8(0x003); + enable = ((enable >> 2) & 0x01); + rate = hb_2->get_output_rate(); + taps.assign(taps_rx_array, taps_rx_array + sizeof(taps_rx_array) / sizeof(boost::int16_t) ); + } else if (direction == TX) { + full_scale = 8192; + interpol = 2; + enable = _io_iface->peek8(0x002); + enable = ((enable >> 2) & 0x01); + rate = hb_2->get_input_rate(); + if(enable) + { + rate /= 2; + } + taps.assign(taps_tx_array, taps_tx_array + sizeof(taps_tx_array) / sizeof(boost::int16_t) ); + } + + filter_info_base::sptr hb(new digital_filter_base<boost::int16_t>(type, (enable == 0) ? true : false, 4, rate, interpol, dec, full_scale, taps.size(), taps)); + return hb; +} + +filter_info_base::sptr ad9361_device_t::_get_filter_fir(direction_t direction, chain_t chain) +{ + double rate = 0; + size_t dec = 1; + size_t interpol = 1; + size_t max_num_taps = 128; + boost::uint8_t enable = 1; + + digital_filter_base<boost::int16_t>::sptr hb_1 = boost::dynamic_pointer_cast<digital_filter_base<boost::int16_t> >(_get_filter_hb_1(direction)); + + if(direction == RX) + { + dec = _get_fir_dec_int(direction); + if(dec == 0) + { + enable = 0; + dec = 1; + } + interpol = 1; + rate = hb_1->get_output_rate(); + }else if (direction == TX) { + interpol = _get_fir_dec_int(direction); + if(interpol == 0) + { + enable = 0; + interpol = 1; + } + dec = 1; + rate = hb_1->get_input_rate(); + if(enable) + { + rate /= interpol; + } + } + max_num_taps = _get_num_fir_taps(direction); + + filter_info_base::sptr fir(new digital_filter_fir<boost::int16_t>(filter_info_base::DIGITAL_FIR_I16, (enable == 0) ? true : false, 5, rate, interpol, dec, 32767, max_num_taps, _get_fir_taps(direction, chain))); + + return fir; +} + +void ad9361_device_t::_set_filter_fir(direction_t direction, chain_t channel, filter_info_base::sptr filter) +{ + digital_filter_fir<boost::int16_t>::sptr fir = boost::dynamic_pointer_cast<digital_filter_fir<boost::int16_t> >(filter); + //only write taps. Ignore everything else for now + _set_fir_taps(direction, channel, fir->get_taps()); +} + +/* + * If BW of one of the analog filters gets overwritten manually, + * _tx_analog_bw and _rx_analog_bw are not valid any more! + * For useful data in those variables set_bw_filter method should be used + */ +void ad9361_device_t::_set_filter_lp_bb(direction_t direction, filter_info_base::sptr filter) +{ + analog_filter_lp::sptr lpf = boost::dynamic_pointer_cast<analog_filter_lp>(filter); + double bw = lpf->get_cutoff(); + if(direction == RX) + { + //remember: this function takes rf bw as its input and calibrated to 1.4 x the given value + _rx_bb_lp_bw = _calibrate_baseband_rx_analog_filter(2 * bw / 1.4); //returns bb bw + + } else { + //remember: this function takes rf bw as its input and calibrates to 1.6 x the given value + _tx_bb_lp_bw = _calibrate_baseband_tx_analog_filter(2 * bw / 1.6); + } +} + +void ad9361_device_t::_set_filter_lp_tia_sec(direction_t direction, filter_info_base::sptr filter) +{ + analog_filter_lp::sptr lpf = boost::dynamic_pointer_cast<analog_filter_lp>(filter); + double bw = lpf->get_cutoff(); + if(direction == RX) + { + //remember: this function takes rf bw as its input and calibrated to 2.5 x the given value + _rx_tia_lp_bw = _calibrate_rx_TIAs(2 * bw / 2.5); //returns bb bw + + } else { + //remember: this function takes rf bw as its input and calibrates to 5 x the given value + _tx_sec_lp_bw = _calibrate_secondary_tx_filter(2 * bw / 5); + } +} + }} diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h index 71ce78da7..a2038ea01 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h @@ -8,6 +8,14 @@ #include <ad9361_client.h> #include <boost/noncopyable.hpp> #include <boost/thread/recursive_mutex.hpp> +#include <uhd/types/filters.hpp> +#include <uhd/types/sensors.hpp> +#include <complex> +#include <vector> +#include <map> +#include "boost/assign.hpp" +#include "boost/bind.hpp" +#include "boost/function.hpp" namespace uhd { namespace usrp { @@ -15,10 +23,41 @@ class ad9361_device_t : public boost::noncopyable { public: enum direction_t { RX, TX }; - enum chain_t { CHAIN_1, CHAIN_2 }; + enum gain_mode_t {GAIN_MODE_MANUAL, GAIN_MODE_SLOW_AGC, GAIN_MODE_FAST_AGC}; + enum chain_t { CHAIN_1, CHAIN_2, CHAIN_BOTH }; ad9361_device_t(ad9361_params::sptr client, ad9361_io::sptr io_iface) : - _client_params(client), _io_iface(io_iface) {} + _client_params(client), _io_iface(io_iface) { + + /* + * This Boost.Assign to_container() workaround is necessary because STL containers + * apparently confuse newer versions of MSVC. + * + * Source: http://www.boost.org/doc/libs/1_55_0/libs/assign/doc/#portability + */ + + _rx_filters = (boost::assign::map_list_of("LPF_TIA", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_lp_tia_sec, this, _1), + boost::bind(&ad9361_device_t::_set_filter_lp_tia_sec, this, _1, _3))) + ("LPF_BB", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_lp_bb, this, _1), + boost::bind(&ad9361_device_t::_set_filter_lp_bb, this, _1, _3))) + ("HB_3", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_hb_3, this, _1), 0)) + ("DEC_3", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_dec_int_3, this, _1), 0)) + ("HB_2", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_hb_2, this, _1), 0)) + ("HB_1", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_hb_1, this, _1), 0)) + ("FIR_1", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_fir, this, _1, _2), + boost::bind(&ad9361_device_t::_set_filter_fir, this, _1, _2, _3)))).to_container(_rx_filters); + + _tx_filters = (boost::assign::map_list_of("LPF_SECONDARY", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_lp_tia_sec, this, _1), + boost::bind(&ad9361_device_t::_set_filter_lp_tia_sec, this, _1, _3))) + ("LPF_BB", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_lp_bb, this, _1), + boost::bind(&ad9361_device_t::_set_filter_lp_bb, this, _1, _3))) + ("HB_3", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_hb_3, this, _1), 0)) + ("INT_3", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_dec_int_3, this, _1), 0)) + ("HB_2", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_hb_2, this, _1), 0)) + ("HB_1", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_hb_1, this, _1), 0)) + ("FIR_1", filter_query_helper(boost::bind(&ad9361_device_t::_get_filter_fir, this, _1, _2), + boost::bind(&ad9361_device_t::_set_filter_fir, this, _1, _2, _3)))).to_container(_tx_filters); + } /* Initialize the AD9361 codec. */ void initialize(); @@ -69,21 +108,56 @@ public: /* Read back the internal RSSI measurement data. */ double get_rssi(chain_t chain); + /*! Read the internal temperature sensor + *\param calibrate return raw sensor readings or apply calibration factor. + *\param num_samples number of measurements to average over + */ + double get_average_temperature(const double cal_offset = -30.0, const size_t num_samples = 3); + + /* Turn on/off AD9361's RX DC offset correction */ + void set_dc_offset_auto(direction_t direction, const bool on); + + /* Turn on/off AD9361's RX IQ imbalance correction */ + void set_iq_balance_auto(direction_t direction, const bool on); + + /* Configure AD9361's AGC module to use either fast or slow AGC mode. */ + void set_agc_mode(chain_t chain, gain_mode_t gain_mode); + + /* Enable AD9361's AGC gain mode. */ + void set_agc(chain_t chain, bool enable); + + /* Set bandwidth of AD9361's analog LP filters. + * Bandwidth should be RF bandwidth */ + double set_bw_filter(direction_t direction, const double rf_bw); + + /* + * Filter API implementation + * */ + filter_info_base::sptr get_filter(direction_t direction, chain_t chain, const std::string &name); + + void set_filter(direction_t direction, chain_t chain, const std::string &name, filter_info_base::sptr filter); + + std::vector<std::string> get_filter_names(direction_t direction); + //Constants static const double AD9361_MAX_GAIN; static const double AD9361_MAX_CLOCK_RATE; + static const double AD9361_CAL_VALID_WINDOW; static const double AD9361_RECOMMENDED_MAX_BANDWIDTH; private: //Methods void _program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs); void _setup_tx_fir(size_t num_taps, boost::int32_t interpolation); void _setup_rx_fir(size_t num_taps, boost::int32_t decimation); + void _program_fir_filter(direction_t direction, chain_t chain, int num_taps, boost::uint16_t *coeffs); + void _setup_tx_fir(size_t num_taps); + void _setup_rx_fir(size_t num_taps); void _calibrate_lock_bbpll(); void _calibrate_synth_charge_pumps(); - double _calibrate_baseband_rx_analog_filter(); - double _calibrate_baseband_tx_analog_filter(); - void _calibrate_secondary_tx_filter(); - void _calibrate_rx_TIAs(); + double _calibrate_baseband_rx_analog_filter(double rfbw); + double _calibrate_baseband_tx_analog_filter(double rfbw); + double _calibrate_secondary_tx_filter(double rfbw); + double _calibrate_rx_TIAs(double rfbw); void _setup_adc(); void _calibrate_baseband_dc_offset(); void _calibrate_rf_dc_offset(); @@ -92,12 +166,29 @@ private: //Methods void _calibrate_tx_quadrature(); void _program_mixer_gm_subtable(); void _program_gain_table(); - void _setup_gain_control(); + void _setup_gain_control(bool use_agc); void _setup_synth(direction_t direction, double vcorate); double _tune_bbvco(const double rate); void _reprogram_gains(); double _tune_helper(direction_t direction, const double value); double _setup_rates(const double rate); + double _get_temperature(const double cal_offset, const double timeout = 0.1); + void _configure_bb_rf_dc_tracking(const bool on); + void _setup_agc(chain_t chain, gain_mode_t gain_mode); + void _set_fir_taps(direction_t direction, chain_t chain, const std::vector<boost::int16_t>& taps); + std::vector<boost::int16_t> _get_fir_taps(direction_t direction, chain_t chain); + size_t _get_num_fir_taps(direction_t direction); + size_t _get_fir_dec_int(direction_t direction); + filter_info_base::sptr _get_filter_lp_tia_sec(direction_t direction); + filter_info_base::sptr _get_filter_lp_bb(direction_t direction); + filter_info_base::sptr _get_filter_dec_int_3(direction_t direction); + filter_info_base::sptr _get_filter_hb_3(direction_t direction); + filter_info_base::sptr _get_filter_hb_2(direction_t direction); + filter_info_base::sptr _get_filter_hb_1(direction_t direction); + filter_info_base::sptr _get_filter_fir(direction_t direction, chain_t chain); + void _set_filter_fir(direction_t direction, chain_t channel, filter_info_base::sptr filter); + void _set_filter_lp_bb(direction_t direction, filter_info_base::sptr filter); + void _set_filter_lp_tia_sec(direction_t direction, filter_info_base::sptr filter); private: //Members typedef struct { @@ -110,11 +201,30 @@ private: //Members boost::uint8_t bbftune_mode; } chip_regs_t; + struct filter_query_helper + { + filter_query_helper( + boost::function<filter_info_base::sptr (direction_t, chain_t)> p_get, + boost::function<void (direction_t, chain_t, filter_info_base::sptr)> p_set + ) : get(p_get), set(p_set) { } + + filter_query_helper(){ } + + boost::function<filter_info_base::sptr (direction_t, chain_t)> get; + boost::function<void (direction_t, chain_t, filter_info_base::sptr)> set; + }; + + std::map<std::string, filter_query_helper> _rx_filters; + std::map<std::string, filter_query_helper> _tx_filters; + //Interfaces ad9361_params::sptr _client_params; ad9361_io::sptr _io_iface; //Intermediate state double _rx_freq, _tx_freq, _req_rx_freq, _req_tx_freq; + double _last_calibration_freq; + double _rx_analog_bw, _tx_analog_bw, _rx_bb_lp_bw, _tx_bb_lp_bw; + double _rx_tia_lp_bw, _tx_sec_lp_bw; //! Current baseband sampling rate (this is the actual rate the device is // is running at) double _baseband_bw; @@ -129,10 +239,14 @@ private: //Members double _rx1_gain, _rx2_gain, _tx1_gain, _tx2_gain; boost::int32_t _tfir_factor; boost::int32_t _rfir_factor; + gain_mode_t _rx1_agc_mode, _rx2_agc_mode; + bool _rx1_agc_enable, _rx2_agc_enable; //Register soft-copies chip_regs_t _regs; //Synchronization boost::recursive_mutex _mutex; + bool _use_dc_offset_correction; + bool _use_iq_balance_correction; }; }} //namespace diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h index 786029d6e..553655fa5 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h @@ -7,91 +7,91 @@ #include <boost/cstdint.hpp> -boost::uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1}, - {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0}, - {4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0}, - {7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0}, - {10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0}, - {13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0}, - {16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0}, - {19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0}, - {22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0}, - {25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0}, - {28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x27,0x20,1}, - {31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0}, - {34,0x04,0x2B,0x00,1}, {35,0x24,0x21,0x20,0}, {36,0x24,0x22,0x00,1}, - {37,0x44,0x20,0x20,0}, {38,0x44,0x21,0x00,0}, {39,0x44,0x22,0x00,0}, - {40,0x44,0x23,0x00,0}, {41,0x44,0x24,0x00,0}, {42,0x44,0x25,0x00,0}, - {43,0x44,0x26,0x00,0}, {44,0x44,0x27,0x00,0}, {45,0x44,0x28,0x00,0}, - {46,0x44,0x29,0x00,0}, {47,0x44,0x2A,0x00,0}, {48,0x44,0x2B,0x00,0}, - {49,0x44,0x2C,0x00,0}, {50,0x44,0x2D,0x00,0}, {51,0x44,0x2E,0x00,0}, - {52,0x44,0x2F,0x00,0}, {53,0x44,0x30,0x00,0}, {54,0x44,0x31,0x00,0}, - {55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0}, - {58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0}, - {61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0}, - {64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1}, - {67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1}, - {70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1}, - {73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1}, - {76,0x6F,0x38,0x20,1}}; +boost::uint8_t gain_table_sub_1300mhz[77][3] = { +{ 0x00, 0x00, 0x20 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, +{ 0x00, 0x01, 0x00 }, { 0x00, 0x02, 0x00 }, { 0x00, 0x03, 0x00 }, +{ 0x00, 0x04, 0x00 }, { 0x00, 0x05, 0x00 }, { 0x01, 0x03, 0x20 }, +{ 0x01, 0x04, 0x00 }, { 0x01, 0x05, 0x00 }, { 0x01, 0x06, 0x00 }, +{ 0x01, 0x07, 0x00 }, { 0x01, 0x08, 0x00 }, { 0x01, 0x09, 0x00 }, +{ 0x01, 0x0A, 0x00 }, { 0x01, 0x0B, 0x00 }, { 0x01, 0x0C, 0x00 }, +{ 0x01, 0x0D, 0x00 }, { 0x01, 0x0E, 0x00 }, { 0x02, 0x09, 0x20 }, +{ 0x02, 0x0A, 0x00 }, { 0x02, 0x0B, 0x00 }, { 0x02, 0x0C, 0x00 }, +{ 0x02, 0x0D, 0x00 }, { 0x02, 0x0E, 0x00 }, { 0x02, 0x0F, 0x00 }, +{ 0x02, 0x10, 0x00 }, { 0x02, 0x2B, 0x20 }, { 0x02, 0x2C, 0x00 }, +{ 0x04, 0x28, 0x20 }, { 0x04, 0x29, 0x00 }, { 0x04, 0x2A, 0x00 }, +{ 0x04, 0x2B, 0x00 }, { 0x24, 0x20, 0x20 }, { 0x24, 0x21, 0x00 }, +{ 0x44, 0x20, 0x20 }, { 0x44, 0x21, 0x00 }, { 0x44, 0x22, 0x00 }, +{ 0x44, 0x23, 0x00 }, { 0x44, 0x24, 0x00 }, { 0x44, 0x25, 0x00 }, +{ 0x44, 0x26, 0x00 }, { 0x44, 0x27, 0x00 }, { 0x44, 0x28, 0x00 }, +{ 0x44, 0x29, 0x00 }, { 0x44, 0x2A, 0x00 }, { 0x44, 0x2B, 0x00 }, +{ 0x44, 0x2C, 0x00 }, { 0x44, 0x2D, 0x00 }, { 0x44, 0x2E, 0x00 }, +{ 0x44, 0x2F, 0x00 }, { 0x44, 0x30, 0x00 }, { 0x44, 0x31, 0x00 }, +{ 0x44, 0x32, 0x00 }, { 0x64, 0x2E, 0x20 }, { 0x64, 0x2F, 0x00 }, +{ 0x64, 0x30, 0x00 }, { 0x64, 0x31, 0x00 }, { 0x64, 0x32, 0x00 }, +{ 0x64, 0x33, 0x00 }, { 0x64, 0x34, 0x00 }, { 0x64, 0x35, 0x00 }, +{ 0x64, 0x36, 0x00 }, { 0x64, 0x37, 0x00 }, { 0x64, 0x38, 0x00 }, +{ 0x65, 0x38, 0x20 }, { 0x66, 0x38, 0x20 }, { 0x67, 0x38, 0x20 }, +{ 0x68, 0x38, 0x20 }, { 0x69, 0x38, 0x20 }, { 0x6A, 0x38, 0x20 }, +{ 0x6B, 0x38, 0x20 }, { 0x6C, 0x38, 0x20 }, { 0x6D, 0x38, 0x20 }, +{ 0x6E, 0x38, 0x20 }, { 0x6F, 0x38, 0x20 } }; -boost::uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1}, - {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0}, - {4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0}, - {7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0}, - {10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0}, - {13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0}, - {16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0}, - {19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0}, - {22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0}, - {25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0}, - {28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x28,0x20,1}, - {31,0x04,0x29,0x00,0}, {32,0x04,0x2A,0x00,0}, {33,0x04,0x2B,0x00,0}, - {34,0x24,0x20,0x20,0}, {35,0x24,0x21,0x00,1}, {36,0x44,0x20,0x20,0}, - {37,0x44,0x21,0x00,1}, {38,0x44,0x22,0x00,0}, {39,0x44,0x23,0x00,0}, - {40,0x44,0x24,0x00,0}, {41,0x44,0x25,0x00,0}, {42,0x44,0x26,0x00,0}, - {43,0x44,0x27,0x00,0}, {44,0x44,0x28,0x00,0}, {45,0x44,0x29,0x00,0}, - {46,0x44,0x2A,0x00,0}, {47,0x44,0x2B,0x00,0}, {48,0x44,0x2C,0x00,0}, - {49,0x44,0x2D,0x00,0}, {50,0x44,0x2E,0x00,0}, {51,0x44,0x2F,0x00,0}, - {52,0x44,0x30,0x00,0}, {53,0x44,0x31,0x00,0}, {54,0x44,0x32,0x00,0}, - {55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0}, - {58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0}, - {61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0}, - {64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1}, - {67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1}, - {70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1}, - {73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1}, - {76,0x6F,0x38,0x20,1}}; +boost::uint8_t gain_table_1300mhz_to_4000mhz[77][3] = { +{ 0x00, 0x00, 0x20 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, +{ 0x00, 0x01, 0x00 }, { 0x00, 0x02, 0x00 }, { 0x00, 0x03, 0x00 }, +{ 0x00, 0x04, 0x00 }, { 0x00, 0x05, 0x00 }, { 0x01, 0x03, 0x20 }, +{ 0x01, 0x04, 0x00 }, { 0x01, 0x05, 0x00 }, { 0x01, 0x06, 0x00 }, +{ 0x01, 0x07, 0x00 }, { 0x01, 0x08, 0x00 }, { 0x01, 0x09, 0x00 }, +{ 0x01, 0x0A, 0x00 }, { 0x01, 0x0B, 0x00 }, { 0x01, 0x0C, 0x00 }, +{ 0x01, 0x0D, 0x00 }, { 0x01, 0x0E, 0x00 }, { 0x02, 0x09, 0x20 }, +{ 0x02, 0x0A, 0x00 }, { 0x02, 0x0B, 0x00 }, { 0x02, 0x0C, 0x00 }, +{ 0x02, 0x0D, 0x00 }, { 0x02, 0x0E, 0x00 }, { 0x02, 0x0F, 0x00 }, +{ 0x02, 0x10, 0x00 }, { 0x02, 0x2B, 0x20 }, { 0x02, 0x2C, 0x00 }, +{ 0x04, 0x27, 0x20 }, { 0x04, 0x28, 0x00 }, { 0x04, 0x29, 0x00 }, +{ 0x04, 0x2A, 0x00 }, { 0x04, 0x2B, 0x00 }, { 0x24, 0x21, 0x20 }, +{ 0x24, 0x22, 0x00 }, { 0x44, 0x20, 0x20 }, { 0x44, 0x21, 0x00 }, +{ 0x44, 0x22, 0x00 }, { 0x44, 0x23, 0x00 }, { 0x44, 0x24, 0x00 }, +{ 0x44, 0x25, 0x00 }, { 0x44, 0x26, 0x00 }, { 0x44, 0x27, 0x00 }, +{ 0x44, 0x28, 0x00 }, { 0x44, 0x29, 0x00 }, { 0x44, 0x2A, 0x00 }, +{ 0x44, 0x2B, 0x00 }, { 0x44, 0x2C, 0x00 }, { 0x44, 0x2D, 0x00 }, +{ 0x44, 0x2E, 0x00 }, { 0x44, 0x2F, 0x00 }, { 0x44, 0x30, 0x00 }, +{ 0x44, 0x31, 0x00 }, { 0x64, 0x2E, 0x20 }, { 0x64, 0x2F, 0x00 }, +{ 0x64, 0x30, 0x00 }, { 0x64, 0x31, 0x00 }, { 0x64, 0x32, 0x00 }, +{ 0x64, 0x33, 0x00 }, { 0x64, 0x34, 0x00 }, { 0x64, 0x35, 0x00 }, +{ 0x64, 0x36, 0x00 }, { 0x64, 0x37, 0x00 }, { 0x64, 0x38, 0x00 }, +{ 0x65, 0x38, 0x20 }, { 0x66, 0x38, 0x20 }, { 0x67, 0x38, 0x20 }, +{ 0x68, 0x38, 0x20 }, { 0x69, 0x38, 0x20 }, { 0x6A, 0x38, 0x20 }, +{ 0x6B, 0x38, 0x20 }, { 0x6C, 0x38, 0x20 }, { 0x6D, 0x38, 0x20 }, +{ 0x6E, 0x38, 0x20 }, { 0x6F, 0x38, 0x20 } }; -boost::uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1}, - {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x00,0x00,0}, - {4,0x00,0x00,0x00,0}, {5,0x00,0x01,0x00,0}, {6,0x00,0x02,0x00,0}, - {7,0x00,0x03,0x00,0}, {8,0x01,0x01,0x20,1}, {9,0x01,0x02,0x00,0}, - {10,0x01,0x03,0x00,0}, {11,0x01,0x04,0x20,1}, {12,0x01,0x05,0x00,0}, - {13,0x01,0x06,0x00,0}, {14,0x01,0x07,0x00,0}, {15,0x01,0x08,0x00,0}, - {16,0x01,0x09,0x00,0}, {17,0x01,0x0A,0x00,0}, {18,0x01,0x0B,0x00,0}, - {19,0x01,0x0C,0x00,0}, {20,0x02,0x08,0x20,1}, {21,0x02,0x09,0x00,0}, - {22,0x02,0x0A,0x00,0}, {23,0x02,0x0B,0x20,1}, {24,0x02,0x0C,0x00,0}, - {25,0x02,0x0D,0x00,0}, {26,0x02,0x0E,0x00,0}, {27,0x02,0x0F,0x00,0}, - {28,0x02,0x2A,0x20,1}, {29,0x02,0x2B,0x00,0}, {30,0x04,0x27,0x20,1}, - {31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0}, - {34,0x04,0x2B,0x00,0}, {35,0x04,0x2C,0x00,0}, {36,0x04,0x2D,0x00,0}, - {37,0x24,0x20,0x20,1}, {38,0x24,0x21,0x00,0}, {39,0x24,0x22,0x00,0}, - {40,0x44,0x20,0x20,1}, {41,0x44,0x21,0x00,0}, {42,0x44,0x22,0x00,0}, - {43,0x44,0x23,0x00,0}, {44,0x44,0x24,0x00,0}, {45,0x44,0x25,0x00,0}, - {46,0x44,0x26,0x00,0}, {47,0x44,0x27,0x00,0}, {48,0x44,0x28,0x00,0}, - {49,0x44,0x29,0x00,0}, {50,0x44,0x2A,0x00,0}, {51,0x44,0x2B,0x00,0}, - {52,0x44,0x2C,0x00,0}, {53,0x44,0x2D,0x00,0}, {54,0x44,0x2E,0x00,0}, - {55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0}, - {58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0}, - {61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0}, - {64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1}, - {67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1}, - {70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1}, - {73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1}, - {76,0x6F,0x38,0x20,1}}; +boost::uint8_t gain_table_4000mhz_to_6000mhz[77][3] = { +{ 0x00, 0x00, 0x20 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, +{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x01, 0x00 }, +{ 0x00, 0x02, 0x00 }, { 0x00, 0x03, 0x00 }, { 0x01, 0x01, 0x20 }, +{ 0x01, 0x02, 0x00 }, { 0x01, 0x03, 0x00 }, { 0x01, 0x04, 0x20 }, +{ 0x01, 0x05, 0x00 }, { 0x01, 0x06, 0x00 }, { 0x01, 0x07, 0x00 }, +{ 0x01, 0x08, 0x00 }, { 0x01, 0x09, 0x00 }, { 0x01, 0x0A, 0x00 }, +{ 0x01, 0x0B, 0x00 }, { 0x01, 0x0C, 0x00 }, { 0x02, 0x08, 0x20 }, +{ 0x02, 0x09, 0x00 }, { 0x02, 0x0A, 0x00 }, { 0x02, 0x0B, 0x20 }, +{ 0x02, 0x0C, 0x00 }, { 0x02, 0x0D, 0x00 }, { 0x02, 0x0E, 0x00 }, +{ 0x02, 0x0F, 0x00 }, { 0x02, 0x2A, 0x20 }, { 0x02, 0x2B, 0x00 }, +{ 0x04, 0x27, 0x20 }, { 0x04, 0x28, 0x00 }, { 0x04, 0x29, 0x00 }, +{ 0x04, 0x2A, 0x00 }, { 0x04, 0x2B, 0x00 }, { 0x04, 0x2C, 0x00 }, +{ 0x04, 0x2D, 0x00 }, { 0x24, 0x20, 0x20 }, { 0x24, 0x21, 0x00 }, +{ 0x24, 0x22, 0x00 }, { 0x44, 0x20, 0x20 }, { 0x44, 0x21, 0x00 }, +{ 0x44, 0x22, 0x00 }, { 0x44, 0x23, 0x00 }, { 0x44, 0x24, 0x00 }, +{ 0x44, 0x25, 0x00 }, { 0x44, 0x26, 0x00 }, { 0x44, 0x27, 0x00 }, +{ 0x44, 0x28, 0x00 }, { 0x44, 0x29, 0x00 }, { 0x44, 0x2A, 0x00 }, +{ 0x44, 0x2B, 0x00 }, { 0x44, 0x2C, 0x00 }, { 0x44, 0x2D, 0x00 }, +{ 0x44, 0x2E, 0x00 }, { 0x64, 0x2E, 0x20 }, { 0x64, 0x2F, 0x00 }, +{ 0x64, 0x30, 0x00 }, { 0x64, 0x31, 0x00 }, { 0x64, 0x32, 0x00 }, +{ 0x64, 0x33, 0x00 }, { 0x64, 0x34, 0x00 }, { 0x64, 0x35, 0x00 }, +{ 0x64, 0x36, 0x00 }, { 0x64, 0x37, 0x00 }, { 0x64, 0x38, 0x00 }, +{ 0x65, 0x38, 0x20 }, { 0x66, 0x38, 0x20 }, { 0x67, 0x38, 0x20 }, +{ 0x68, 0x38, 0x20 }, { 0x69, 0x38, 0x20 }, { 0x6A, 0x38, 0x20 }, +{ 0x6B, 0x38, 0x20 }, { 0x6C, 0x38, 0x20 }, { 0x6D, 0x38, 0x20 }, +{ 0x6E, 0x38, 0x20 }, { 0x6F, 0x38, 0x20 } }; #endif /* INCLUDED_AD9361_GAIN_TABLES_HPP */ diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h b/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h index cb320e1f4..0475a5eb1 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h @@ -6,20 +6,20 @@ #define INCLUDED_AD9361_SYNTH_LUT_HPP -double vco_index[53] = {12605000000, 12245000000, 11906000000, 11588000000, - 11288000000, 11007000000, 10742000000, 10492000000, - 10258000000, 10036000000, 9827800000, 9631100000, - 9445300000, 9269800000, 9103600000, 8946300000, - 8797000000, 8655300000, 8520600000, 8392300000, - 8269900000, 8153100000, 8041400000, 7934400000, - 7831800000, 7733200000, 7638400000, 7547100000, - 7459000000, 7374000000, 7291900000, 7212400000, - 7135500000, 7061000000, 6988700000, 6918600000, - 6850600000, 6784600000, 6720500000, 6658200000, - 6597800000, 6539200000, 6482300000, 6427000000, - 6373400000, 6321400000, 6270900000, 6222000000, - 6174500000, 6128400000, 6083600000, 6040100000, - 5997700000}; +double vco_index[53] = {12605000000.0, 12245000000.0, 11906000000.0, 11588000000.0, + 11288000000.0, 11007000000.0, 10742000000.0, 10492000000.0, + 10258000000.0, 10036000000.0, 9827800000.0, 9631100000.0, + 9445300000.0, 9269800000.0, 9103600000.0, 8946300000.0, + 8797000000.0, 8655300000.0, 8520600000.0, 8392300000.0, + 8269900000.0, 8153100000.0, 8041400000.0, 7934400000.0, + 7831800000.0, 7733200000.0, 7638400000.0, 7547100000.0, + 7459000000.0, 7374000000.0, 7291900000.0, 7212400000.0, + 7135500000.0, 7061000000.0, 6988700000.0, 6918600000.0, + 6850600000.0, 6784600000.0, 6720500000.0, 6658200000.0, + 6597800000.0, 6539200000.0, 6482300000.0, 6427000000.0, + 6373400000.0, 6321400000.0, 6270900000.0, 6222000000.0, + 6174500000.0, 6128400000.0, 6083600000.0, 6040100000.0, + 5997700000.0}; int synth_cal_lut[53][12] = { {10, 0, 4, 0, 15, 8, 8, 13, 4, 13, 15, 9}, {10, 0, 4, 0, 15, 8, 9, 13, 4, 13, 15, 9}, diff --git a/host/lib/usrp/cores/gpio_core_200.hpp b/host/lib/usrp/cores/gpio_core_200.hpp index 164437f40..e22834fd9 100644 --- a/host/lib/usrp/cores/gpio_core_200.hpp +++ b/host/lib/usrp/cores/gpio_core_200.hpp @@ -1,5 +1,5 @@ // -// Copyright 2011,2014 Ettus Research LLC +// Copyright 2011,2014,2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -20,10 +20,34 @@ #include <uhd/config.hpp> #include <uhd/usrp/dboard_iface.hpp> +#include <boost/assign.hpp> #include <boost/cstdint.hpp> #include <boost/utility.hpp> #include <boost/shared_ptr.hpp> #include <uhd/types/wb_iface.hpp> +#include <map> + +typedef enum { + GPIO_CTRL, + GPIO_DDR, + GPIO_OUT, + GPIO_ATR_0X, + GPIO_ATR_RX, + GPIO_ATR_TX, + GPIO_ATR_XX +} gpio_attr_t; + +typedef std::map<gpio_attr_t,std::string> gpio_attr_map_t; +static const gpio_attr_map_t gpio_attr_map = + boost::assign::map_list_of + (GPIO_CTRL, "CTRL") + (GPIO_DDR, "DDR") + (GPIO_OUT, "OUT") + (GPIO_ATR_0X, "ATR_0X") + (GPIO_ATR_RX, "ATR_RX") + (GPIO_ATR_TX, "ATR_TX") + (GPIO_ATR_XX, "ATR_XX") +; class gpio_core_200 : boost::noncopyable{ public: diff --git a/host/lib/usrp/dboard_eeprom.cpp b/host/lib/usrp/dboard_eeprom.cpp index f2bee47a9..3b56ae19a 100644 --- a/host/lib/usrp/dboard_eeprom.cpp +++ b/host/lib/usrp/dboard_eeprom.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2011 Ettus Research LLC +// Copyright 2010-2011,2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -15,6 +15,7 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // +#include <uhd/types/byte_vector.hpp> #include <uhd/usrp/dboard_eeprom.hpp> #include <uhd/exception.hpp> #include <uhd/utils/log.hpp> @@ -27,30 +28,6 @@ using namespace uhd; using namespace uhd::usrp; -/*********************************************************************** - * Utility functions - **********************************************************************/ - -//! create a string from a byte vector, return empty if invalid ascii -static const std::string bytes_to_string(const byte_vector_t &bytes){ - std::string out; - BOOST_FOREACH(boost::uint8_t byte, bytes){ - if (byte < 32 or byte > 127) return out; - out += byte; - } - return out; -} - -//! create a byte vector from a string, null terminate unless max length -static const byte_vector_t string_to_bytes(const std::string &string, size_t max_length){ - byte_vector_t bytes; - for (size_t i = 0; i < std::min(string.size(), max_length); i++){ - bytes.push_back(string[i]); - } - if (bytes.size() < max_length - 1) bytes.push_back('\0'); - return bytes; -} - //////////////////////////////////////////////////////////////////////// // format of daughterboard EEPROM // 00: 0xDB code for ``I'm a daughterboard'' diff --git a/host/lib/usrp/e300/e300_defaults.hpp b/host/lib/usrp/e300/e300_defaults.hpp index 89afcb256..41e8453c4 100644 --- a/host/lib/usrp/e300/e300_defaults.hpp +++ b/host/lib/usrp/e300/e300_defaults.hpp @@ -24,7 +24,7 @@ namespace uhd { namespace usrp { namespace e300 { static const double DEFAULT_TICK_RATE = 32e6; static const double MAX_TICK_RATE = 50e6; -static const double MIN_TICK_RATE = 1e6; +static const double MIN_TICK_RATE = 10e6; static const double DEFAULT_TX_SAMP_RATE = 1.0e6; static const double DEFAULT_RX_SAMP_RATE = 1.0e6; @@ -70,7 +70,7 @@ public: digital_interface_delays_t get_digital_interface_timing() { digital_interface_delays_t delays; delays.rx_clk_delay = 0; - delays.rx_data_delay = 0xF; + delays.rx_data_delay = 0x8; delays.tx_clk_delay = 0; delays.tx_data_delay = 0xF; return delays; diff --git a/host/lib/usrp/e300/e300_fpga_defs.hpp b/host/lib/usrp/e300/e300_fpga_defs.hpp index eea4d7f63..fbbca329a 100644 --- a/host/lib/usrp/e300/e300_fpga_defs.hpp +++ b/host/lib/usrp/e300/e300_fpga_defs.hpp @@ -21,7 +21,7 @@ namespace uhd { namespace usrp { namespace e300 { namespace fpga { static const size_t NUM_RADIOS = 2; -static const boost::uint32_t COMPAT_MAJOR = 8; +static const boost::uint32_t COMPAT_MAJOR = 9; static const boost::uint32_t COMPAT_MINOR = 0; }}}} // namespace diff --git a/host/lib/usrp/e300/e300_impl.cpp b/host/lib/usrp/e300/e300_impl.cpp index 515fccc08..de2357100 100644 --- a/host/lib/usrp/e300/e300_impl.cpp +++ b/host/lib/usrp/e300/e300_impl.cpp @@ -473,15 +473,14 @@ e300_impl::e300_impl(const uhd::device_addr_t &device_addr) // internal gpios //////////////////////////////////////////////////////////////////// gpio_core_200::sptr fp_gpio = gpio_core_200::make(_radio_perifs[0].ctrl, TOREG(SR_FP_GPIO), RB32_FP_GPIO); - const std::vector<std::string> gpio_attrs = boost::assign::list_of("CTRL")("DDR")("OUT")("ATR_0X")("ATR_RX")("ATR_TX")("ATR_XX"); - BOOST_FOREACH(const std::string &attr, gpio_attrs) + BOOST_FOREACH(const gpio_attr_map_t::value_type attr, gpio_attr_map) { - _tree->create<boost::uint32_t>(mb_path / "gpio" / "INT0" / attr) - .subscribe(boost::bind(&e300_impl::_set_internal_gpio, this, fp_gpio, attr, _1)) + _tree->create<boost::uint32_t>(mb_path / "gpio" / "INT0" / attr.second) + .subscribe(boost::bind(&e300_impl::_set_internal_gpio, this, fp_gpio, attr.first, _1)) .set(0); } _tree->create<boost::uint8_t>(mb_path / "gpio" / "INT0" / "READBACK") - .publish(boost::bind(&e300_impl::_get_internal_gpio, this, fp_gpio, "READBACK")); + .publish(boost::bind(&e300_impl::_get_internal_gpio, this, fp_gpio)); //////////////////////////////////////////////////////////////////// @@ -587,32 +586,35 @@ e300_impl::e300_impl(const uhd::device_addr_t &device_addr) boost::this_thread::sleep(boost::posix_time::seconds(1)); } -boost::uint8_t e300_impl::_get_internal_gpio( - gpio_core_200::sptr gpio, - const std::string &) +boost::uint8_t e300_impl::_get_internal_gpio(gpio_core_200::sptr gpio) { return boost::uint32_t(gpio->read_gpio(dboard_iface::UNIT_RX)); } void e300_impl::_set_internal_gpio( gpio_core_200::sptr gpio, - const std::string &attr, + const gpio_attr_t attr, const boost::uint32_t value) { - if (attr == "CTRL") + switch (attr) + { + case GPIO_CTRL: return gpio->set_pin_ctrl(dboard_iface::UNIT_RX, value); - else if (attr == "DDR") + case GPIO_DDR: return gpio->set_gpio_ddr(dboard_iface::UNIT_RX, value); - else if (attr == "OUT") + case GPIO_OUT: return gpio->set_gpio_out(dboard_iface::UNIT_RX, value); - else if (attr == "ATR_0X") + case GPIO_ATR_0X: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, value); - else if (attr == "ATR_RX") + case GPIO_ATR_RX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, value); - else if (attr == "ATR_TX") + case GPIO_ATR_TX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, value); - else if (attr == "ATR_XX") + case GPIO_ATR_XX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, value); + default: + UHD_THROW_INVALID_CODE_PATH(); + } } uhd::sensor_value_t e300_impl::_get_fe_pll_lock(const bool is_tx) @@ -654,6 +656,17 @@ void e300_impl::_enforce_tick_rate_limits( % direction )); } + // Minimum rate restriction due to MMCM used in capture interface to AD9361. + // Xilinx Artix-7 FPGA MMCM minimum input frequency is 10 MHz. + const double min_tick_rate = uhd::usrp::e300::MIN_TICK_RATE / ((chan_count <= 1) ? 1 : 2); + if (tick_rate - min_tick_rate < 0.0) + { + throw uhd::value_error(boost::str( + boost::format("current master clock rate (%.6f MHz) set below minimum possible master clock rate (%.6f MHz)") + % (tick_rate/1e6) + % (min_tick_rate/1e6) + )); + } } } @@ -1040,6 +1053,8 @@ void e300_impl::_setup_radio(const size_t dspno) _tree->create<int>(rf_fe_path / "sensors"); //empty TODO _tree->create<sensor_value_t>(rf_fe_path / "sensors" / "lo_locked") .publish(boost::bind(&e300_impl::_get_fe_pll_lock, this, direction == "tx")); + _tree->create<sensor_value_t>(rf_fe_path / "sensors" / "temp") + .publish(boost::bind(&ad9361_ctrl::get_temperature, _codec_ctrl)); BOOST_FOREACH(const std::string &name, ad9361_ctrl::get_gain_names(key)) { _tree->create<meta_range_t>(rf_fe_path / "gains" / name / "range") @@ -1065,6 +1080,18 @@ void e300_impl::_setup_radio(const size_t dspno) _tree->create<meta_range_t>(rf_fe_path / "freq" / "range") .publish(boost::bind(&ad9361_ctrl::get_rf_freq_range)); + //only in local mode + if(_xport_path == AXI) { + //add all frontend filters + std::vector<std::string> filter_names = _codec_ctrl->get_filter_names(key); + for(size_t i = 0;i < filter_names.size(); i++) + { + _tree->create<filter_info_base::sptr>(rf_fe_path / "filters" / filter_names[i] / "value" ) + .publish(boost::bind(&ad9361_ctrl::get_filter, _codec_ctrl, key, filter_names[i])) + .subscribe(boost::bind(&ad9361_ctrl::set_filter, _codec_ctrl, key, filter_names[i], _1)); + } + } + //setup RX related stuff if (key[0] == 'R') { static const std::vector<std::string> ants = boost::assign::list_of("TX/RX")("RX2"); diff --git a/host/lib/usrp/e300/e300_impl.hpp b/host/lib/usrp/e300/e300_impl.hpp index 7f83c16ed..c530a5d72 100644 --- a/host/lib/usrp/e300/e300_impl.hpp +++ b/host/lib/usrp/e300/e300_impl.hpp @@ -267,13 +267,11 @@ private: // methods uhd::sensor_value_t _get_fe_pll_lock(const bool is_tx); // internal gpios - boost::uint8_t _get_internal_gpio( - gpio_core_200::sptr, - const std::string &); + boost::uint8_t _get_internal_gpio(gpio_core_200::sptr); void _set_internal_gpio( gpio_core_200::sptr gpio, - const std::string &attr, + const gpio_attr_t attr, const boost::uint32_t value); private: // members diff --git a/host/lib/usrp/e300/e300_network.cpp b/host/lib/usrp/e300/e300_network.cpp index 408f9e62d..d68dc4541 100644 --- a/host/lib/usrp/e300/e300_network.cpp +++ b/host/lib/usrp/e300/e300_network.cpp @@ -230,6 +230,27 @@ static void e300_codec_ctrl_tunnel( case codec_xact_t::ACTION_GET_RSSI: out->rssi = _codec_ctrl->get_rssi(which_str).to_real(); break; + case codec_xact_t::ACTION_GET_TEMPERATURE: + out->temp = _codec_ctrl->get_temperature().to_real(); + break; + case codec_xact_t::ACTION_SET_DC_OFFSET_AUTO: + _codec_ctrl->set_dc_offset_auto(which_str, in->use_dc_correction == 1); + break; + case codec_xact_t::ACTION_SET_IQ_BALANCE_AUTO: + _codec_ctrl->set_iq_balance_auto(which_str, in->use_iq_correction == 1); + case codec_xact_t::ACTION_SET_AGC: + _codec_ctrl->set_agc(which_str, in->use_agc == 1); + break; + case codec_xact_t::ACTION_SET_AGC_MODE: + if(in->agc_mode == 0) { + _codec_ctrl->set_agc_mode(which_str, "slow"); + } else if (in->agc_mode == 1) { + _codec_ctrl->set_agc_mode(which_str, "fast"); + } + break; + case codec_xact_t::ACTION_SET_BW: + out->bw = _codec_ctrl->set_bw_filter(which_str, in->bw); + break; default: UHD_MSG(status) << "Got unknown request?!" << std::endl; //Zero out actions to fail this request on client diff --git a/host/lib/usrp/e300/e300_remote_codec_ctrl.cpp b/host/lib/usrp/e300/e300_remote_codec_ctrl.cpp index 6742f5f86..9708634dd 100644 --- a/host/lib/usrp/e300/e300_remote_codec_ctrl.cpp +++ b/host/lib/usrp/e300/e300_remote_codec_ctrl.cpp @@ -130,10 +130,118 @@ public: _args.bits = uhd::htonx<boost::uint32_t>(0); _transact(); - return sensor_value_t("RSSI", _retval.rssi, "dB"); } + sensor_value_t get_temperature() + { + _clear(); + _args.action = uhd::htonx<boost::uint32_t>(transaction_t::ACTION_GET_TEMPERATURE); + _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_NONE); /*Unused*/ + _args.bits = uhd::htonx<boost::uint32_t>(0); + + _transact(); + return sensor_value_t("temp", _retval.temp, "C"); + } + + void set_dc_offset_auto(const std::string &which, const bool on) + { + _clear(); + _args.action = uhd::htonx<boost::uint32_t>(transaction_t::ACTION_SET_DC_OFFSET_AUTO); + if (which == "TX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX1); + else if (which == "TX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX2); + else if (which == "RX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX1); + else if (which == "RX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX2); + else throw std::runtime_error("e300_remote_codec_ctrl_impl incorrect chain string."); + _args.use_dc_correction = on ? 1 : 0; + + _transact(); + } + + void set_iq_balance_auto(const std::string &which, const bool on) + { + _clear(); + _args.action = uhd::htonx<boost::uint32_t>(transaction_t::ACTION_SET_IQ_BALANCE_AUTO); + if (which == "TX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX1); + else if (which == "TX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX2); + else if (which == "RX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX1); + else if (which == "RX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX2); + else throw std::runtime_error("e300_remote_codec_ctrl_impl incorrect chain string."); + _args.use_iq_correction = on ? 1 : 0; + + _transact(); + } + + void set_agc(const std::string &which, bool enable) + { + _clear(); + _args.action = uhd::htonx<boost::uint32_t>(transaction_t::ACTION_SET_AGC); + if (which == "TX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX1); + else if (which == "TX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX2); + else if (which == "RX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX1); + else if (which == "RX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX2); + else throw std::runtime_error("e300_remote_codec_ctrl_impl incorrect chain string."); + _args.use_agc = enable ? 1 : 0; + + _transact(); + } + + void set_agc_mode(const std::string &which, const std::string &mode) + { + _clear(); + _args.action = uhd::htonx<boost::uint32_t>(transaction_t::ACTION_SET_AGC_MODE); + + if (which == "TX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX1); + else if (which == "TX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX2); + else if (which == "RX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX1); + else if (which == "RX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX2); + else throw std::runtime_error("e300_remote_codec_ctrl_impl incorrect chain string."); + + if(mode == "slow") { + _args.agc_mode = 0; + } else if (mode == "fast") { + _args.agc_mode = 1; + } else { + throw std::runtime_error("e300_remote_codec_ctrl_impl incorrect agc mode."); + } + + _transact(); + } + + //! set the filter bandwidth for the frontend's analog low pass + double set_bw_filter(const std::string &which, const double bw) + { + _clear(); + _args.action = uhd::htonx<boost::uint32_t>(transaction_t::ACTION_SET_BW); + if (which == "TX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX1); + else if (which == "TX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_TX2); + else if (which == "RX1") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX1); + else if (which == "RX2") _args.which = uhd::htonx<boost::uint32_t>(transaction_t::CHAIN_RX2); + else throw std::runtime_error("e300_remote_codec_ctrl_impl incorrect chain string."); + _args.bw = bw; + + _transact(); + return _retval.bw; + } + + //! List all available filters by name + std::vector<std::string> get_filter_names(const std::string &) + { + UHD_THROW_INVALID_CODE_PATH(); + } + + //! Return a list of all filters + filter_info_base::sptr get_filter(const std::string &, const std::string &) + { + UHD_THROW_INVALID_CODE_PATH(); + } + + //! Write back a filter + void set_filter(const std::string &, const std::string &, const filter_info_base::sptr) + { + UHD_THROW_INVALID_CODE_PATH(); + } + private: void _transact() { { diff --git a/host/lib/usrp/e300/e300_remote_codec_ctrl.hpp b/host/lib/usrp/e300/e300_remote_codec_ctrl.hpp index e21f2ef95..43723e0d5 100644 --- a/host/lib/usrp/e300/e300_remote_codec_ctrl.hpp +++ b/host/lib/usrp/e300/e300_remote_codec_ctrl.hpp @@ -34,6 +34,12 @@ public: double gain; double freq; double rssi; + double temp; + double bw; + boost::uint32_t use_dc_correction; + boost::uint32_t use_iq_correction; + boost::uint32_t use_agc; + boost::uint32_t agc_mode; boost::uint64_t bits; }; @@ -44,7 +50,13 @@ public: static const boost::uint32_t ACTION_TUNE = 13; static const boost::uint32_t ACTION_SET_LOOPBACK = 14; static const boost::uint32_t ACTION_GET_RSSI = 15; - static const boost::uint32_t ACTION_GET_FREQ = 16; + static const boost::uint32_t ACTION_GET_TEMPERATURE = 16; + static const boost::uint32_t ACTION_SET_DC_OFFSET_AUTO = 17; + static const boost::uint32_t ACTION_SET_IQ_BALANCE_AUTO = 18; + static const boost::uint32_t ACTION_SET_AGC = 19; + static const boost::uint32_t ACTION_SET_AGC_MODE = 20; + static const boost::uint32_t ACTION_SET_BW = 21; + static const boost::uint32_t ACTION_GET_FREQ = 22; //Values for "which" static const boost::uint32_t CHAIN_NONE = 0; diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp index 68c084589..9c92fe252 100644 --- a/host/lib/usrp/mboard_eeprom.cpp +++ b/host/lib/usrp/mboard_eeprom.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2013 Ettus Research LLC +// Copyright 2010-2013,2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -16,6 +16,7 @@ // #include <uhd/usrp/mboard_eeprom.hpp> +#include <uhd/types/byte_vector.hpp> #include <uhd/types/mac_addr.hpp> #include <uhd/utils/byteswap.hpp> #include <boost/asio/ip/address_v4.hpp> @@ -39,32 +40,6 @@ static const size_t NAME_MAX_LEN = 32 - SERIAL_LEN; * Utility functions **********************************************************************/ -//! A wrapper around std::copy that takes ranges instead of iterators. -template<typename RangeSrc, typename RangeDst> inline -void byte_copy(const RangeSrc &src, RangeDst &dst){ - std::copy(boost::begin(src), boost::end(src), boost::begin(dst)); -} - -//! create a string from a byte vector, return empty if invalid ascii -static const std::string bytes_to_string(const byte_vector_t &bytes){ - std::string out; - BOOST_FOREACH(boost::uint8_t byte, bytes){ - if (byte < 32 or byte > 127) return out; - out += byte; - } - return out; -} - -//! create a byte vector from a string, null terminate unless max length -static const byte_vector_t string_to_bytes(const std::string &string, size_t max_length){ - byte_vector_t bytes; - for (size_t i = 0; i < std::min(string.size(), max_length); i++){ - bytes.push_back(string[i]); - } - if (bytes.size() < max_length - 1) bytes.push_back('\0'); - return bytes; -} - //! convert a string to a byte vector to write to eeprom static byte_vector_t string_to_uint16_bytes(const std::string &num_str){ const boost::uint16_t num = boost::lexical_cast<boost::uint16_t>(num_str); diff --git a/host/lib/usrp/multi_usrp.cpp b/host/lib/usrp/multi_usrp.cpp index 794438b90..1866255c9 100644 --- a/host/lib/usrp/multi_usrp.cpp +++ b/host/lib/usrp/multi_usrp.cpp @@ -30,6 +30,8 @@ #include <boost/thread.hpp> #include <boost/foreach.hpp> #include <boost/format.hpp> +#include <boost/algorithm/string.hpp> +#include <algorithm> #include <cmath> using namespace uhd; @@ -431,6 +433,9 @@ public: ******************************************************************/ void set_master_clock_rate(double rate, size_t mboard){ if (mboard != ALL_MBOARDS){ + if (_tree->exists(mb_root(mboard) / "auto_tick_rate")) { + _tree->access<bool>(mb_root(mboard) / "auto_tick_rate").set(false); + } _tree->access<double>(mb_root(mboard) / "tick_rate").set(rate); return; } @@ -821,6 +826,26 @@ public: } void set_rx_gain(double gain, const std::string &name, size_t chan){ + /* Check if any AGC mode is enable and if so warn the user */ + if (chan != ALL_CHANS) { + if (_tree->exists(rx_rf_fe_root(chan) / "gain" / "agc")) { + bool agc = _tree->access<bool>(rx_rf_fe_root(chan) / "gain" / "agc" / "enable").get(); + if(agc) { + UHD_MSG(warning) << "AGC enabled for this channel. Setting will be ignored." << std::endl; + } + } + } else { + for (size_t c = 0; c < get_rx_num_channels(); c++){ + if (_tree->exists(rx_rf_fe_root(c) / "gain" / "agc")) { + bool agc = _tree->access<bool>(rx_rf_fe_root(chan) / "gain" / "agc" / "enable").get(); + if(agc) { + UHD_MSG(warning) << "AGC enabled for this channel. Setting will be ignored." << std::endl; + } + } + } + } + /* Apply gain setting. + * If device is in AGC mode it will ignore the setting. */ try { return rx_gain_group(chan)->set_value(gain, name); } catch (uhd::key_error &) { @@ -828,6 +853,32 @@ public: } } + void set_normalized_rx_gain(double gain, size_t chan = 0) + { + if (gain > 1.0 || gain < 0.0) { + throw uhd::runtime_error("Normalized gain out of range, must be in [0, 1]."); + } + gain_range_t gain_range = get_rx_gain_range(ALL_GAINS, chan); + double abs_gain = (gain * (gain_range.stop() - gain_range.start())) + gain_range.start(); + set_rx_gain(abs_gain, ALL_GAINS, chan); + } + + void set_rx_agc(bool enable, size_t chan = 0) + { + if (chan != ALL_CHANS){ + if (_tree->exists(rx_rf_fe_root(chan) / "gain" / "agc" / "enable")) { + _tree->access<bool>(rx_rf_fe_root(chan) / "gain" / "agc" / "enable").set(enable); + } else { + UHD_MSG(warning) << "AGC is not available on this device." << std::endl; + } + return; + } + for (size_t c = 0; c < get_rx_num_channels(); c++){ + this->set_rx_agc(enable, c); + } + + } + double get_rx_gain(const std::string &name, size_t chan){ try { return rx_gain_group(chan)->get_value(name); @@ -836,6 +887,21 @@ public: } } + double get_normalized_rx_gain(size_t chan) + { + gain_range_t gain_range = get_rx_gain_range(ALL_GAINS, chan); + double gain_range_width = gain_range.stop() - gain_range.start(); + // In case we have a device without a range of gains: + if (gain_range_width == 0.0) { + return 0; + } + double norm_gain = (get_rx_gain(ALL_GAINS, chan) - gain_range.start()) / gain_range_width; + // Avoid rounding errors: + if (norm_gain > 1.0) return 1.0; + if (norm_gain < 0.0) return 0.0; + return norm_gain; + } + gain_range_t get_rx_gain_range(const std::string &name, size_t chan){ try { return rx_gain_group(chan)->get_range(name); @@ -888,6 +954,9 @@ public: if (chan != ALL_CHANS){ if (_tree->exists(rx_fe_root(chan) / "dc_offset" / "enable")) { _tree->access<bool>(rx_fe_root(chan) / "dc_offset" / "enable").set(enb); + } else if (_tree->exists(rx_rf_fe_root(chan) / "dc_offset" / "enable")) { + /*For B2xx devices the dc-offset correction is implemented in the rf front-end*/ + _tree->access<bool>(rx_rf_fe_root(chan) / "dc_offset" / "enable").set(enb); } else { UHD_MSG(warning) << "Setting DC offset compensation is not possible on this device." << std::endl; } @@ -912,6 +981,20 @@ public: } } + void set_rx_iq_balance(const bool enb, size_t chan){ + if (chan != ALL_CHANS){ + if (_tree->exists(rx_rf_fe_root(chan) / "iq_balance" / "enable")) { + _tree->access<bool>(rx_rf_fe_root(chan) / "iq_balance" / "enable").set(enb); + } else { + UHD_MSG(warning) << "Setting IQ imbalance compensation is not possible on this device." << std::endl; + } + return; + } + for (size_t c = 0; c < get_rx_num_channels(); c++){ + this->set_rx_iq_balance(enb, c); + } + } + void set_rx_iq_balance(const std::complex<double> &offset, size_t chan){ if (chan != ALL_CHANS){ if (_tree->exists(rx_fe_root(chan) / "iq_balance" / "value")) { @@ -926,6 +1009,87 @@ public: } } + std::vector<std::string> get_filter_names(const std::string &search_mask) + { + std::vector<std::string> ret; + + for (size_t chan = 0; chan < get_rx_num_channels(); chan++){ + + if (_tree->exists(rx_rf_fe_root(chan) / "filters")) { + std::vector<std::string> names = _tree->list(rx_rf_fe_root(chan) / "filters"); + for(size_t i = 0; i < names.size(); i++) + { + std::string name = rx_rf_fe_root(chan) / "filters" / names[i]; + if((search_mask.empty()) or boost::contains(name, search_mask)) { + ret.push_back(name); + } + } + } + if (_tree->exists(rx_dsp_root(chan) / "filters")) { + std::vector<std::string> names = _tree->list(rx_dsp_root(chan) / "filters"); + for(size_t i = 0; i < names.size(); i++) + { + std::string name = rx_dsp_root(chan) / "filters" / names[i]; + if((search_mask.empty()) or (boost::contains(name, search_mask))) { + ret.push_back(name); + } + } + } + + } + + for (size_t chan = 0; chan < get_tx_num_channels(); chan++){ + + if (_tree->exists(tx_rf_fe_root(chan) / "filters")) { + std::vector<std::string> names = _tree->list(tx_rf_fe_root(chan) / "filters"); + for(size_t i = 0; i < names.size(); i++) + { + std::string name = tx_rf_fe_root(chan) / "filters" / names[i]; + if((search_mask.empty()) or (boost::contains(name, search_mask))) { + ret.push_back(name); + } + } + } + if (_tree->exists(rx_dsp_root(chan) / "filters")) { + std::vector<std::string> names = _tree->list(tx_dsp_root(chan) / "filters"); + for(size_t i = 0; i < names.size(); i++) + { + std::string name = tx_dsp_root(chan) / "filters" / names[i]; + if((search_mask.empty()) or (boost::contains(name, search_mask))) { + ret.push_back(name); + } + } + } + + } + + return ret; + } + + filter_info_base::sptr get_filter(const std::string &path) + { + std::vector<std::string> possible_names = get_filter_names(""); + std::vector<std::string>::iterator it; + it = find(possible_names.begin(), possible_names.end(), path); + if (it == possible_names.end()) { + throw uhd::runtime_error("Attempting to get non-existing filter: "+path); + } + + return _tree->access<filter_info_base::sptr>(path / "value").get(); + } + + void set_filter(const std::string &path, filter_info_base::sptr filter) + { + std::vector<std::string> possible_names = get_filter_names(""); + std::vector<std::string>::iterator it; + it = find(possible_names.begin(), possible_names.end(), path); + if (it == possible_names.end()) { + throw uhd::runtime_error("Attempting to set non-existing filter: "+path); + } + + _tree->access<filter_info_base::sptr>(path / "value").set(filter); + } + /******************************************************************* * TX methods ******************************************************************/ @@ -1029,6 +1193,17 @@ public: } } + void set_normalized_tx_gain(double gain, size_t chan = 0) + { + if (gain > 1.0 || gain < 0.0) { + throw uhd::runtime_error("Normalized gain out of range, must be in [0, 1]."); + } + gain_range_t gain_range = get_tx_gain_range(ALL_GAINS, chan); + double abs_gain = (gain * (gain_range.stop() - gain_range.start())) + gain_range.start(); + set_tx_gain(abs_gain, ALL_GAINS, chan); + } + + double get_tx_gain(const std::string &name, size_t chan){ try { return tx_gain_group(chan)->get_value(name); @@ -1037,6 +1212,21 @@ public: } } + double get_normalized_tx_gain(size_t chan) + { + gain_range_t gain_range = get_tx_gain_range(ALL_GAINS, chan); + double gain_range_width = gain_range.stop() - gain_range.start(); + // In case we have a device without a range of gains: + if (gain_range_width == 0.0) { + return 0.0; + } + double norm_gain = (get_rx_gain(ALL_GAINS, chan) - gain_range.start()) / gain_range_width; + // Avoid rounding errors: + if (norm_gain > 1.0) return 1.0; + if (norm_gain < 0.0) return 0.0; + return norm_gain; + } + gain_range_t get_tx_gain_range(const std::string &name, size_t chan){ try { return tx_gain_group(chan)->get_range(name); diff --git a/host/lib/usrp/x300/x300_adc_ctrl.cpp b/host/lib/usrp/x300/x300_adc_ctrl.cpp index b0e4e4b95..edb4ce885 100644 --- a/host/lib/usrp/x300/x300_adc_ctrl.cpp +++ b/host/lib/usrp/x300/x300_adc_ctrl.cpp @@ -55,8 +55,8 @@ public: _ads62p48_regs.lvds_cmos = ads62p48_regs_t::LVDS_CMOS_DDR_LVDS; _ads62p48_regs.channel_control = ads62p48_regs_t::CHANNEL_CONTROL_INDEPENDENT; _ads62p48_regs.data_format = ads62p48_regs_t::DATA_FORMAT_2S_COMPLIMENT; - _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_MINUS7_26; - _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_MINUS7_26; + _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_NORMAL; + _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_NORMAL; this->send_ads62p48_reg(0); diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index 6450686dd..0812bcc8e 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -21,6 +21,7 @@ #include <uhd/utils/math.hpp> #include <boost/cstdint.hpp> #include <boost/format.hpp> +#include <boost/math/special_functions/round.hpp> #include <stdexcept> #include <cmath> #include <cstdlib> @@ -29,6 +30,30 @@ static const double X300_REF_CLK_OUT_RATE = 10e6; static const boost::uint16_t X300_MAX_CLKOUT_DIV = 1045; static const double X300_DEFAULT_DBOARD_CLK_RATE = 50e6; +struct x300_clk_delays { + x300_clk_delays() : + fpga_dly_ns(0.0),adc_dly_ns(0.0),dac_dly_ns(0.0),db_rx_dly_ns(0.0),db_tx_dly_ns(0.0) + {} + x300_clk_delays(double fpga, double adc, double dac, double db_rx, double db_tx) : + fpga_dly_ns(fpga),adc_dly_ns(adc),dac_dly_ns(dac),db_rx_dly_ns(db_rx),db_tx_dly_ns(db_tx) + {} + + double fpga_dly_ns; + double adc_dly_ns; + double dac_dly_ns; + double db_rx_dly_ns; + double db_tx_dly_ns; +}; + +// Tune the FPGA->ADC clock delay to ensure a safe ADC_SSCLK -> RADIO_CLK crossing. +// If the FPGA_CLK is delayed, we also need to delay the reference clocks going to the DAC +// because the data interface clock is generated from FPGA_CLK. +static const x300_clk_delays X300_REV0_6_CLK_DELAYS = x300_clk_delays( + /*fpga=*/0.000, /*adc=*/1.600, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); + +static const x300_clk_delays X300_REV7_CLK_DELAYS = x300_clk_delays( + /*fpga=*/0.000, /*adc=*/4.400, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); + using namespace uhd; x300_clock_ctrl::~x300_clock_ctrl(void){ @@ -213,6 +238,187 @@ public: _spiface->write_spi(_slaveno, spi_config_t::EDGE_RISE, data,32); } + double set_clock_delay(const x300_clock_which_t which, const double delay_ns, const bool resync = true) { + //All dividers have are delayed by 5 taps by default. The delay + //set by this function is relative to the 5 tap delay + static const boost::uint16_t DDLY_MIN_TAPS = 5; + static const boost::uint16_t DDLY_MAX_TAPS = 522; //Extended mode + + //The resolution and range of the analog delay is fixed + static const double ADLY_RES_NS = 0.025; + static const double ADLY_MIN_NS = 0.500; + static const double ADLY_MAX_NS = 0.975; + + //Each digital tap delays the clock by one VCO period + double vco_period_ns = 1.0e9/_vco_freq; + double half_vco_period_ns = vco_period_ns/2.0; + + //Implement as much of the requested delay using digital taps. Whatever is leftover + //will be made up using the analog delay element and the half-cycle digital tap. + //A caveat here is that the analog delay starts at ADLY_MIN_NS, so we need to back off + //by that much when coming up with the digital taps so that the difference can be made + //up using the analog delay. + boost::uint16_t ddly_taps = 0; + if (delay_ns < ADLY_MIN_NS) { + ddly_taps = static_cast<boost::uint16_t>(std::floor((delay_ns)/vco_period_ns)); + } else { + ddly_taps = static_cast<boost::uint16_t>(std::floor((delay_ns-ADLY_MIN_NS)/vco_period_ns)); + } + double leftover_delay = delay_ns - (vco_period_ns * ddly_taps); + + //Compute settings + boost::uint16_t ddly_value = ddly_taps + DDLY_MIN_TAPS; + bool adly_en = false; + boost::uint8_t adly_value = 0; + boost::uint8_t half_shift_en = 0; + + if (ddly_value > DDLY_MAX_TAPS) { + throw uhd::value_error("set_clock_delay: Requested delay is out of range."); + } + + double coerced_delay = (vco_period_ns * ddly_taps); + if (leftover_delay > ADLY_MAX_NS) { + //The VCO is running too slowly for us to compensate the digital delay difference using + //analog delay. Do the best we can. + adly_en = true; + adly_value = static_cast<boost::uint8_t>(boost::math::round((ADLY_MAX_NS-ADLY_MIN_NS)/ADLY_RES_NS)); + coerced_delay += ADLY_MAX_NS; + } else if (leftover_delay >= ADLY_MIN_NS && leftover_delay <= ADLY_MAX_NS) { + //The leftover delay can be compensated by the analog delay up to the analog delay resolution + adly_en = true; + adly_value = static_cast<boost::uint8_t>(boost::math::round((leftover_delay-ADLY_MIN_NS)/ADLY_RES_NS)); + coerced_delay += ADLY_MIN_NS+(ADLY_RES_NS*adly_value); + } else if (leftover_delay >= (ADLY_MIN_NS - half_vco_period_ns) && leftover_delay < ADLY_MIN_NS) { + //The leftover delay if less than the minimum supported analog delay but if we move the digital + //delay back by half a VCO cycle then it will be in the range of the analog delay. So do that! + adly_en = true; + adly_value = static_cast<boost::uint8_t>(boost::math::round((leftover_delay+half_vco_period_ns-ADLY_MIN_NS)/ADLY_RES_NS)); + half_shift_en = 1; + coerced_delay += ADLY_MIN_NS+(ADLY_RES_NS*adly_value)-half_vco_period_ns; + } else { + //Even after moving the digital delay back by half a cycle, we cannot make up the difference + //so give up on compensating for the difference from the digital delay tap. + //If control reaches here then the value of leftover_delay is possible very small and will still + //be close to what the client requested. + } + + UHD_LOGV(often) + << boost::format("x300_clock_ctrl::set_clock_delay: Which=%d, Requested=%f, Digital Taps=%d, Half Shift=%d, Analog Delay=%d (%s), Coerced Delay=%fns" + ) % which % delay_ns % ddly_value % (half_shift_en?"ON":"OFF") % ((int)adly_value) % (adly_en?"ON":"OFF") % coerced_delay << std::endl; + + //Apply settings + switch (which) + { + case X300_CLOCK_WHICH_FPGA: + _lmk04816_regs.CLKout0_1_DDLY = ddly_value; + _lmk04816_regs.CLKout0_1_HS = half_shift_en; + if (adly_en) { + _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout1_ADLY_SEL = lmk04816_regs_t::CLKOUT1_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout0_1_ADLY = adly_value; + } else { + _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_PD; + _lmk04816_regs.CLKout1_ADLY_SEL = lmk04816_regs_t::CLKOUT1_ADLY_SEL_D_PD; + } + write_regs(0); + write_regs(6); + _delays.fpga_dly_ns = coerced_delay; + break; + case X300_CLOCK_WHICH_DB0_RX: + case X300_CLOCK_WHICH_DB1_RX: + _lmk04816_regs.CLKout2_3_DDLY = ddly_value; + _lmk04816_regs.CLKout2_3_HS = half_shift_en; + if (adly_en) { + _lmk04816_regs.CLKout2_ADLY_SEL = lmk04816_regs_t::CLKOUT2_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout3_ADLY_SEL = lmk04816_regs_t::CLKOUT3_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout2_3_ADLY = adly_value; + } else { + _lmk04816_regs.CLKout2_ADLY_SEL = lmk04816_regs_t::CLKOUT2_ADLY_SEL_D_PD; + _lmk04816_regs.CLKout3_ADLY_SEL = lmk04816_regs_t::CLKOUT3_ADLY_SEL_D_PD; + } + write_regs(1); + write_regs(6); + _delays.db_rx_dly_ns = coerced_delay; + break; + case X300_CLOCK_WHICH_DB0_TX: + case X300_CLOCK_WHICH_DB1_TX: + _lmk04816_regs.CLKout4_5_DDLY = ddly_value; + _lmk04816_regs.CLKout4_5_HS = half_shift_en; + if (adly_en) { + _lmk04816_regs.CLKout4_ADLY_SEL = lmk04816_regs_t::CLKOUT4_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout5_ADLY_SEL = lmk04816_regs_t::CLKOUT5_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout4_5_ADLY = adly_value; + } else { + _lmk04816_regs.CLKout4_ADLY_SEL = lmk04816_regs_t::CLKOUT4_ADLY_SEL_D_PD; + _lmk04816_regs.CLKout5_ADLY_SEL = lmk04816_regs_t::CLKOUT5_ADLY_SEL_D_PD; + } + write_regs(2); + write_regs(7); + _delays.db_tx_dly_ns = coerced_delay; + break; + case X300_CLOCK_WHICH_DAC0: + case X300_CLOCK_WHICH_DAC1: + _lmk04816_regs.CLKout6_7_DDLY = ddly_value; + _lmk04816_regs.CLKout6_7_HS = half_shift_en; + if (adly_en) { + _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout6_7_ADLY = adly_value; + } else { + _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_PD; + _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_PD; + } + write_regs(3); + write_regs(7); + _delays.dac_dly_ns = coerced_delay; + break; + case X300_CLOCK_WHICH_ADC0: + case X300_CLOCK_WHICH_ADC1: + _lmk04816_regs.CLKout8_9_DDLY = ddly_value; + _lmk04816_regs.CLKout8_9_HS = half_shift_en; + if (adly_en) { + _lmk04816_regs.CLKout8_ADLY_SEL = lmk04816_regs_t::CLKOUT8_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout9_ADLY_SEL = lmk04816_regs_t::CLKOUT9_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout8_9_ADLY = adly_value; + } else { + _lmk04816_regs.CLKout8_ADLY_SEL = lmk04816_regs_t::CLKOUT8_ADLY_SEL_D_PD; + _lmk04816_regs.CLKout9_ADLY_SEL = lmk04816_regs_t::CLKOUT9_ADLY_SEL_D_PD; + } + write_regs(4); + write_regs(8); + _delays.adc_dly_ns = coerced_delay; + break; + default: + throw uhd::value_error("set_clock_delay: Requested source is invalid."); + } + + //Delays are applied only on a sync event + if (resync) sync_clocks(); + + return coerced_delay; + } + + double get_clock_delay(const x300_clock_which_t which) { + switch (which) + { + case X300_CLOCK_WHICH_FPGA: + return _delays.fpga_dly_ns; + case X300_CLOCK_WHICH_DB0_RX: + case X300_CLOCK_WHICH_DB1_RX: + return _delays.db_rx_dly_ns; + case X300_CLOCK_WHICH_DB0_TX: + case X300_CLOCK_WHICH_DB1_TX: + return _delays.db_tx_dly_ns; + case X300_CLOCK_WHICH_DAC0: + case X300_CLOCK_WHICH_DAC1: + return _delays.dac_dly_ns; + case X300_CLOCK_WHICH_ADC0: + case X300_CLOCK_WHICH_ADC1: + return _delays.adc_dly_ns; + default: + throw uhd::value_error("get_clock_delay: Requested source is invalid."); + } + } private: @@ -409,7 +615,6 @@ private: _lmk04816_regs.CLKout0_1_PD = lmk04816_regs_t::CLKOUT0_1_PD_POWER_UP; this->write_regs(0); _lmk04816_regs.CLKout0_1_DIV = master_clock_div; - _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_EV_X; this->write_regs(0); // Register 1 @@ -433,9 +638,6 @@ private: _lmk04816_regs.CLKout1_TYPE = lmk04816_regs_t::CLKOUT1_TYPE_P_DOWN; //CPRI feedback clock, use LVDS _lmk04816_regs.CLKout2_TYPE = lmk04816_regs_t::CLKOUT2_TYPE_LVPECL_700MVPP; //DB_0_RX _lmk04816_regs.CLKout3_TYPE = lmk04816_regs_t::CLKOUT3_TYPE_LVPECL_700MVPP; //DB_1_RX - // Analog delay of 900ps to synchronize the radio clock with the source synchronous ADC clocks. - // This delay may need to vary due to temperature. Tested and verified at room temperature only. - _lmk04816_regs.CLKout0_1_ADLY = 0x10; // Register 7 _lmk04816_regs.CLKout4_TYPE = lmk04816_regs_t::CLKOUT4_TYPE_LVPECL_700MVPP; //DB_1_TX @@ -501,6 +703,19 @@ private: // PLL2_P_30 set in individual cases above // PLL2_N_30 set in individual cases above + if (_hw_rev >= 7) { + _delays = X300_REV7_CLK_DELAYS; + } else { + _delays = X300_REV0_6_CLK_DELAYS; + } + + //Apply delay values + set_clock_delay(X300_CLOCK_WHICH_FPGA, _delays.fpga_dly_ns, false); + set_clock_delay(X300_CLOCK_WHICH_DB0_RX, _delays.db_rx_dly_ns, false); //Sets both Ch0 and Ch1 + set_clock_delay(X300_CLOCK_WHICH_DB0_TX, _delays.db_tx_dly_ns, false); //Sets both Ch0 and Ch1 + set_clock_delay(X300_CLOCK_WHICH_ADC0, _delays.adc_dly_ns, false); //Sets both Ch0 and Ch1 + set_clock_delay(X300_CLOCK_WHICH_DAC0, _delays.dac_dly_ns, false); //Sets both Ch0 and Ch1 + /* Write the configuration values into the LMK */ for (size_t i = 1; i <= 16; ++i) { this->write_regs(i); @@ -512,13 +727,14 @@ private: this->sync_clocks(); } - const spi_iface::sptr _spiface; - const size_t _slaveno; - const size_t _hw_rev; - const double _master_clock_rate; - const double _system_ref_rate; - lmk04816_regs_t _lmk04816_regs; - double _vco_freq; + const spi_iface::sptr _spiface; + const size_t _slaveno; + const size_t _hw_rev; + const double _master_clock_rate; + const double _system_ref_rate; + lmk04816_regs_t _lmk04816_regs; + double _vco_freq; + x300_clk_delays _delays; }; x300_clock_ctrl::sptr x300_clock_ctrl::make(uhd::spi_iface::sptr spiface, diff --git a/host/lib/usrp/x300/x300_clock_ctrl.hpp b/host/lib/usrp/x300/x300_clock_ctrl.hpp index 9c08aa356..160a14e6d 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.hpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.hpp @@ -33,7 +33,7 @@ enum x300_clock_which_t X300_CLOCK_WHICH_DB0_TX, X300_CLOCK_WHICH_DB1_RX, X300_CLOCK_WHICH_DB1_TX, - X300_CLOCK_WHICH_TEST, + X300_CLOCK_WHICH_FPGA, }; class x300_clock_ctrl : boost::noncopyable @@ -94,6 +94,22 @@ public: */ virtual void set_ref_out(const bool) = 0; + /*! Set the clock delay for the given clock divider. + * \param which which clock + * \param rate the delay in nanoseconds + * \param resync resync clocks to apply delays + * \return the actual delay value set + * \throw exception when which invalid or delay_ns out of range + */ + virtual double set_clock_delay(const x300_clock_which_t which, const double delay_ns, const bool resync = true) = 0; + + /*! Get the clock delay for the given clock divider. + * \param which which clock + * \return the actual delay value set + * \throw exception when which invalid + */ + virtual double get_clock_delay(const x300_clock_which_t which) = 0; + /*! Reset the clocks. * Should be called if the reference clock changes * to reduce the time required to achieve a lock. diff --git a/host/lib/usrp/x300/x300_dac_ctrl.cpp b/host/lib/usrp/x300/x300_dac_ctrl.cpp index d3bcb8644..bb41146b6 100644 --- a/host/lib/usrp/x300/x300_dac_ctrl.cpp +++ b/host/lib/usrp/x300/x300_dac_ctrl.cpp @@ -129,12 +129,16 @@ public: _check_pll(); // Configure digital interface settings - write_ad9146_reg(0x16, 0x02); // Skew DCI signal by 615ps to find stable data eye - write_ad9146_reg(0x03, 0x00); // 2's comp, I first, byte wide interface - //fpga wants I,Q in the sample word: - //first transaction goes into low bits - //second transaction goes into high bits - //therefore, we want Q to go first (bit 6 == 1) + // Bypass DCI delay. We center the clock edge in the data + // valid window in the FPGA by phase shifting the DCI going + // to the DAC. + write_ad9146_reg(0x16, 0x04); + // 2's comp, I first, byte wide interface + write_ad9146_reg(0x03, 0x00); + // FPGA wants I,Q in the sample word: + // - First transaction goes into low bits + // - Second transaction goes into high bits + // therefore, we want Q to go first (bit 6 == 1) write_ad9146_reg(0x03, (1 << 6)); //2s comp, i first, byte mode // Configure interpolation filters diff --git a/host/lib/usrp/x300/x300_fw_common.h b/host/lib/usrp/x300/x300_fw_common.h index 76531f921..175d37849 100644 --- a/host/lib/usrp/x300/x300_fw_common.h +++ b/host/lib/usrp/x300/x300_fw_common.h @@ -29,10 +29,10 @@ extern "C" { #endif -#define X300_MAX_HW_REV 6 -#define X300_FW_COMPAT_MAJOR 3 +#define X300_MAX_HW_REV 7 +#define X300_FW_COMPAT_MAJOR 4 #define X300_FW_COMPAT_MINOR 0 -#define X300_FPGA_COMPAT_MAJOR 9 +#define X300_FPGA_COMPAT_MAJOR 11 //shared memory sections - in between the stack and the program space #define X300_FW_SHMEM_BASE 0x6000 diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index aff150acb..91e6ded26 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2013-2014 Ettus Research LLC +// Copyright 2013-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -16,7 +16,6 @@ // #include "x300_impl.hpp" -#include "x300_regs.hpp" #include "x300_lvbitx.hpp" #include "x310_lvbitx.hpp" #include <boost/algorithm/string.hpp> @@ -41,7 +40,7 @@ #define NIUSRPRIO_DEFAULT_RPC_PORT "5444" -#define X300_REV(x) (x - "A" + 1) +#define X300_REV(x) ((x) - "A" + 1) using namespace uhd; using namespace uhd::usrp; @@ -508,9 +507,10 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) x300_load_fw(mb.zpu_ctrl, x300_fw_image); } - //check compat -- good place to do after conditional loading - this->check_fw_compat(mb_path, mb.zpu_ctrl); + //check compat numbers + //check fpga compat before fw compat because the fw is a subset of the fpga image this->check_fpga_compat(mb_path, mb.zpu_ctrl); + this->check_fw_compat(mb_path, mb.zpu_ctrl); //store which FPGA image is loaded mb.loaded_fpga_image = get_fpga_option(mb.zpu_ctrl); @@ -696,23 +696,29 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) //////////////////////////////////////////////////////////////////// // setup radios //////////////////////////////////////////////////////////////////// - UHD_MSG(status) << "Initialize Radio control..." << std::endl; - this->setup_radio(mb_i, "A"); - this->setup_radio(mb_i, "B"); + this->setup_radio(mb_i, "A", dev_addr); + this->setup_radio(mb_i, "B", dev_addr); + + //////////////////////////////////////////////////////////////////// + // ADC test and cal + //////////////////////////////////////////////////////////////////// + if (dev_addr.has_key("self_cal_adc_delay")) { + self_cal_adc_xfer_delay(mb, true /* Apply ADC delay */); + } + self_test_adcs(mb); //////////////////////////////////////////////////////////////////// // front panel gpio //////////////////////////////////////////////////////////////////// mb.fp_gpio = gpio_core_200::make(mb.radio_perifs[0].ctrl, TOREG(SR_FP_GPIO), RB32_FP_GPIO); - const std::vector<std::string> GPIO_ATTRS = boost::assign::list_of("CTRL")("DDR")("OUT")("ATR_0X")("ATR_RX")("ATR_TX")("ATR_XX"); - BOOST_FOREACH(const std::string &attr, GPIO_ATTRS) + BOOST_FOREACH(const gpio_attr_map_t::value_type attr, gpio_attr_map) { - _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / attr) + _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / attr.second) .set(0) - .subscribe(boost::bind(&x300_impl::set_fp_gpio, this, mb.fp_gpio, attr, _1)); + .subscribe(boost::bind(&x300_impl::set_fp_gpio, this, mb.fp_gpio, attr.first, _1)); } _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / "READBACK") - .publish(boost::bind(&x300_impl::get_fp_gpio, this, mb.fp_gpio, "READBACK")); + .publish(boost::bind(&x300_impl::get_fp_gpio, this, mb.fp_gpio)); //////////////////////////////////////////////////////////////////// // register the time keepers - only one can be the highlander @@ -829,8 +835,15 @@ x300_impl::~x300_impl(void) { BOOST_FOREACH(mboard_members_t &mb, _mb) { - mb.radio_perifs[0].ctrl->poke32(TOREG(SR_MISC_OUTS), (1 << 2)); //disable/reset ADC/DAC - mb.radio_perifs[1].ctrl->poke32(TOREG(SR_MISC_OUTS), (1 << 2)); //disable/reset ADC/DAC + //disable/reset ADC/DAC + mb.radio_perifs[0].misc_outs->set(radio_misc_outs_reg::ADC_RESET, 1); + mb.radio_perifs[0].misc_outs->set(radio_misc_outs_reg::DAC_RESET_N, 0); + mb.radio_perifs[0].misc_outs->set(radio_misc_outs_reg::DAC_ENABLED, 0); + mb.radio_perifs[0].misc_outs->flush(); + mb.radio_perifs[1].misc_outs->set(radio_misc_outs_reg::ADC_RESET, 1); + mb.radio_perifs[1].misc_outs->set(radio_misc_outs_reg::DAC_RESET_N, 0); + mb.radio_perifs[1].misc_outs->set(radio_misc_outs_reg::DAC_ENABLED, 0); + mb.radio_perifs[1].misc_outs->flush(); //kill the claimer task and unclaim the device mb.claimer_task.reset(); @@ -850,15 +863,7 @@ x300_impl::~x300_impl(void) } } -static void check_adc(wb_iface::sptr iface, const boost::uint32_t val) -{ - boost::uint32_t adc_rb = iface->peek32(RB32_RX); - adc_rb ^= 0xfffc0000; //adapt for I inversion in FPGA - //UHD_MSG(status) << "adc_rb " << std::hex << adc_rb << " val " << std::hex << val << std::endl; - UHD_ASSERT_THROW(adc_rb == val); -} - -void x300_impl::setup_radio(const size_t mb_i, const std::string &slot_name) +void x300_impl::setup_radio(const size_t mb_i, const std::string &slot_name, const uhd::device_addr_t &dev_addr) { const fs_path mb_path = "/mboards/"+boost::lexical_cast<std::string>(mb_i); UHD_ASSERT_THROW(mb_i < _mb.size()); @@ -866,6 +871,8 @@ void x300_impl::setup_radio(const size_t mb_i, const std::string &slot_name) const size_t radio_index = mb.get_radio_index(slot_name); radio_perifs_t &perif = mb.radio_perifs[radio_index]; + UHD_MSG(status) << boost::format("Initialize Radio%d control...") % radio_index << std::endl; + //////////////////////////////////////////////////////////////////// // radio control //////////////////////////////////////////////////////////////////// @@ -873,8 +880,20 @@ void x300_impl::setup_radio(const size_t mb_i, const std::string &slot_name) boost::uint32_t ctrl_sid; both_xports_t xport = this->make_transport(mb_i, dest, X300_RADIO_DEST_PREFIX_CTRL, device_addr_t(), ctrl_sid); perif.ctrl = radio_ctrl_core_3000::make(mb.if_pkt_is_big_endian, xport.recv, xport.send, ctrl_sid, slot_name); - perif.ctrl->poke32(TOREG(SR_MISC_OUTS), (1 << 2)); //reset adc + dac - perif.ctrl->poke32(TOREG(SR_MISC_OUTS), (1 << 1) | (1 << 0)); //out of reset + dac enable + + perif.misc_outs = boost::make_shared<radio_misc_outs_reg>(); + perif.misc_ins = boost::make_shared<radio_misc_ins_reg>(); + perif.misc_outs->initialize(*perif.ctrl, true); + perif.misc_ins->initialize(*perif.ctrl); + + //reset adc + dac + perif.misc_outs->set(radio_misc_outs_reg::ADC_RESET, 1); + perif.misc_outs->set(radio_misc_outs_reg::DAC_RESET_N, 0); + perif.misc_outs->flush(); + perif.misc_outs->set(radio_misc_outs_reg::ADC_RESET, 0); + perif.misc_outs->set(radio_misc_outs_reg::DAC_RESET_N, 1); + perif.misc_outs->set(radio_misc_outs_reg::DAC_ENABLED, 1); + perif.misc_outs->flush(); this->register_loopback_self_test(perif.ctrl); @@ -883,31 +902,16 @@ void x300_impl::setup_radio(const size_t mb_i, const std::string &slot_name) perif.dac = x300_dac_ctrl::make(perif.spi, DB_DAC_SEN, mb.clock->get_master_clock_rate()); perif.leds = gpio_core_200_32wo::make(perif.ctrl, TOREG(SR_LEDS)); + //Capture delays are calibrated every time. The status is only printed is the user + //asks to run the xfer self cal using "self_cal_adc_delay" + self_cal_adc_capture_delay(mb, radio_index, dev_addr.has_key("self_cal_adc_delay")); + _tree->access<time_spec_t>(mb_path / "time" / "cmd") .subscribe(boost::bind(&radio_ctrl_core_3000::set_time, perif.ctrl, _1)); _tree->access<double>(mb_path / "tick_rate") .subscribe(boost::bind(&radio_ctrl_core_3000::set_tick_rate, perif.ctrl, _1)); //////////////////////////////////////////////////////////////// - // ADC self test - //////////////////////////////////////////////////////////////// - perif.adc->set_test_word("ones", "ones"); check_adc(perif.ctrl, 0xfffcfffc); - perif.adc->set_test_word("zeros", "zeros"); check_adc(perif.ctrl, 0x00000000); - perif.adc->set_test_word("ones", "zeros"); check_adc(perif.ctrl, 0xfffc0000); - perif.adc->set_test_word("zeros", "ones"); check_adc(perif.ctrl, 0x0000fffc); - for (size_t k = 0; k < 14; k++) - { - perif.adc->set_test_word("zeros", "custom", 1 << k); - check_adc(perif.ctrl, 1 << (k+2)); - } - for (size_t k = 0; k < 14; k++) - { - perif.adc->set_test_word("custom", "zeros", 1 << k); - check_adc(perif.ctrl, 1 << (k+18)); - } - perif.adc->set_test_word("normal", "normal"); - - //////////////////////////////////////////////////////////////// // create codec control objects //////////////////////////////////////////////////////////////// _tree->create<int>(mb_path / "rx_codecs" / slot_name / "gains"); //phony property so this dir exists @@ -1442,8 +1446,8 @@ bool x300_impl::wait_for_ref_locked(wb_iface::sptr ctrl, double timeout) boost::this_thread::sleep(boost::posix_time::milliseconds(1)); } while (boost::get_system_time() < timeout_time); - //failed to lock on reference - return false; + //Check one last time + return get_ref_locked(ctrl).to_bool(); } sensor_value_t x300_impl::get_ref_locked(wb_iface::sptr ctrl) @@ -1544,20 +1548,24 @@ void x300_impl::set_mb_eeprom(i2c_iface::sptr i2c, const mboard_eeprom_t &mb_eep * front-panel GPIO **********************************************************************/ -boost::uint32_t x300_impl::get_fp_gpio(gpio_core_200::sptr gpio, const std::string &) +boost::uint32_t x300_impl::get_fp_gpio(gpio_core_200::sptr gpio) { return boost::uint32_t(gpio->read_gpio(dboard_iface::UNIT_RX)); } -void x300_impl::set_fp_gpio(gpio_core_200::sptr gpio, const std::string &attr, const boost::uint32_t value) +void x300_impl::set_fp_gpio(gpio_core_200::sptr gpio, const gpio_attr_t attr, const boost::uint32_t value) { - if (attr == "CTRL") return gpio->set_pin_ctrl(dboard_iface::UNIT_RX, value); - if (attr == "DDR") return gpio->set_gpio_ddr(dboard_iface::UNIT_RX, value); - if (attr == "OUT") return gpio->set_gpio_out(dboard_iface::UNIT_RX, value); - if (attr == "ATR_0X") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, value); - if (attr == "ATR_RX") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, value); - if (attr == "ATR_TX") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, value); - if (attr == "ATR_XX") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, value); + switch (attr) + { + case GPIO_CTRL: return gpio->set_pin_ctrl(dboard_iface::UNIT_RX, value); + case GPIO_DDR: return gpio->set_gpio_ddr(dboard_iface::UNIT_RX, value); + case GPIO_OUT: return gpio->set_gpio_out(dboard_iface::UNIT_RX, value); + case GPIO_ATR_0X: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, value); + case GPIO_ATR_RX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, value); + case GPIO_ATR_TX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, value); + case GPIO_ATR_XX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, value); + default: UHD_THROW_INVALID_CODE_PATH(); + } } /*********************************************************************** @@ -1730,14 +1738,20 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res case X300_USRP_PCIE_SSID: mb_type = USRP_X300_MB; break; case X310_USRP_PCIE_SSID: - case X310_2940R_PCIE_SSID: - case X310_2942R_PCIE_SSID: - case X310_2943R_PCIE_SSID: - case X310_2944R_PCIE_SSID: - case X310_2950R_PCIE_SSID: - case X310_2952R_PCIE_SSID: - case X310_2953R_PCIE_SSID: - case X310_2954R_PCIE_SSID: + case X310_2940R_40MHz_PCIE_SSID: + case X310_2940R_120MHz_PCIE_SSID: + case X310_2942R_40MHz_PCIE_SSID: + case X310_2942R_120MHz_PCIE_SSID: + case X310_2943R_40MHz_PCIE_SSID: + case X310_2943R_120MHz_PCIE_SSID: + case X310_2944R_40MHz_PCIE_SSID: + case X310_2950R_40MHz_PCIE_SSID: + case X310_2950R_120MHz_PCIE_SSID: + case X310_2952R_40MHz_PCIE_SSID: + case X310_2952R_120MHz_PCIE_SSID: + case X310_2953R_40MHz_PCIE_SSID: + case X310_2953R_120MHz_PCIE_SSID: + case X310_2954R_40MHz_PCIE_SSID: mb_type = USRP_X310_MB; break; default: mb_type = UNKNOWN; break; @@ -1765,14 +1779,20 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo case X300_USRP_PCIE_SSID: mb_type = USRP_X300_MB; break; case X310_USRP_PCIE_SSID: - case X310_2940R_PCIE_SSID: - case X310_2942R_PCIE_SSID: - case X310_2943R_PCIE_SSID: - case X310_2944R_PCIE_SSID: - case X310_2950R_PCIE_SSID: - case X310_2952R_PCIE_SSID: - case X310_2953R_PCIE_SSID: - case X310_2954R_PCIE_SSID: + case X310_2940R_40MHz_PCIE_SSID: + case X310_2940R_120MHz_PCIE_SSID: + case X310_2942R_40MHz_PCIE_SSID: + case X310_2942R_120MHz_PCIE_SSID: + case X310_2943R_40MHz_PCIE_SSID: + case X310_2943R_120MHz_PCIE_SSID: + case X310_2944R_40MHz_PCIE_SSID: + case X310_2950R_40MHz_PCIE_SSID: + case X310_2950R_120MHz_PCIE_SSID: + case X310_2952R_40MHz_PCIE_SSID: + case X310_2952R_120MHz_PCIE_SSID: + case X310_2953R_40MHz_PCIE_SSID: + case X310_2953R_120MHz_PCIE_SSID: + case X310_2954R_40MHz_PCIE_SSID: mb_type = USRP_X310_MB; break; default: UHD_MSG(warning) << "X300 unknown product code in EEPROM: " << product_num << std::endl; @@ -1782,3 +1802,288 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo return mb_type; } +void x300_impl::self_cal_adc_capture_delay(mboard_members_t& mb, const size_t radio_i, bool print_status) +{ + radio_perifs_t& perif = mb.radio_perifs[radio_i]; + if (print_status) UHD_MSG(status) << "Running ADC capture delay self-cal..." << std::flush; + + static const boost::uint32_t NUM_DELAY_STEPS = 32; //The IDELAYE2 element has 32 steps + static const boost::uint32_t NUM_RETRIES = 2; //Retry self-cal if it fails in warmup situations + static const boost::int32_t MIN_WINDOW_LEN = 4; + + boost::int32_t win_start = -1, win_stop = -1; + boost::uint32_t iter = 0; + while (iter++ < NUM_RETRIES) { + for (boost::uint32_t dly_tap = 0; dly_tap < NUM_DELAY_STEPS; dly_tap++) { + //Apply delay + perif.misc_outs->write(radio_misc_outs_reg::ADC_DATA_DLY_VAL, dly_tap); + perif.misc_outs->write(radio_misc_outs_reg::ADC_DATA_DLY_STB, 1); + perif.misc_outs->write(radio_misc_outs_reg::ADC_DATA_DLY_STB, 0); + + boost::uint32_t err_code = 0; + + // -- Test I Channel -- + //Put ADC in ramp test mode. Tie the other channel to all ones. + perif.adc->set_test_word("ramp", "ones"); + //Turn on the pattern checker in the FPGA. It will lock when it sees a zero + //and count deviations from the expected value + perif.misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 0); + perif.misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 1); + //10ms @ 200MHz = 2 million samples + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + if (perif.misc_ins->read(radio_misc_ins_reg::ADC_CHECKER0_I_LOCKED)) { + err_code += perif.misc_ins->get(radio_misc_ins_reg::ADC_CHECKER0_I_ERROR); + } else { + err_code += 100; //Increment error code by 100 to indicate no lock + } + + // -- Test Q Channel -- + //Put ADC in ramp test mode. Tie the other channel to all ones. + perif.adc->set_test_word("ones", "ramp"); + //Turn on the pattern checker in the FPGA. It will lock when it sees a zero + //and count deviations from the expected value + perif.misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 0); + perif.misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 1); + //10ms @ 200MHz = 2 million samples + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + if (perif.misc_ins->read(radio_misc_ins_reg::ADC_CHECKER0_Q_LOCKED)) { + err_code += perif.misc_ins->get(radio_misc_ins_reg::ADC_CHECKER0_Q_ERROR); + } else { + err_code += 100; //Increment error code by 100 to indicate no lock + } + + if (err_code == 0) { + if (win_start == -1) { //This is the first window + win_start = dly_tap; + win_stop = dly_tap; + } else { //We are extending the window + win_stop = dly_tap; + } + } else { + if (win_start != -1) { //A valid window turned invalid + if (win_stop - win_start >= MIN_WINDOW_LEN) { + break; //Valid window found + } else { + win_start = -1; //Reset window + } + } + } + //UHD_MSG(status) << (boost::format("CapTap=%d, Error=%d\n") % dly_tap % err_code); + } + + //Retry the self-cal if it fails + if ((win_start == -1 || (win_stop - win_start) < MIN_WINDOW_LEN) && iter < NUM_RETRIES /*not last iteration*/) { + win_start = -1; + win_stop = -1; + boost::this_thread::sleep(boost::posix_time::milliseconds(2000)); + } else { + break; + } + } + perif.adc->set_test_word("normal", "normal"); + perif.misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 0); + + if (win_start == -1) { + throw uhd::runtime_error("self_cal_adc_capture_delay: Self calibration failed. Convergence error."); + } + + if (win_stop-win_start < MIN_WINDOW_LEN) { + throw uhd::runtime_error("self_cal_adc_capture_delay: Self calibration failed. Valid window too narrow."); + } + + boost::uint32_t ideal_tap = (win_stop + win_start) / 2; + perif.misc_outs->write(radio_misc_outs_reg::ADC_DATA_DLY_VAL, ideal_tap); + perif.misc_outs->write(radio_misc_outs_reg::ADC_DATA_DLY_STB, 1); + perif.misc_outs->write(radio_misc_outs_reg::ADC_DATA_DLY_STB, 0); + + if (print_status) { + double tap_delay = (1.0e12 / mb.clock->get_master_clock_rate()) / (2*32); //in ps + UHD_MSG(status) << boost::format(" done (Tap=%d, Window=%d, TapDelay=%.3fps, Iter=%d)\n") % ideal_tap % (win_stop-win_start) % tap_delay % iter; + } +} + +double x300_impl::self_cal_adc_xfer_delay(mboard_members_t& mb, bool apply_delay) +{ + UHD_MSG(status) << "Running ADC transfer delay self-cal: " << std::flush; + + //Effective resolution of the self-cal. + static const size_t NUM_DELAY_STEPS = 100; + + double master_clk_period = (1.0e9 / mb.clock->get_master_clock_rate()); //in ns + double delay_start = 0.0; + double delay_range = 2 * master_clk_period; + double delay_incr = delay_range / NUM_DELAY_STEPS; + + UHD_MSG(status) << "Measuring..." << std::flush; + double cached_clk_delay = mb.clock->get_clock_delay(X300_CLOCK_WHICH_ADC0); + double fpga_clk_delay = mb.clock->get_clock_delay(X300_CLOCK_WHICH_FPGA); + + //Iterate through several values of delays and measure ADC data integrity + std::vector< std::pair<double,bool> > results; + for (size_t i = 0; i < NUM_DELAY_STEPS; i++) { + //Delay the ADC clock (will set both Ch0 and Ch1 delays) + double delay = mb.clock->set_clock_delay(X300_CLOCK_WHICH_ADC0, delay_incr*i + delay_start); + wait_for_ref_locked(mb.zpu_ctrl, 0.1); + + boost::uint32_t err_code = 0; + for (size_t r = 0; r < mboard_members_t::NUM_RADIOS; r++) { + //Test each channel (I and Q) individually so as to not accidentally trigger + //on the data from the other channel if there is a swap + + // -- Test I Channel -- + //Put ADC in ramp test mode. Tie the other channel to all ones. + mb.radio_perifs[r].adc->set_test_word("ramp", "ones"); + //Turn on the pattern checker in the FPGA. It will lock when it sees a zero + //and count deviations from the expected value + mb.radio_perifs[r].misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 0); + mb.radio_perifs[r].misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 1); + //50ms @ 200MHz = 10 million samples + boost::this_thread::sleep(boost::posix_time::milliseconds(50)); + if (mb.radio_perifs[r].misc_ins->read(radio_misc_ins_reg::ADC_CHECKER1_I_LOCKED)) { + err_code += mb.radio_perifs[r].misc_ins->get(radio_misc_ins_reg::ADC_CHECKER1_I_ERROR); + } else { + err_code += 100; //Increment error code by 100 to indicate no lock + } + + // -- Test Q Channel -- + //Put ADC in ramp test mode. Tie the other channel to all ones. + mb.radio_perifs[r].adc->set_test_word("ones", "ramp"); + //Turn on the pattern checker in the FPGA. It will lock when it sees a zero + //and count deviations from the expected value + mb.radio_perifs[r].misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 0); + mb.radio_perifs[r].misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 1); + //50ms @ 200MHz = 10 million samples + boost::this_thread::sleep(boost::posix_time::milliseconds(50)); + if (mb.radio_perifs[r].misc_ins->read(radio_misc_ins_reg::ADC_CHECKER1_Q_LOCKED)) { + err_code += mb.radio_perifs[r].misc_ins->get(radio_misc_ins_reg::ADC_CHECKER1_Q_ERROR); + } else { + err_code += 100; //Increment error code by 100 to indicate no lock + } + } + //UHD_MSG(status) << (boost::format("XferDelay=%fns, Error=%d\n") % delay % err_code); + results.push_back(std::pair<double,bool>(delay, err_code==0)); + } + + //Calculate the valid window + int win_start_idx = -1, win_stop_idx = -1, cur_start_idx = -1, cur_stop_idx = -1; + for (size_t i = 0; i < results.size(); i++) { + std::pair<double,bool>& item = results[i]; + if (item.second) { //If data is stable + if (cur_start_idx == -1) { //This is the first window + cur_start_idx = i; + cur_stop_idx = i; + } else { //We are extending the window + cur_stop_idx = i; + } + } else { + if (cur_start_idx == -1) { //We haven't yet seen valid data + //Do nothing + } else if (win_start_idx == -1) { //We passed the first valid window + win_start_idx = cur_start_idx; + win_stop_idx = cur_stop_idx; + } else { //Update cached window if current window is larger + double cur_win_len = results[cur_stop_idx].first - results[cur_start_idx].first; + double cached_win_len = results[win_stop_idx].first - results[win_start_idx].first; + if (cur_win_len > cached_win_len) { + win_start_idx = cur_start_idx; + win_stop_idx = cur_stop_idx; + } + } + //Reset current window + cur_start_idx = -1; + cur_stop_idx = -1; + } + } + if (win_start_idx == -1) { + throw uhd::runtime_error("self_cal_adc_xfer_delay: Self calibration failed. Convergence error."); + } + + double win_center = (results[win_stop_idx].first + results[win_start_idx].first) / 2.0; + double win_length = results[win_stop_idx].first - results[win_start_idx].first; + if (win_length < master_clk_period/4) { + throw uhd::runtime_error("self_cal_adc_xfer_delay: Self calibration failed. Valid window too narrow."); + } + + //Cycle slip the relative delay by a clock cycle to prevent sample misalignment + //fpga_clk_delay > 0 and 0 < win_center < 2*(1/MCR) so one cycle slip is all we need + bool cycle_slip = (win_center-fpga_clk_delay >= master_clk_period); + if (cycle_slip) { + win_center -= master_clk_period; + } + + if (apply_delay) { + UHD_MSG(status) << "Validating..." << std::flush; + //Apply delay + win_center = mb.clock->set_clock_delay(X300_CLOCK_WHICH_ADC0, win_center); //Sets ADC0 and ADC1 + wait_for_ref_locked(mb.zpu_ctrl, 0.1); + //Validate + self_test_adcs(mb, 2000); + } else { + //Restore delay + mb.clock->set_clock_delay(X300_CLOCK_WHICH_ADC0, cached_clk_delay); //Sets ADC0 and ADC1 + } + + //Teardown + for (size_t r = 0; r < mboard_members_t::NUM_RADIOS; r++) { + mb.radio_perifs[r].adc->set_test_word("normal", "normal"); + mb.radio_perifs[r].misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 0); + } + UHD_MSG(status) << (boost::format(" done (FPGA->ADC=%.3fns%s, Window=%.3fns)\n") % + (win_center-fpga_clk_delay) % (cycle_slip?" +cyc":"") % win_length); + + return win_center; +} + +static void check_adc(wb_iface::sptr iface, const boost::uint32_t val, const boost::uint32_t i) +{ + boost::uint32_t adc_rb = iface->peek32(RB32_RX); + adc_rb ^= 0xfffc0000; //adapt for I inversion in FPGA + if (val != adc_rb) { + throw uhd::runtime_error( + (boost::format("ADC self-test failed for Radio%d. (Exp=0x%x, Got=0x%x)")%i%val%adc_rb).str()); + } +} + +void x300_impl::self_test_adcs(mboard_members_t& mb, boost::uint32_t ramp_time_ms) { + for (size_t r = 0; r < mboard_members_t::NUM_RADIOS; r++) { + radio_perifs_t &perif = mb.radio_perifs[r]; + + //First test basic patterns + perif.adc->set_test_word("ones", "ones"); check_adc(perif.ctrl, 0xfffcfffc,r); + perif.adc->set_test_word("zeros", "zeros"); check_adc(perif.ctrl, 0x00000000,r); + perif.adc->set_test_word("ones", "zeros"); check_adc(perif.ctrl, 0xfffc0000,r); + perif.adc->set_test_word("zeros", "ones"); check_adc(perif.ctrl, 0x0000fffc,r); + for (size_t k = 0; k < 14; k++) + { + perif.adc->set_test_word("zeros", "custom", 1 << k); + check_adc(perif.ctrl, 1 << (k+2),r); + } + for (size_t k = 0; k < 14; k++) + { + perif.adc->set_test_word("custom", "zeros", 1 << k); + check_adc(perif.ctrl, 1 << (k+18),r); + } + + //Turn on ramp pattern test + perif.adc->set_test_word("ramp", "ramp"); + perif.misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 0); + perif.misc_outs->write(radio_misc_outs_reg::ADC_CHECKER_ENABLED, 1); + } + boost::this_thread::sleep(boost::posix_time::milliseconds(ramp_time_ms)); + for (size_t r = 0; r < mboard_members_t::NUM_RADIOS; r++) { + radio_perifs_t &perif = mb.radio_perifs[r]; + + if (!perif.misc_ins->read(radio_misc_ins_reg::ADC_CHECKER1_I_LOCKED) || + perif.misc_ins->read(radio_misc_ins_reg::ADC_CHECKER1_I_ERROR) || + !perif.misc_ins->read(radio_misc_ins_reg::ADC_CHECKER1_Q_LOCKED) || + perif.misc_ins->read(radio_misc_ins_reg::ADC_CHECKER1_Q_ERROR)) + { + throw uhd::runtime_error( + (boost::format("ADC self-test failed for Radio%d. (Ramp checker failure)")%r).str()); + } + + //Return to normal mode + perif.adc->set_test_word("normal", "normal"); + } +} + diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index 890ef7bcb..dca6360b8 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -1,5 +1,5 @@ // -// Copyright 2013-2014 Ettus Research LLC +// Copyright 2013-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -49,6 +49,8 @@ #include <uhd/transport/nirio/niusrprio_session.h> #include <uhd/transport/vrt_if_packet.hpp> #include "recv_packet_demuxer_3000.hpp" +#include <uhd/utils/soft_register.hpp> +#include "x300_regs.hpp" static const std::string X300_FW_FILE_NAME = "usrp_x300_fw.bin"; @@ -169,9 +171,43 @@ public: private: boost::shared_ptr<async_md_type> _async_md; + class radio_misc_outs_reg : public uhd::soft_reg32_wo_t { + public: + UHD_DEFINE_SOFT_REG_FIELD(DAC_ENABLED, /*width*/ 1, /*shift*/ 0); //[0] + UHD_DEFINE_SOFT_REG_FIELD(DAC_RESET_N, /*width*/ 1, /*shift*/ 1); //[1] + UHD_DEFINE_SOFT_REG_FIELD(ADC_RESET, /*width*/ 1, /*shift*/ 2); //[2] + UHD_DEFINE_SOFT_REG_FIELD(ADC_DATA_DLY_STB, /*width*/ 1, /*shift*/ 3); //[3] + UHD_DEFINE_SOFT_REG_FIELD(ADC_DATA_DLY_VAL, /*width*/ 5, /*shift*/ 4); //[8:4] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER_ENABLED, /*width*/ 1, /*shift*/ 9); //[9] + + radio_misc_outs_reg(): uhd::soft_reg32_wo_t(TOREG(SR_MISC_OUTS)) { + //Initial values + set(DAC_ENABLED, 0); + set(DAC_RESET_N, 0); + set(ADC_RESET, 0); + set(ADC_DATA_DLY_STB, 0); + set(ADC_DATA_DLY_VAL, 16); + set(ADC_CHECKER_ENABLED, 0); + } + }; + class radio_misc_ins_reg : public uhd::soft_reg32_ro_t { + public: + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER0_Q_LOCKED, /*width*/ 1, /*shift*/ 0); //[0] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER0_I_LOCKED, /*width*/ 1, /*shift*/ 1); //[1] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER1_Q_LOCKED, /*width*/ 1, /*shift*/ 2); //[2] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER1_I_LOCKED, /*width*/ 1, /*shift*/ 3); //[3] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER0_Q_ERROR, /*width*/ 1, /*shift*/ 4); //[4] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER0_I_ERROR, /*width*/ 1, /*shift*/ 5); //[5] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER1_Q_ERROR, /*width*/ 1, /*shift*/ 6); //[6] + UHD_DEFINE_SOFT_REG_FIELD(ADC_CHECKER1_I_ERROR, /*width*/ 1, /*shift*/ 7); //[7] + + radio_misc_ins_reg(): uhd::soft_reg32_ro_t(RB32_MISC_INS) { } + }; + //perifs in the radio core struct radio_perifs_t { + //Interfaces radio_ctrl_core_3000::sptr ctrl; spi_core_3000::sptr spi; x300_adc_ctrl::sptr adc; @@ -184,6 +220,9 @@ private: gpio_core_200_32wo::sptr leds; rx_frontend_core_200::sptr rx_fe; tx_frontend_core_200::sptr tx_fe; + //Registers + radio_misc_outs_reg::sptr misc_outs; + radio_misc_ins_reg::sptr misc_ins; }; //overflow recovery impl @@ -211,7 +250,8 @@ private: i2c_core_100_wb32::sptr zpu_i2c; //perifs in each radio - radio_perifs_t radio_perifs[2]; //!< This is hardcoded s.t. radio_perifs[0] points to slot A and [1] to B + static const size_t NUM_RADIOS = 2; + radio_perifs_t radio_perifs[NUM_RADIOS]; //!< This is hardcoded s.t. radio_perifs[0] points to slot A and [1] to B uhd::usrp::dboard_eeprom_t db_eeproms[8]; //! Return the index of a radio component, given a slot name. This means DSPs, radio_perifs size_t get_radio_index(const std::string &slot_name) { @@ -259,7 +299,7 @@ private: * \param mb_i Motherboard index * \param slot_name Slot name (A or B). */ - void setup_radio(const size_t, const std::string &slot_name); + void setup_radio(const size_t, const std::string &slot_name, const uhd::device_addr_t &dev_addr); size_t _sid_framer; struct sid_config_t @@ -361,8 +401,12 @@ private: void check_fpga_compat(const uhd::fs_path &mb_path, uhd::wb_iface::sptr iface); void update_atr_leds(gpio_core_200_32wo::sptr, const std::string &ant); - boost::uint32_t get_fp_gpio(gpio_core_200::sptr, const std::string &); - void set_fp_gpio(gpio_core_200::sptr, const std::string &, const boost::uint32_t); + boost::uint32_t get_fp_gpio(gpio_core_200::sptr); + void set_fp_gpio(gpio_core_200::sptr, const gpio_attr_t, const boost::uint32_t); + + void self_cal_adc_capture_delay(mboard_members_t& mb, const size_t radio_i, bool print_status = false); + double self_cal_adc_xfer_delay(mboard_members_t& mb, bool apply_delay = false); + void self_test_adcs(mboard_members_t& mb, boost::uint32_t ramp_time_ms = 100); //**PRECONDITION** //This function assumes that all the VITA times in "radios" are synchronized diff --git a/host/lib/usrp/x300/x300_io_impl.cpp b/host/lib/usrp/x300/x300_io_impl.cpp index 334ae8168..e3515af0c 100644 --- a/host/lib/usrp/x300/x300_io_impl.cpp +++ b/host/lib/usrp/x300/x300_io_impl.cpp @@ -23,6 +23,7 @@ #include <uhd/transport/nirio_zero_copy.hpp> #include "async_packet_handler.hpp" #include <uhd/transport/bounded_buffer.hpp> +#include <uhd/transport/chdr.hpp> #include <boost/bind.hpp> #include <uhd/utils/tasks.hpp> #include <uhd/utils/log.hpp> @@ -124,41 +125,6 @@ void x300_impl::update_subdev_spec(const std::string &tx_rx, const size_t mb_i, /*********************************************************************** - * VITA stuff - **********************************************************************/ -static void x300_if_hdr_unpack_be( - const boost::uint32_t *packet_buff, - vrt::if_packet_info_t &if_packet_info -){ - if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR; - return vrt::if_hdr_unpack_be(packet_buff, if_packet_info); -} - -static void x300_if_hdr_pack_be( - boost::uint32_t *packet_buff, - vrt::if_packet_info_t &if_packet_info -){ - if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR; - return vrt::if_hdr_pack_be(packet_buff, if_packet_info); -} - -static void x300_if_hdr_unpack_le( - const boost::uint32_t *packet_buff, - vrt::if_packet_info_t &if_packet_info -){ - if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR; - return vrt::if_hdr_unpack_le(packet_buff, if_packet_info); -} - -static void x300_if_hdr_pack_le( - boost::uint32_t *packet_buff, - vrt::if_packet_info_t &if_packet_info -){ - if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR; - return vrt::if_hdr_pack_le(packet_buff, if_packet_info); -} - -/*********************************************************************** * RX flow control handler **********************************************************************/ static size_t get_rx_flow_control_window(size_t frame_size, size_t sw_buff_size, const device_addr_t& rx_args) @@ -209,9 +175,9 @@ static void handle_rx_flowctrl(const boost::uint32_t sid, zero_copy_if::sptr xpo //load header if (big_endian) - x300_if_hdr_pack_be(pkt, packet_info); + vrt::chdr::if_hdr_pack_be(pkt, packet_info); else - x300_if_hdr_pack_le(pkt, packet_info); + vrt::chdr::if_hdr_pack_le(pkt, packet_info); //load payload pkt[packet_info.num_header_words32+0] = uhd::htonx<boost::uint32_t>(0); @@ -276,12 +242,12 @@ static void handle_tx_async_msgs(boost::shared_ptr<x300_tx_fc_guts_t> guts, zero { if (big_endian) { - x300_if_hdr_unpack_be(packet_buff, if_packet_info); + vrt::chdr::if_hdr_unpack_be(packet_buff, if_packet_info); endian_conv = uhd::ntohx; } else { - x300_if_hdr_unpack_le(packet_buff, if_packet_info); + vrt::chdr::if_hdr_unpack_le(packet_buff, if_packet_info); endian_conv = uhd::wtohx; } } @@ -430,10 +396,10 @@ rx_streamer::sptr x300_impl::get_rx_stream(const uhd::stream_args_t &args_) //init some streamer stuff std::string conv_endianness; if (mb.if_pkt_is_big_endian) { - my_streamer->set_vrt_unpacker(&x300_if_hdr_unpack_be); + my_streamer->set_vrt_unpacker(&vrt::chdr::if_hdr_unpack_be); conv_endianness = "be"; } else { - my_streamer->set_vrt_unpacker(&x300_if_hdr_unpack_le); + my_streamer->set_vrt_unpacker(&vrt::chdr::if_hdr_unpack_le); conv_endianness = "le"; } @@ -594,10 +560,10 @@ tx_streamer::sptr x300_impl::get_tx_stream(const uhd::stream_args_t &args_) std::string conv_endianness; if (mb.if_pkt_is_big_endian) { - my_streamer->set_vrt_packer(&x300_if_hdr_pack_be); + my_streamer->set_vrt_packer(&vrt::chdr::if_hdr_pack_be); conv_endianness = "be"; } else { - my_streamer->set_vrt_packer(&x300_if_hdr_pack_le); + my_streamer->set_vrt_packer(&vrt::chdr::if_hdr_pack_le); conv_endianness = "le"; } diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp index f920b5ae2..e984eb908 100644 --- a/host/lib/usrp/x300/x300_regs.hpp +++ b/host/lib/usrp/x300/x300_regs.hpp @@ -25,40 +25,41 @@ #define localparam static const int -localparam SR_DACSYNC = 5; -localparam SR_LOOPBACK = 6; -localparam SR_TEST = 7; -localparam SR_SPI = 8; -localparam SR_GPIO = 16; -localparam SR_MISC_OUTS = 24; -localparam SR_READBACK = 32; -localparam SR_TX_CTRL = 64; -localparam SR_RX_CTRL = 96; -localparam SR_TIME = 128; -localparam SR_RX_DSP = 144; -localparam SR_TX_DSP = 184; -localparam SR_LEDS = 195; -localparam SR_FP_GPIO = 200; -localparam SR_RX_FRONT = 208; -localparam SR_TX_FRONT = 216; - -localparam RB32_GPIO = 0; -localparam RB32_SPI = 4; -localparam RB64_TIME_NOW = 8; -localparam RB64_TIME_PPS = 16; -localparam RB32_TEST = 24; -localparam RB32_RX = 28; -localparam RB32_FP_GPIO = 32; - -localparam BL_ADDRESS = 0; -localparam BL_DATA = 1; +localparam SR_DACSYNC = 5; +localparam SR_LOOPBACK = 6; +localparam SR_TEST = 7; +localparam SR_SPI = 8; +localparam SR_GPIO = 16; +localparam SR_MISC_OUTS = 24; +localparam SR_READBACK = 32; +localparam SR_TX_CTRL = 64; +localparam SR_RX_CTRL = 96; +localparam SR_TIME = 128; +localparam SR_RX_DSP = 144; +localparam SR_TX_DSP = 184; +localparam SR_LEDS = 195; +localparam SR_FP_GPIO = 200; +localparam SR_RX_FRONT = 208; +localparam SR_TX_FRONT = 216; + +localparam RB32_GPIO = 0; +localparam RB32_SPI = 4; +localparam RB64_TIME_NOW = 8; +localparam RB64_TIME_PPS = 16; +localparam RB32_TEST = 24; +localparam RB32_RX = 28; +localparam RB32_FP_GPIO = 32; +localparam RB32_MISC_INS = 36; + +localparam BL_ADDRESS = 0; +localparam BL_DATA = 1; //wishbone settings map - relevant to host code -#define SET0_BASE 0xa000 -#define SETXB_BASE 0xb000 -#define BOOT_LDR_BASE 0xFA00 -#define I2C0_BASE 0xfe00 -#define I2C1_BASE 0xff00 +#define SET0_BASE 0xa000 +#define SETXB_BASE 0xb000 +#define BOOT_LDR_BASE 0xfa00 +#define I2C0_BASE 0xfe00 +#define I2C1_BASE 0xff00 #define SR_ADDR(base, offset) ((base) + (offset)*4) localparam ZPU_SR_LEDS = 00; @@ -70,56 +71,62 @@ localparam ZPU_SR_ETHINT0 = 40; localparam ZPU_SR_ETHINT1 = 56; //clock controls -#define ZPU_SR_CLOCK_CTRL_CLK_SRC_EXTERNAL 0x00 -#define ZPU_SR_CLOCK_CTRL_CLK_SRC_INTERNAL 0x02 -#define ZPU_SR_CLOCK_CTRL_CLK_SRC_GPSDO 0x03 -#define ZPU_SR_CLOCK_CTRL_PPS_SRC_EXTERNAL 0x00 -#define ZPU_SR_CLOCK_CTRL_PPS_SRC_INTERNAL 0x02 -#define ZPU_SR_CLOCK_CTRL_PPS_SRC_GPSDO 0x03 - -localparam ZPU_RB_SPI = 2; +#define ZPU_SR_CLOCK_CTRL_CLK_SRC_EXTERNAL 0x00 +#define ZPU_SR_CLOCK_CTRL_CLK_SRC_INTERNAL 0x02 +#define ZPU_SR_CLOCK_CTRL_CLK_SRC_GPSDO 0x03 +#define ZPU_SR_CLOCK_CTRL_PPS_SRC_EXTERNAL 0x00 +#define ZPU_SR_CLOCK_CTRL_PPS_SRC_INTERNAL 0x02 +#define ZPU_SR_CLOCK_CTRL_PPS_SRC_GPSDO 0x03 + +localparam ZPU_RB_SPI = 2; localparam ZPU_RB_CLK_STATUS = 3; localparam ZPU_RB_COMPAT_NUM = 6; localparam ZPU_RB_ETH_TYPE0 = 4; localparam ZPU_RB_ETH_TYPE1 = 5; //clock status -#define ZPU_RB_CLK_STATUS_LMK_STATUS (0x3 << 0) -#define ZPU_RB_CLK_STATUS_LMK_LOCK (0x1 << 2) -#define ZPU_RB_CLK_STATUS_LMK_HOLDOVER (0x1 << 3) -#define ZPU_RB_CLK_STATUS_PPS_DETECT (0x1 << 4) +#define ZPU_RB_CLK_STATUS_LMK_STATUS (0x3 << 0) +#define ZPU_RB_CLK_STATUS_LMK_LOCK (0x1 << 2) +#define ZPU_RB_CLK_STATUS_LMK_HOLDOVER (0x1 << 3) +#define ZPU_RB_CLK_STATUS_PPS_DETECT (0x1 << 4) //spi slaves on radio -#define DB_DAC_SEN (1 << 7) -#define DB_ADC_SEN (1 << 6) +#define DB_DAC_SEN (1 << 7) +#define DB_ADC_SEN (1 << 6) #define DB_RX_LSADC_SEN (1 << 5) #define DB_RX_LSDAC_SEN (1 << 4) #define DB_TX_LSADC_SEN (1 << 3) #define DB_TX_LSDAC_SEN (1 << 2) -#define DB_RX_SEN (1 << 1) -#define DB_TX_SEN (1 << 0) +#define DB_RX_SEN (1 << 1) +#define DB_TX_SEN (1 << 0) //------------------------------------------------------------------- // PCIe Registers //------------------------------------------------------------------- -static const uint32_t X300_PCIE_VID = 0x1093; -static const uint32_t X300_PCIE_PID = 0xC4C4; -static const uint32_t X300_USRP_PCIE_SSID = 0x7736; -static const uint32_t X310_USRP_PCIE_SSID = 0x76CA; -static const uint32_t X310_2940R_PCIE_SSID = 0x772B; -static const uint32_t X310_2942R_PCIE_SSID = 0x772C; -static const uint32_t X310_2943R_PCIE_SSID = 0x772D; -static const uint32_t X310_2944R_PCIE_SSID = 0x772E; -static const uint32_t X310_2950R_PCIE_SSID = 0x772F; -static const uint32_t X310_2952R_PCIE_SSID = 0x7730; -static const uint32_t X310_2953R_PCIE_SSID = 0x7731; -static const uint32_t X310_2954R_PCIE_SSID = 0x7732; +static const uint32_t X300_PCIE_VID = 0x1093; +static const uint32_t X300_PCIE_PID = 0xC4C4; +static const uint32_t X300_USRP_PCIE_SSID = 0x7736; +static const uint32_t X310_USRP_PCIE_SSID = 0x76CA; +static const uint32_t X310_2940R_40MHz_PCIE_SSID = 0x772B; +static const uint32_t X310_2940R_120MHz_PCIE_SSID = 0x77FB; +static const uint32_t X310_2942R_40MHz_PCIE_SSID = 0x772C; +static const uint32_t X310_2942R_120MHz_PCIE_SSID = 0x77FC; +static const uint32_t X310_2943R_40MHz_PCIE_SSID = 0x772D; +static const uint32_t X310_2943R_120MHz_PCIE_SSID = 0x77FD; +static const uint32_t X310_2944R_40MHz_PCIE_SSID = 0x772E; +static const uint32_t X310_2950R_40MHz_PCIE_SSID = 0x772F; +static const uint32_t X310_2950R_120MHz_PCIE_SSID = 0x77FE; +static const uint32_t X310_2952R_40MHz_PCIE_SSID = 0x7730; +static const uint32_t X310_2952R_120MHz_PCIE_SSID = 0x77FF; +static const uint32_t X310_2953R_40MHz_PCIE_SSID = 0x7731; +static const uint32_t X310_2953R_120MHz_PCIE_SSID = 0x7800; +static const uint32_t X310_2954R_40MHz_PCIE_SSID = 0x7732; static const uint32_t FPGA_X3xx_SIG_VALUE = 0x58333030; static const uint32_t PCIE_FPGA_ADDR_BASE = 0xC0000; -#define PCIE_FPGA_REG(X) (PCIE_FPGA_ADDR_BASE + X) +#define PCIE_FPGA_REG(X) (PCIE_FPGA_ADDR_BASE + (X)) static const uint32_t FPGA_PCIE_SIG_REG = PCIE_FPGA_REG(0x0000); static const uint32_t FPGA_CNTR_LO_REG = PCIE_FPGA_REG(0x0004); @@ -140,8 +147,8 @@ static const uint32_t DMA_FRAME_SIZE_REG = 0x4; static const uint32_t DMA_SAMPLE_COUNT_REG = 0x8; static const uint32_t DMA_PKT_COUNT_REG = 0xC; -#define PCIE_TX_DMA_REG(REG, CHAN) (PCIE_TX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG) -#define PCIE_RX_DMA_REG(REG, CHAN) (PCIE_RX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG) +#define PCIE_TX_DMA_REG(REG, CHAN) (PCIE_TX_DMA_REG_BASE + ((CHAN)*DMA_REG_GRP_SIZE) + (REG)) +#define PCIE_RX_DMA_REG(REG, CHAN) (PCIE_RX_DMA_REG_BASE + ((CHAN)*DMA_REG_GRP_SIZE) + (REG)) static const uint32_t DMA_CTRL_DISABLED = 0x00000000; static const uint32_t DMA_CTRL_ENABLED = 0x00000002; @@ -154,15 +161,15 @@ static const uint32_t DMA_STATUS_ERROR = 0x00000001; static const uint32_t DMA_STATUS_BUSY = 0x00000002; static const uint32_t PCIE_ROUTER_REG_BASE = PCIE_FPGA_REG(0x0500); -#define PCIE_ROUTER_REG(X) (PCIE_ROUTER_REG_BASE + X) +#define PCIE_ROUTER_REG(X) (PCIE_ROUTER_REG_BASE + (X)) static const uint32_t PCIE_ZPU_DATA_BASE = 0x30000; static const uint32_t PCIE_ZPU_READ_BASE = 0x20000; //Trig and Status share the same base static const uint32_t PCIE_ZPU_STATUS_BASE = 0x20000; -#define PCIE_ZPU_DATA_REG(X) (PCIE_FPGA_REG(PCIE_ZPU_DATA_BASE) + X) -#define PCIE_ZPU_READ_REG(X) (PCIE_FPGA_REG(PCIE_ZPU_READ_BASE) + X) -#define PCIE_ZPU_STATUS_REG(X) (PCIE_FPGA_REG(PCIE_ZPU_STATUS_BASE) + X) +#define PCIE_ZPU_DATA_REG(X) (PCIE_FPGA_REG(PCIE_ZPU_DATA_BASE) + (X)) +#define PCIE_ZPU_READ_REG(X) (PCIE_FPGA_REG(PCIE_ZPU_READ_BASE) + (X)) +#define PCIE_ZPU_STATUS_REG(X) (PCIE_FPGA_REG(PCIE_ZPU_STATUS_BASE) + (X)) static const uint32_t PCIE_ZPU_READ_START = 0x0; static const uint32_t PCIE_ZPU_READ_CLOBBER = 0x80000000; diff --git a/host/lib/usrp_clock/octoclock/common.h b/host/lib/usrp_clock/octoclock/common.h index 96acbb30f..5861bc4b1 100644 --- a/host/lib/usrp_clock/octoclock/common.h +++ b/host/lib/usrp_clock/octoclock/common.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Ettus Research LLC + * Copyright 2014-2015 Ettus Research LLC * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -42,11 +42,11 @@ extern "C" { * only valid C code should go in this section. */ -//These values are placed in the octoclock_packet_t.proto_ver field +// These values are placed in the octoclock_packet_t.proto_ver field #define OCTOCLOCK_BOOTLOADER_PROTO_VER 1234 -#define OCTOCLOCK_FW_COMPAT_NUM 2 +#define OCTOCLOCK_FW_COMPAT_NUM 3 -//UDP ports assigned for different tasks +// UDP ports assigned for different tasks #define OCTOCLOCK_UDP_CTRL_PORT 50000 #define OCTOCLOCK_UDP_GPSDO_PORT 50001 #define OCTOCLOCK_UDP_FW_PORT 50002 @@ -98,11 +98,21 @@ typedef enum { } ref_t; typedef enum { - UP, - DOWN + PREFER_INTERNAL, + PREFER_EXTERNAL } switch_pos_t; +/* + * Some versions of AVR-GCC ignore #pragma pack, so + * if AVR-GCC is being used, use __attribute__ + * instead. + */ +#ifdef AVR +#define __AVR_ALIGNED__ __attribute__((aligned(1))) +#else +#define __AVR_ALIGNED__ #pragma pack(push,1) +#endif // Structure of values in EEPROM, starting in location 0 typedef struct { @@ -113,34 +123,37 @@ typedef struct { uint8_t serial[10]; uint8_t name[10]; uint8_t revision; -} octoclock_fw_eeprom_t; +} octoclock_fw_eeprom_t __AVR_ALIGNED__; typedef struct { uint8_t external_detected; uint8_t gps_detected; uint8_t which_ref; uint8_t switch_pos; -} octoclock_state_t; +} octoclock_state_t __AVR_ALIGNED__; typedef struct { uint8_t num_wraps; uint8_t pos; -} gpsdo_cache_state_t; +} gpsdo_cache_state_t __AVR_ALIGNED__; typedef struct { uint32_t proto_ver; uint32_t sequence; uint8_t code; union { - uint16_t len; + uint16_t crc; gpsdo_cache_state_t state; uint16_t poolsize; uint16_t addr; }; uint8_t data[256]; -} octoclock_packet_t; + uint16_t len; +} octoclock_packet_t __AVR_ALIGNED__; +#ifndef AVR #pragma pack(pop) +#endif #ifdef __cplusplus } diff --git a/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp b/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp index 93c317191..49d1a0442 100644 --- a/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp +++ b/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp @@ -1,5 +1,5 @@ // -// Copyright 2014 Ettus Research LLC +// Copyright 2014-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ #include <uhd/usrp_clock/octoclock_eeprom.hpp> #include <uhd/transport/udp_simple.hpp> #include <uhd/usrp/mboard_eeprom.hpp> +#include <uhd/types/byte_vector.hpp> #include <uhd/types/mac_addr.hpp> #include <uhd/utils/byteswap.hpp> #include <boost/assign/list_of.hpp> @@ -37,26 +38,6 @@ using namespace uhd::usrp_clock; using namespace uhd::transport; /*********************************************************************** - * Utility functions - **********************************************************************/ - -//! A wrapper around std::copy that takes ranges instead of iterators. -template<typename RangeSrc, typename RangeDst> inline -void byte_copy(const RangeSrc &src, RangeDst &dst){ - std::copy(boost::begin(src), boost::end(src), boost::begin(dst)); -} - -//! create a string from a byte vector, return empty if invalid ascii -static const std::string bytes_to_string(const byte_vector_t &bytes){ - std::string out; - BOOST_FOREACH(boost::uint8_t byte, bytes){ - if (byte < 32 or byte > 127) return out; - out += byte; - } - return out; -} - -/*********************************************************************** * Implementation **********************************************************************/ void octoclock_eeprom_t::_load(){ diff --git a/host/lib/usrp_clock/octoclock/octoclock_impl.cpp b/host/lib/usrp_clock/octoclock/octoclock_impl.cpp index b98d95725..ef1bc8ca0 100644 --- a/host/lib/usrp_clock/octoclock/octoclock_impl.cpp +++ b/host/lib/usrp_clock/octoclock/octoclock_impl.cpp @@ -357,14 +357,14 @@ void octoclock_impl::_get_state(const std::string &oc){ } uhd::dict<ref_t, std::string> _ref_strings = boost::assign::map_list_of - (NO_REF, "none") + (NO_REF, "none") (INTERNAL, "internal") (EXTERNAL, "external") ; uhd::dict<switch_pos_t, std::string> _switch_pos_strings = boost::assign::map_list_of - (UP, "Prefer internal") - (DOWN, "Prefer external") + (PREFER_INTERNAL, "Prefer internal") + (PREFER_EXTERNAL, "Prefer external") ; sensor_value_t octoclock_impl::_ext_ref_detected(const std::string &oc){ @@ -410,7 +410,7 @@ boost::uint32_t octoclock_impl::_get_time(const std::string &oc){ } std::string octoclock_impl::_get_images_help_message(const std::string &addr){ - const std::string image_name = "octoclock_r4_fw.bin"; + const std::string image_name = "octoclock_r4_fw.hex"; //Check to see if image is in default location std::string image_location; diff --git a/host/lib/utils/paths.cpp b/host/lib/utils/paths.cpp index f29318ddd..a9c9965c8 100644 --- a/host/lib/utils/paths.cpp +++ b/host/lib/utils/paths.cpp @@ -367,10 +367,10 @@ std::string uhd::find_utility(std::string name) { .string(); } -std::string uhd::print_utility_error(std::string name){ +std::string uhd::print_utility_error(const std::string &name, const std::string &args){ #ifdef UHD_PLATFORM_WIN32 - return "As an Administrator, please run:\n\n\"" + find_utility(name) + "\""; + return "As an Administrator, please run:\n\n\"" + find_utility(name) + args + "\""; #else - return "Please run:\n\n \"" + find_utility(name) + "\""; + return "Please run:\n\n \"" + find_utility(name) + (args.empty() ? "" : (" " + args)) + "\""; #endif } diff --git a/host/lib/utils/platform.cpp b/host/lib/utils/platform.cpp index e2f92039e..a9cef663b 100644 --- a/host/lib/utils/platform.cpp +++ b/host/lib/utils/platform.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2012 Ettus Research LLC +// Copyright 2010-2012,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -19,7 +19,7 @@ #include <uhd/config.hpp> #include <boost/functional/hash.hpp> #ifdef UHD_PLATFORM_WIN32 -#include <Windows.h> +#include <windows.h> #else #include <unistd.h> #endif diff --git a/host/lib/utils/thread_priority.cpp b/host/lib/utils/thread_priority.cpp index 7c3faa37a..af25d088a 100644 --- a/host/lib/utils/thread_priority.cpp +++ b/host/lib/utils/thread_priority.cpp @@ -74,7 +74,7 @@ static void check_priority_range(float priority){ #ifdef HAVE_WIN_SETTHREADPRIORITY #include <windows.h> - void uhd::set_thread_priority(float priority, bool realtime){ + void uhd::set_thread_priority(float priority, UHD_UNUSED(bool realtime)){ check_priority_range(priority); /* diff --git a/host/tests/CMakeLists.txt b/host/tests/CMakeLists.txt index 62544b69b..596ab1017 100644 --- a/host/tests/CMakeLists.txt +++ b/host/tests/CMakeLists.txt @@ -27,16 +27,19 @@ SET(test_sources addr_test.cpp buffer_test.cpp byteswap_test.cpp - convert_test.cpp cast_test.cpp + chdr_test.cpp + convert_test.cpp dict_test.cpp error_test.cpp fp_compare_delta_test.cpp fp_compare_epsilon_test.cpp gain_group_test.cpp + math_test.cpp msg_test.cpp property_test.cpp ranges_test.cpp + sid_t_test.cpp sph_recv_test.cpp sph_send_test.cpp subdev_spec_test.cpp @@ -45,7 +48,11 @@ SET(test_sources ) #turn each test cpp file into an executable with an int main() function -ADD_DEFINITIONS(-DBOOST_TEST_DYN_LINK -DBOOST_TEST_MAIN) +IF(MINGW) + ADD_DEFINITIONS(-DBOOST_TEST_MAIN) +ELSE() + ADD_DEFINITIONS(-DBOOST_TEST_DYN_LINK -DBOOST_TEST_MAIN) +ENDIF() SET(UHD_TEST_TARGET_DEPS uhd) SET(UHD_TEST_LIBRARY_DIRS ${Boost_LIBRARY_DIRS}) @@ -54,7 +61,7 @@ SET(UHD_TEST_LIBRARY_DIRS ${Boost_LIBRARY_DIRS}) FOREACH(test_source ${test_sources}) GET_FILENAME_COMPONENT(test_name ${test_source} NAME_WE) ADD_EXECUTABLE(${test_name} ${test_source}) - TARGET_LINK_LIBRARIES(${test_name} uhd) + TARGET_LINK_LIBRARIES(${test_name} uhd ${Boost_LIBRARIES}) UHD_ADD_TEST(${test_name} ${test_name}) UHD_INSTALL(TARGETS ${test_name} RUNTIME DESTINATION ${PKG_LIB_DIR}/tests COMPONENT tests) ENDFOREACH(test_source) diff --git a/host/tests/addr_test.cpp b/host/tests/addr_test.cpp index cea2f224c..61bb6d049 100644 --- a/host/tests/addr_test.cpp +++ b/host/tests/addr_test.cpp @@ -66,6 +66,13 @@ BOOST_AUTO_TEST_CASE(test_device_addr){ old_dev_addr_vals.begin(), old_dev_addr_vals.end(), new_dev_addr_vals.begin(), new_dev_addr_vals.end() ); + + uhd::device_addr_t dev_addr_lhs1("key1=val1,key2=val2"); + dev_addr_lhs1.update(uhd::device_addr_t("key2=val2x,key3=val3"), false); + BOOST_CHECK_EQUAL(dev_addr_lhs1["key1"], "val1"); + BOOST_CHECK_EQUAL(dev_addr_lhs1["key2"], "val2x"); + BOOST_CHECK_EQUAL(dev_addr_lhs1["key3"], "val3"); + std::cout << "Merged: " << dev_addr_lhs1.to_string() << std::endl; } BOOST_AUTO_TEST_CASE(test_dboard_id){ diff --git a/host/tests/chdr_test.cpp b/host/tests/chdr_test.cpp new file mode 100644 index 000000000..f48073a09 --- /dev/null +++ b/host/tests/chdr_test.cpp @@ -0,0 +1,144 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/transport/chdr.hpp> +#include <uhd/utils/byteswap.hpp> +#include <boost/test/unit_test.hpp> +#include <boost/format.hpp> +#include <cstdlib> +#include <iostream> + +using namespace uhd::transport::vrt; + +static void pack_and_unpack( + if_packet_info_t &if_packet_info_in +){ + // Temp buffer for packed packet + boost::uint32_t packet_buff[2048] = {0}; + + // Check input (must not be lazy) + BOOST_REQUIRE( + (if_packet_info_in.num_payload_words32 == 0 and if_packet_info_in.num_payload_bytes == 0) + or + (if_packet_info_in.num_payload_words32 != 0 and if_packet_info_in.num_payload_bytes != 0) + ); + if (if_packet_info_in.num_payload_words32) { + BOOST_REQUIRE(if_packet_info_in.num_payload_bytes <= 4 * if_packet_info_in.num_payload_words32); + BOOST_REQUIRE(if_packet_info_in.num_payload_bytes > 4*(if_packet_info_in.num_payload_words32-1)); + } + + //pack metadata into a vrt header + chdr::if_hdr_pack_be( + packet_buff, if_packet_info_in + ); + std::cout << std::endl; + boost::uint32_t header_bits = (uhd::ntohx(packet_buff[0]) >> 28); + std::cout << boost::format("header bits = 0b%d%d%d%d") % ((header_bits & 8) > 0) + % ((header_bits & 4) > 0) + % ((header_bits & 2) > 0) + % ((header_bits & 1) > 0) << std::endl; + for (size_t i = 0; i < 5; i++) + { + std::cout << boost::format("packet_buff[%u] = 0x%08x") % i % uhd::ntohx(packet_buff[i]) << std::endl; + } + + if_packet_info_t if_packet_info_out; + // Must be set a-priori as per contract + if_packet_info_out.num_packet_words32 = if_packet_info_in.num_packet_words32; + + //unpack the vrt header back into metadata + chdr::if_hdr_unpack_be( + packet_buff, if_packet_info_out + ); + + //check the the unpacked metadata is the same + BOOST_CHECK_EQUAL(if_packet_info_in.packet_count, if_packet_info_out.packet_count); + BOOST_CHECK_EQUAL(if_packet_info_in.num_header_words32, if_packet_info_out.num_header_words32); + BOOST_CHECK_EQUAL(if_packet_info_in.num_payload_words32, if_packet_info_out.num_payload_words32); + BOOST_CHECK(if_packet_info_out.has_sid); + BOOST_CHECK_EQUAL(if_packet_info_in.sid, if_packet_info_out.sid); + BOOST_CHECK(if_packet_info_out.has_sid); + BOOST_CHECK_EQUAL(if_packet_info_in.has_tsf, if_packet_info_out.has_tsf); + if (if_packet_info_in.has_tsf and if_packet_info_out.has_tsf){ + BOOST_CHECK_EQUAL(if_packet_info_in.tsf, if_packet_info_out.tsf); + } +} + +BOOST_AUTO_TEST_CASE(test_with_chdr){ + if_packet_info_t if_packet_info; + if_packet_info.packet_type = if_packet_info_t::PACKET_TYPE_DATA; + if_packet_info.eob = false; + if_packet_info.packet_count = 7; + if_packet_info.has_tsf = true; + if_packet_info.tsf = 0x1234567890ABCDEFull; + if_packet_info.sid = 0xAABBCCDD; + if_packet_info.num_payload_words32 = 24; + if_packet_info.num_payload_bytes = 95; + pack_and_unpack(if_packet_info); +} + +BOOST_AUTO_TEST_CASE(test_with_chdr_fc){ + if_packet_info_t if_packet_info; + if_packet_info.packet_type = if_packet_info_t::PACKET_TYPE_FC; + if_packet_info.eob = false; + if_packet_info.packet_count = 19; + if_packet_info.has_tsf = false; + if_packet_info.tsf = 0x1234567890ABCDEFull; + if_packet_info.sid = 0xAABBCCDD; + if_packet_info.num_payload_words32 = 4; + if_packet_info.num_payload_bytes = 16; + pack_and_unpack(if_packet_info); +} + +BOOST_AUTO_TEST_CASE(test_with_chdr_cmd){ + if_packet_info_t if_packet_info; + if_packet_info.packet_type = if_packet_info_t::PACKET_TYPE_CMD; + if_packet_info.packet_count = 19; + if_packet_info.has_tsf = true; + if_packet_info.tsf = 0x1234567890ABCDEFull; + if_packet_info.sid = 0xAABBCCDD; + if_packet_info.num_payload_words32 = 4; + if_packet_info.num_payload_bytes = 16; + pack_and_unpack(if_packet_info); +} + +BOOST_AUTO_TEST_CASE(test_with_chdr_resp){ + if_packet_info_t if_packet_info; + if_packet_info.packet_type = if_packet_info_t::PACKET_TYPE_RESP; + if_packet_info.packet_count = 123; + if_packet_info.has_tsf = false; + if_packet_info.tsf = 0x1234567890ABCDEFull; + if_packet_info.sid = 0xAABBCCDD; + if_packet_info.num_payload_words32 = 4; + if_packet_info.num_payload_bytes = 16; + pack_and_unpack(if_packet_info); +} + +BOOST_AUTO_TEST_CASE(test_with_chdr_err){ + if_packet_info_t if_packet_info; + if_packet_info.packet_type = if_packet_info_t::PACKET_TYPE_ERROR; + if_packet_info.packet_count = 1928; + if_packet_info.eob = false; + if_packet_info.error = false; // Needs to be set explicitly + if_packet_info.has_tsf = false; + if_packet_info.tsf = 0x1234567890ABCDEFull; + if_packet_info.sid = 0xAABBCCDD; + if_packet_info.num_payload_words32 = 4; + if_packet_info.num_payload_bytes = 16; + pack_and_unpack(if_packet_info); +} + diff --git a/host/tests/dict_test.cpp b/host/tests/dict_test.cpp index 7b388d090..333aadbba 100644 --- a/host/tests/dict_test.cpp +++ b/host/tests/dict_test.cpp @@ -70,3 +70,28 @@ BOOST_AUTO_TEST_CASE(test_dict_pop){ BOOST_CHECK(d.keys()[0] == -1); BOOST_CHECK(d.keys()[1] == 1); } + +BOOST_AUTO_TEST_CASE(test_dict_update) +{ + uhd::dict<std::string, std::string> d1 = boost::assign::map_list_of + ("key1", "val1") + ("key2", "val2") + ; + uhd::dict<std::string, std::string> d2 = boost::assign::map_list_of + ("key2", "val2x") + ("key3", "val3") + ; + + d1.update(d2, false /* don't throw cause of conflict */); + BOOST_CHECK_EQUAL(d1["key1"], "val1"); + BOOST_CHECK_EQUAL(d1["key2"], "val2x"); + BOOST_CHECK_EQUAL(d1["key3"], "val3"); + + uhd::dict<std::string, std::string> d3 = boost::assign::map_list_of + ("key1", "val1") + ("key2", "val2") + ; + BOOST_CHECK_THROW(d3.update(d2), uhd::value_error); +} + + diff --git a/host/tests/fp_compare_delta_test.cpp b/host/tests/fp_compare_delta_test.cpp index 0ac4e257d..36ff14756 100644 --- a/host/tests/fp_compare_delta_test.cpp +++ b/host/tests/fp_compare_delta_test.cpp @@ -239,12 +239,12 @@ BOOST_AUTO_TEST_CASE(double_greaterthanequals_operators) { BOOST_AUTO_TEST_CASE(frequency_compare_function) { - BOOST_CHECK(uhd::math::frequencies_are_equal(6817333232, 6817333232)); - BOOST_CHECK(!uhd::math::frequencies_are_equal(6817333233, 6817333232)); + BOOST_CHECK(uhd::math::frequencies_are_equal(6817333232.0, 6817333232.0)); + BOOST_CHECK(!uhd::math::frequencies_are_equal(6817333233.0, 6817333232.0)); BOOST_CHECK(uhd::math::frequencies_are_equal(6817333232.1, 6817333232.1)); BOOST_CHECK(!uhd::math::frequencies_are_equal(6817333232.5, 6817333232.6)); BOOST_CHECK(uhd::math::frequencies_are_equal(16.8173332321e9, 16.8173332321e9)); BOOST_CHECK(!uhd::math::frequencies_are_equal(16.8173332322e9, 16.8173332321e9)); BOOST_CHECK(!uhd::math::frequencies_are_equal(5.0, 4.0)); - BOOST_CHECK(uhd::math::frequencies_are_equal(48750000, 48749999.9946)); + BOOST_CHECK(uhd::math::frequencies_are_equal(48750000.0, 48749999.9946)); } diff --git a/host/tests/math_test.cpp b/host/tests/math_test.cpp new file mode 100644 index 000000000..6c890c484 --- /dev/null +++ b/host/tests/math_test.cpp @@ -0,0 +1,29 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <boost/test/unit_test.hpp> +#include <boost/cstdint.hpp> +#include <uhd/utils/math.hpp> + +// NOTE: This is not the only math test case, see e.g. special tests +// for fp comparison. + +BOOST_AUTO_TEST_CASE(test_log2){ + double y = uhd::math::log2(16.0); + BOOST_CHECK_EQUAL(y, 4.0); +} + diff --git a/host/tests/sid_t_test.cpp b/host/tests/sid_t_test.cpp new file mode 100644 index 000000000..31eb4b458 --- /dev/null +++ b/host/tests/sid_t_test.cpp @@ -0,0 +1,158 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <iostream> +#include <sstream> +#include <boost/test/unit_test.hpp> +#include <uhd/types/sid.hpp> +#include <uhd/exception.hpp> + +using uhd::sid_t; + +BOOST_AUTO_TEST_CASE(test_sid_t) { + boost::uint32_t sid_value = 0x01020310; + sid_t sid(sid_value); + + BOOST_CHECK_EQUAL(sid.is_set(), true); + BOOST_CHECK_EQUAL(sid.to_pp_string(), "1.2>3.16"); + BOOST_CHECK_EQUAL(sid.to_pp_string_hex(), "01:02>03:10"); + BOOST_CHECK_EQUAL(sid.get_src(), (boost::uint32_t)0x0102); + BOOST_CHECK_EQUAL(sid.get_dst(), (boost::uint32_t)0x0310); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)0x01); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x02); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x03); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0x10); + BOOST_CHECK_EQUAL(sid == sid, true); + BOOST_CHECK_EQUAL(sid == sid_value, true); + + boost::uint32_t check_sid_val = (boost::uint32_t) sid; + BOOST_CHECK_EQUAL(check_sid_val, sid_value); + + std::stringstream ss_dec; + ss_dec << sid; + BOOST_CHECK_EQUAL(ss_dec.str(), "1.2>3.16"); + + std::stringstream ss_hex; + ss_hex << std::hex << sid; + BOOST_CHECK_EQUAL(ss_hex.str(), "01:02>03:10"); + + sid_t empty_sid; + BOOST_CHECK_EQUAL(empty_sid.is_set(), false); + BOOST_CHECK_EQUAL(empty_sid.to_pp_string(), "x.x>x.x"); + BOOST_CHECK_EQUAL(empty_sid.to_pp_string_hex(), "xx:xx>xx:xx"); + BOOST_CHECK_EQUAL(empty_sid == sid, false); + BOOST_CHECK_EQUAL(empty_sid == sid_value, false); + BOOST_CHECK_EQUAL((bool) empty_sid, false); + + empty_sid = sid_value; // No longer empty + BOOST_CHECK_EQUAL(empty_sid.is_set(), true); + BOOST_CHECK_EQUAL(empty_sid == sid, true); +} + +BOOST_AUTO_TEST_CASE(test_sid_t_set) { + boost::uint32_t sid_value = 0x0; + sid_t sid(sid_value); + + sid.set(0x01020304); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x01020304); + BOOST_CHECK_EQUAL(sid.get_src_addr(),(boost::uint32_t)0x01); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x02); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x03); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0x04); + BOOST_CHECK_EQUAL(sid.get_dst_xbarport(), (boost::uint32_t)0x0); + BOOST_CHECK_EQUAL(sid.get_dst_blockport(), (boost::uint32_t)0x4); + + sid.set_src_addr(0x0a); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x0a020304); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)0x0a); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x02); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x03); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0x04); + + sid.set_src_endpoint(0x0b); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x0a0b0304); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)0x0a); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x0b); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x03); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0x04); + + sid.set_dst_addr(0x0c); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x0a0b0c04); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)0x0a); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x0b); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x0c); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0x04); + + sid.set_dst_endpoint(0x0d); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x0a0b0c0d); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)0x0a); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x0b); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x0c); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0x0d); + + sid.set_dst_xbarport(0xb); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x0a0b0cbd); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)0x0a); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x0b); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x0c); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0xbd); + + sid.set_dst_blockport(0xc); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x0a0b0cbc); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)0x0a); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)0x0b); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)0x0c); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)0xbc); + + sid_t flipped_sid = sid.reversed(); + BOOST_CHECK_EQUAL(flipped_sid.get(), (boost::uint32_t)0x0cbc0a0b); + + // In-place + sid.reverse(); + BOOST_CHECK_EQUAL(sid.get(), (boost::uint32_t)0x0cbc0a0b); +} + +BOOST_AUTO_TEST_CASE(test_sid_t_from_str) { + sid_t sid("1.2>3.4"); + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)1); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)2); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)3); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)4); + + sid = "01:02>03:10"; + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)1); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)2); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)3); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)16); + + sid = "01:06/03:10"; + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)1); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)6); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)3); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)16); + + sid = "01:02:04:10"; + BOOST_CHECK_EQUAL(sid.get_src_addr(), (boost::uint32_t)1); + BOOST_CHECK_EQUAL(sid.get_src_endpoint(), (boost::uint32_t)2); + BOOST_CHECK_EQUAL(sid.get_dst_addr(), (boost::uint32_t)4); + BOOST_CHECK_EQUAL(sid.get_dst_endpoint(), (boost::uint32_t)16); + + BOOST_REQUIRE_THROW(sid_t fail_sid("foobar"), uhd::value_error); + BOOST_REQUIRE_THROW(sid_t fail_sid("01:02:03:4"), uhd::value_error); + BOOST_REQUIRE_THROW(sid_t fail_sid("01:02:03:004"), uhd::value_error); + BOOST_REQUIRE_THROW(sid_t fail_sid("1.2.3.0004"), uhd::value_error); +} diff --git a/host/tests/time_spec_test.cpp b/host/tests/time_spec_test.cpp index c9b9652f9..b98bea7d9 100644 --- a/host/tests/time_spec_test.cpp +++ b/host/tests/time_spec_test.cpp @@ -112,8 +112,8 @@ BOOST_AUTO_TEST_CASE(test_time_large_ticks_to_time_spec) BOOST_AUTO_TEST_CASE(test_time_error_irrational_rate) { - static const double rate = 1625e3/6; - const long long tick_in = 23423436291667; + static const double rate = 1625e3/6.0; + const long long tick_in = 23423436291667ll; const uhd::time_spec_t ts = uhd::time_spec_t::from_ticks(tick_in, rate); const long long tick_out = ts.to_ticks(rate); const long long err = tick_in - tick_out; diff --git a/host/utils/b2xx_fx3_utils.cpp b/host/utils/b2xx_fx3_utils.cpp index 572daef70..bc14932f1 100644 --- a/host/utils/b2xx_fx3_utils.cpp +++ b/host/utils/b2xx_fx3_utils.cpp @@ -51,20 +51,26 @@ struct vid_pid_t { const static vid_pid_t known_vid_pids[] = { {FX3_VID, FX3_DEFAULT_PID}, {FX3_VID, FX3_REENUM_PID}, - {B200_VENDOR_ID, B200_PRODUCT_ID} + {B200_VENDOR_ID, B200_PRODUCT_ID}, + {B200_VENDOR_NI_ID, B200_PRODUCT_NI_ID}, + {B200_VENDOR_NI_ID, B210_PRODUCT_NI_ID} }; const static std::vector<vid_pid_t> known_vid_pid_vector(known_vid_pids, known_vid_pids + (sizeof(known_vid_pids) / sizeof(known_vid_pids[0]))); -const static boost::uint8_t eeprom_init_values[] = { - 0x43, - 0x59, - 0x14, - 0xB2, - (B200_PRODUCT_ID & 0xff), - (B200_PRODUCT_ID >> 8), - (B200_VENDOR_ID & 0xff), - (B200_VENDOR_ID >> 8) - }; -const static uhd::byte_vector_t eeprom_init_value_vector(eeprom_init_values, eeprom_init_values + (sizeof(eeprom_init_values) / sizeof(eeprom_init_values[0]))); + +static const size_t EEPROM_INIT_VALUE_VECTOR_SIZE = 8; +static uhd::byte_vector_t construct_eeprom_init_value_vector(boost::uint16_t vid, boost::uint16_t pid) +{ + uhd::byte_vector_t init_values(EEPROM_INIT_VALUE_VECTOR_SIZE); + init_values.at(0) = 0x43; + init_values.at(1) = 0x59; + init_values.at(2) = 0x14; + init_values.at(3) = 0xB2; + init_values.at(4) = static_cast<boost::uint8_t>(pid & 0xff); + init_values.at(5) = static_cast<boost::uint8_t>(pid >> 8); + init_values.at(6) = static_cast<boost::uint8_t>(vid & 0xff); + init_values.at(7) = static_cast<boost::uint8_t>(vid >> 8); + return init_values; +} //!used with lexical cast to parse a hex string template <class T> struct to_hex{ @@ -153,15 +159,22 @@ uhd::transport::usb_device_handle::sptr open_device(const boost::uint16_t vid, c try { // try caller's VID/PID first - handles = uhd::transport::usb_device_handle::get_device_list(vp.vid,vp.pid); - if (user_supplied && handles.size() == 0) - std::cerr << (boost::format("Failed to open device with VID 0x%04x and PID 0x%04x - trying other known VID/PIDs") % vid % pid).str() << std::endl; - - // try known VID/PIDs next - for (size_t i = 0; handles.size() == 0 && i < known_vid_pid_vector.size(); i++) + std::vector<uhd::transport::usb_device_handle::vid_pid_pair_t> vid_pid_pair_list(1,uhd::transport::usb_device_handle::vid_pid_pair_t(vid,pid)); + handles = uhd::transport::usb_device_handle::get_device_list(vid_pid_pair_list); + if (handles.size() == 0) { - vp = known_vid_pid_vector[i]; - handles = uhd::transport::usb_device_handle::get_device_list(vp.vid,vp.pid); + if (user_supplied) + { + std::cerr << (boost::format("Failed to open device with VID 0x%04x and PID 0x%04x - trying other known VID/PIDs") % vid % pid).str() << std::endl; + } + + // try known VID/PIDs next + for (size_t i = 0; handles.size() == 0 && i < known_vid_pid_vector.size(); i++) + { + vp = known_vid_pid_vector[i]; + handles = uhd::transport::usb_device_handle::get_device_list(vp.vid, vp.pid); + } + } if (handles.size() > 0) @@ -221,7 +234,7 @@ int read_eeprom(b200_iface::sptr& b200, uhd::byte_vector_t& data) int write_eeprom(b200_iface::sptr& b200, const uhd::byte_vector_t& data) { try { - b200->write_eeprom(0x0, 0x0, data); + b200->write_eeprom(0x0, 0x0, data); } catch (std::exception &e) { std::cerr << "Exception while writing EEPROM: " << e.what() << std::endl; return -1; @@ -281,7 +294,7 @@ int erase_eeprom(b200_iface::sptr& b200) boost::int32_t main(boost::int32_t argc, char *argv[]) { boost::uint16_t vid, pid; - std::string pid_str, vid_str, fw_file, fpga_file; + std::string pid_str, vid_str, fw_file, fpga_file, writevid_str, writepid_str; bool user_supplied_vid_pid = false; po::options_description visible("Allowed options"); @@ -295,7 +308,6 @@ boost::int32_t main(boost::int32_t argc, char *argv[]) { ("reset-device,D", "Reset the B2xx Device.") ("reset-fpga,F", "Reset the FPGA (does not require re-programming.") ("reset-usb,U", "Reset the USB subsystem on your host computer.") - ("init-device,I", "Initialize a B2xx device.") ("load-fw,W", po::value<std::string>(&fw_file), "Load a firmware (hex) file into the FX3.") ("load-fpga,L", po::value<std::string>(&fpga_file), @@ -305,9 +317,14 @@ boost::int32_t main(boost::int32_t argc, char *argv[]) { // Hidden options provided for testing - use at your own risk! po::options_description hidden("Hidden options"); hidden.add_options() - ("uninit-device,U", "Uninitialize a B2xx device.") + ("init-device,I", "Initialize a B2xx device.") + ("uninit-device", "Uninitialize a B2xx device.") ("read-eeprom,R", "Read first 8 bytes of EEPROM") - ("erase-eeprom,E", "Erase first 8 bytes of EEPROM"); + ("erase-eeprom,E", "Erase first 8 bytes of EEPROM") + ("write-vid", po::value<std::string>(&writevid_str), + "Write VID field of EEPROM") + ("write-pid", po::value<std::string>(&writepid_str), + "Write PID field of EEPROM"); po::options_description desc; desc.add(visible); @@ -486,9 +503,24 @@ boost::int32_t main(boost::int32_t argc, char *argv[]) { * Cypress VID/PID for the initial FW load, but we can initialize from any state. */ if (vm.count("init-device")) { + uint16_t writevid = B200_VENDOR_ID; + uint16_t writepid = B200_PRODUCT_ID; + /* Now, initialize the device. */ - if (write_and_verify_eeprom(b200, eeprom_init_value_vector)) - return -1; + // Added for testing purposes - not exposed + if (vm.count("write-vid") && vm.count("write-pid")) + { + try { + writevid = atoh(writevid_str); + writepid = atoh(writepid_str); + } catch (std::exception &e) { + std::cerr << "Exception while parsing write VID and PID: " << e.what() << std:: endl; + return ~0; + } + } + + std::cout << "Writing VID and PID to EEPROM..." << std::endl << std::endl; + if (write_and_verify_eeprom(b200, construct_eeprom_init_value_vector(writevid, writepid))) return -1; std::cout << "EEPROM initialized, resetting device..." << std::endl << std::endl; diff --git a/host/utils/b2xx_side_channel.py b/host/utils/b2xx_side_channel.py new file mode 100755 index 000000000..7b1e980eb --- /dev/null +++ b/host/utils/b2xx_side_channel.py @@ -0,0 +1,644 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- +# +# Copyright 2013-2015 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +import sys +import time +import struct + +from optparse import OptionParser + +try: + import usb.core + import usb.util +except Exception as e: + print "Failed to import module 'usb'." + print "Please make sure you have PyUSB installed and in your PYTHONPATH." + print "PyUSB PyPI website: https://pypi.python.org/pypi/pyusb" + print "To install, download from the website or use 'pip install pysusb'" + exit(1) + +import serial + +VRT_OUT = usb.util.CTRL_TYPE_VENDOR | usb.util.CTRL_OUT +VRT_IN = usb.util.CTRL_TYPE_VENDOR | usb.util.CTRL_IN + +VRQS = {} +B200_VREQ_GET_LOG = 0x23 +VRQS[B200_VREQ_GET_LOG] = 'B200_VREQ_GET_LOG' +B200_VREQ_GET_COUNTERS = 0x24 +VRQS[B200_VREQ_GET_COUNTERS] = 'B200_VREQ_GET_COUNTERS' +B200_VREQ_CLEAR_COUNTERS = 0x25 +VRQS[B200_VREQ_CLEAR_COUNTERS] = 'B200_VREQ_CLEAR_COUNTERS' +B200_VREQ_GET_USB_EVENT_LOG = 0x26 +VRQS[B200_VREQ_GET_USB_EVENT_LOG] = 'B200_VREQ_GET_USB_EVENT_LOG' +B200_VREQ_SET_CONFIG = 0x27 +VRQS[B200_VREQ_SET_CONFIG] = 'B200_VREQ_SET_CONFIG' +B200_VREQ_GET_CONFIG = 0x28 +VRQS[B200_VREQ_GET_CONFIG] = 'B200_VREQ_GET_CONFIG' +B200_VREQ_GET_USB_SPEED = 0x80 +VRQS[B200_VREQ_GET_USB_SPEED] ='B200_VREQ_GET_USB_SPEED' +B200_VREQ_WRITE_SB = 0x29 +VRQS[B200_VREQ_WRITE_SB] = 'B200_VREQ_WRITE_SB' +B200_VREQ_SET_SB_BAUD_DIV = 0x30 +VRQS[B200_VREQ_SET_SB_BAUD_DIV] = 'B200_VREQ_SET_SB_BAUD_DIV' +B200_VREQ_FLUSH_DATA_EPS = 0x31 +VRQS[B200_VREQ_FLUSH_DATA_EPS] = 'B200_VREQ_FLUSH_DATA_EPS' +B200_VREQ_AD9361_LOOPBACK = 0x92 +VRQS[B200_VREQ_AD9361_LOOPBACK] = 'B200_VREQ_AD9361_LOOPBACK' + +COUNTER_MAGIC = 0x10024001 +""" +typedef struct Counters { + int magic; + + DMA_COUNTERS dma_to_host; + DMA_COUNTERS dma_from_host; + + int log_overrun_count; + + int usb_error_update_count; + USB_ERROR_COUNTERS usb_error_counters; + + int usb_ep_underrun_count; + + int heap_size; +} COUNTERS, *PCOUNTERS; + +typedef struct USBErrorCounters { + int phy_error_count; + int link_error_count; + + int PHY_LOCK_EV; + int TRAINING_ERROR_EV; + int RX_ERROR_CRC32_EV; + int RX_ERROR_CRC16_EV; + int RX_ERROR_CRC5_EV; + int PHY_ERROR_DISPARITY_EV; + int PHY_ERROR_EB_UND_EV; + int PHY_ERROR_EB_OVR_EV; + int PHY_ERROR_DECODE_EV; +} USB_ERROR_COUNTERS, *PUSB_ERROR_COUNTERS; + +typedef struct DMACounters { + int XFER_CPLT; + int SEND_CPLT; + int RECV_CPLT; + int PROD_EVENT; + int CONS_EVENT; + int ABORTED; + int ERROR; + int PROD_SUSP; + int CONS_SUSP; + + int BUFFER_MARKER; + int BUFFER_EOP; + int BUFFER_ERROR; + int BUFFER_OCCUPIED; + + int last_count; + int last_size; + + int last_sid; + int bad_sid_count; + + int resume_count; +} DMA_COUNTERS, *PDMA_COUNTERS; +""" +DMA_COUNTERS = [ + 'XFER_CPLT', + 'SEND_CPLT', + 'RECV_CPLT', + 'PROD_EVENT', + 'CONS_EVENT', + 'ABORTED', + 'ERROR', + 'PROD_SUSP', + 'CONS_SUSP', + + 'BUFFER_MARKER', + 'BUFFER_EOP', + 'BUFFER_ERROR', + 'BUFFER_OCCUPIED', + + 'last_count', + 'last_size', + + 'last_sid', + 'bad_sid_count' +] + +USB_ERROR_COUNTERS = [ + 'phy_error_count', + 'link_error_count' +] + +USB_PHY_ERROR_REGISTERS = [ + 'PHY_LOCK_EV', + 'TRAINING_ERROR_EV', + 'RX_ERROR_CRC32_EV', + 'RX_ERROR_CRC16_EV', + 'RX_ERROR_CRC5_EV', + 'PHY_ERROR_DISPARITY_EV', + 'PHY_ERROR_EB_UND_EV', + 'PHY_ERROR_EB_OVR_EV', + 'PHY_ERROR_DECODE_EV' +] + +USB_ERROR_COUNTERS += USB_PHY_ERROR_REGISTERS + +COUNTERS = [ + 'magic', + + ('dma_to_host', DMA_COUNTERS), + ('dma_from_host', DMA_COUNTERS), + + 'log_overrun_count', + + 'usb_error_update_count', + ('usb_error_counters', USB_ERROR_COUNTERS), + + 'usb_ep_underrun_count', + + 'heap_size', + + 'resume_count' +] + +USB_EVENTS = {} +USB_EVENTS[0x01] = ('CYU3P_USB_LOG_VBUS_OFF' , 'Indicates VBus turned off.') +USB_EVENTS[0x02] = ('CYU3P_USB_LOG_VBUS_ON' , 'Indicates VBus turned on.') +USB_EVENTS[0x03] = ('CYU3P_USB_LOG_USB2_PHY_OFF' , 'Indicates that the 2.0 PHY has been turned off.') +USB_EVENTS[0x04] = ('CYU3P_USB_LOG_USB3_PHY_OFF' , 'Indicates that the 3.0 PHY has been turned off.') +USB_EVENTS[0x05] = ('CYU3P_USB_LOG_USB2_PHY_ON' , 'Indicates that the 2.0 PHY has been turned on.') +USB_EVENTS[0x06] = ('CYU3P_USB_LOG_USB3_PHY_ON' , 'Indicates that the 3.0 PHY has been turned on.') +USB_EVENTS[0x10] = ('CYU3P_USB_LOG_USBSS_DISCONNECT' , 'Indicates that the USB 3.0 link has been disabled.') +USB_EVENTS[0x11] = ('CYU3P_USB_LOG_USBSS_RESET' , 'Indicates that a USB 3.0 reset (warm/hot) has happened.') +USB_EVENTS[0x12] = ('CYU3P_USB_LOG_USBSS_CONNECT' , 'Indicates that USB 3.0 Rx Termination has been detected.') +USB_EVENTS[0x14] = ('CYU3P_USB_LOG_USBSS_CTRL' , 'Indicates that a USB 3.0 control request has been received.') +USB_EVENTS[0x15] = ('CYU3P_USB_LOG_USBSS_STATUS' , 'Indicates completion of status stage for a 3.0 control request.') +USB_EVENTS[0x16] = ('CYU3P_USB_LOG_USBSS_ACKSETUP' , 'Indicates that the CyU3PUsbAckSetup API has been called.') +USB_EVENTS[0x21] = ('CYU3P_USB_LOG_LGO_U1' , 'Indicates that a LGO_U1 command has been received.') +USB_EVENTS[0x22] = ('CYU3P_USB_LOG_LGO_U2' , 'Indicates that a LGO_U2 command has been received.') +USB_EVENTS[0x23] = ('CYU3P_USB_LOG_LGO_U3' , 'Indicates that a LGO_U3 command has been received.') +USB_EVENTS[0x40] = ('CYU3P_USB_LOG_USB2_SUSP' , 'Indicates that a USB 2.0 suspend condition has been detected.') +USB_EVENTS[0x41] = ('CYU3P_USB_LOG_USB2_RESET' , 'Indicates that a USB 2.0 bus reset has been detected.') +USB_EVENTS[0x42] = ('CYU3P_USB_LOG_USB2_HSGRANT' , 'Indicates that the USB High-Speed handshake has been completed.') +USB_EVENTS[0x44] = ('CYU3P_USB_LOG_USB2_CTRL' , 'Indicates that a FS/HS control request has been received.') +USB_EVENTS[0x45] = ('CYU3P_USB_LOG_USB2_STATUS' , 'Indicates completion of status stage for a FS/HS control transfer.') +USB_EVENTS[0x50] = ('CYU3P_USB_LOG_USB_FALLBACK' , 'Indicates that the USB connection is dropping from 3.0 to 2.0') +USB_EVENTS[0x51] = ('CYU3P_USB_LOG_USBSS_ENABLE' , 'Indicates that a USB 3.0 connection is being attempted again.') +USB_EVENTS[0x52] = ('CYU3P_USB_LOG_USBSS_LNKERR' , 'The number of link errors has crossed the threshold.') +USB_EVENTS[0x80] = ('CYU3P_USB_LOG_LTSSM_CHG' , 'Base of values that indicate a USB 3.0 LTSSM state change.') + +LTSSM_STATES = {} +LTSSM_STATES[0x00] = ['00000', "SS.Disabled"] +LTSSM_STATES[0x01] = ['00001', "Rx.Detect.Reset"] +LTSSM_STATES[0x02] = ['00010', "Rx.Detect.Active"] +LTSSM_STATES[0x03] = ['00011', "Rx.Detect.Quiet"] +LTSSM_STATES[0x04] = ['00100', "SS.Inactive.Quiet"] +LTSSM_STATES[0x05] = ['00101', "SS.Inactive.Disconnect.Detect"] +LTSSM_STATES[0x06] = ['00110', "Hot Reset.Active"] +LTSSM_STATES[0x07] = ['00111', "Hot Reset.Exit"] +LTSSM_STATES[0x08] = ['01000', "Polling.LFPS"] +LTSSM_STATES[0x09] = ['01001', "Polling.RxEQ"] +LTSSM_STATES[0x0a] = ['01010', "Polling.Active"] +LTSSM_STATES[0x0b] = ['01011', "Polling.Configuration"] +LTSSM_STATES[0x0c] = ['01100', "Polling.Idle"] +LTSSM_STATES[0x0d] = ['01101', "(none)"] +#LTSSM_STATES[0x0X] = ['0111X', "(none)"] +LTSSM_STATES[0x0e] = ['0111X', "(none)"] +LTSSM_STATES[0x0f] = ['0111X', "(none)"] +LTSSM_STATES[0x10] = ['10000', "U0"] +LTSSM_STATES[0x11] = ['10001', "U1"] +LTSSM_STATES[0x12] = ['10010', "U2"] +LTSSM_STATES[0x13] = ['10011', "U3"] +LTSSM_STATES[0x14] = ['10100', "Loopback.Active"] +LTSSM_STATES[0x15] = ['10101', "Loopback.Exit"] +LTSSM_STATES[0x16] = ['10110', "(none)"] +LTSSM_STATES[0x17] = ['10111', "Compliance"] +LTSSM_STATES[0x18] = ['11000', "Recovery.Active"] +LTSSM_STATES[0x19] = ['11001', "Recovery.Configuration"] +LTSSM_STATES[0x1a] = ['11010', "Recovery.Idle"] +LTSSM_STATES[0x1b] = ['11011', "(none)"] +#LTSSM_STATES[0x1X] = ['111XX', "(none)"] +LTSSM_STATES[0x1c] = ['111XX', "(none)"] +LTSSM_STATES[0x1d] = ['111XX', "(none)"] +LTSSM_STATES[0x1c] = ['111XX', "(none)"] +LTSSM_STATES[0x1f] = ['111XX', "(none)"] +LTSSM_STATES[0x2c] = ['101100', "Cypress/Intel workaround"] + +def _parse_usb_event_log(data): + l = [] + for d in data: + if d == 0x14 or d == 0x15 or d == 0x16: # CTRL, STATUS, ACKSETUP + continue + elif (d & 0x80): + #l += [(USB_EVENTS[0x80][0] + "+%i" % (d & ~0x80), USB_EVENTS[0x80][1])] + ltssm_key = (d & ~0x80) + ltssm_val = "(unknown)" + if LTSSM_STATES.has_key(ltssm_key): + ltssm_val = LTSSM_STATES[ltssm_key][1] + ltssm_val = "LTSSM: " + ltssm_val + l += [(USB_EVENTS[0x80][0] + "+%i" % (d & ~0x80), ltssm_val)] + elif USB_EVENTS.has_key(d): + l += [USB_EVENTS[d]] + #else: + # l += [("?", "?")] + return l + +class counter_set(): + def __init__(self, counters, name='(top)'): + self._counters = counters + self._counter_names = [] + self._name = name + for c in counters: + o = 0 + default_value = False + if isinstance(c, str): + name = c + default_value = True + elif isinstance(c, tuple): + name = c[0] + o = counter_set(c[1]) + elif isinstance(c, dict): + raise Exception('Not implemented yet') + else: + raise Exception('Unknown counter format') + setattr(self, name, o) + self._counter_names += [(name, default_value)] + self._fmt_str = self._get_struct_format() + + def _get_struct_format(self): + fmt_str = "" + for name, default_value in self._counter_names: + if default_value: + fmt_str += "i" + else: + o = getattr(self, name) + fmt_str += o._get_struct_format() + return fmt_str + + def _update(self, data, parents=[]): + if len(data) == 0: + raise Exception('Ran out of data entering %s' % (self._name)) + #return [] + for name, default_value in self._counter_names: + if default_value: + if len(data) == 0: + raise Exception('Ran out of data setting %s in %s' % (name, self._name)) + setattr(self, name, data[0]) + data = data[1:] + else: + o = getattr(self, name) + data = o._update(data, parents+[self]) + return data + + def update(self, data): + try: + vals = struct.unpack(self._fmt_str, data) + self._update(vals) + except Exception, e: + print e + + def __str__(self): + return self.to_string() + + def to_string(self, parents=[]): + s = "" + cnt = 0 + for name, default_value in self._counter_names: + o = getattr(self, name) + if default_value: + if cnt > 0: + s += "\t" + s += "%s: %05i" % (name, o) + cnt += 1 + else: + if cnt > 0: + s += "\n" + s += "\t"*(len(parents) + 1) + s += o.to_string(parents+[self]) + cnt = 0 + s += "\n" + return s + +class usb_device(): + def __init__(self): + #self.max_buffer_size = 64 # Default to USB2 + self.max_buffer_size = 1024*4 # Apparently it'll frag bigger packets + self.counters = counter_set(COUNTERS) + self.timeout = 2000 + + def open(self, idVendor, idProduct): + print "Finding %04x:%04x..." % (idVendor, idProduct) + self.dev = usb.core.find(idVendor=idVendor, idProduct=idProduct) + if self.dev is None: + raise ValueError('Device not found: %04x:%04x' % (idVendor, idProduct)) + + self.log_index = 0 + self.log_read_count = 0 + self.usb_event_log_read_count = 0 + self.counters_read_count = 0 + + #if self.dev.is_kernel_driver_active(0): + # print "Detaching kernel driver..." + # self.dev.detach_kernel_driver(0) + + #self.dev.set_configuration() # This will throw as device is already claimed + + print "Opened %04x:%04x" % (idVendor, idProduct) + + #self.dev.ctrl_transfer(0x21, 0x09, 0, 0, [0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x00] ) + #self.dev.ctrl_transfer(bmRequestType, bRequest, wValue=0, wIndex=0, data_or_wLength = None, timeout = None + + #res = self.dev.ctrl_transfer(VRT_IN, 0x83, 0, 0, 1024) + # Can give 1024 byte size for IN, result will be actual payload size + # Invalid VREQ results in usb.core.USBError 32 Pipe error + #print res + + #res = self.dev.ctrl_transfer(VRT_IN, B200_VREQ_GET_USB_SPEED, 0, 0, 1) + #self.usb_speed = res[0] + while True: + #l = self.vrt_get(B200_VREQ_GET_USB_SPEED) + l = [] + try: + l = self.dev.ctrl_transfer(VRT_IN, B200_VREQ_GET_USB_SPEED, 0, 0, 1) + except usb.core.USBError, e: + if e.errno == 32: + print e + sys.exit(0) + if len(l) > 0: + self.usb_speed = l[0] + print "Operating at USB", self.usb_speed + break + else: + print "Retrying..." + #if self.usb_speed == 3: + # self.max_buffer_size = 512 + print "Max buffer size:", self.max_buffer_size + print + + def _handle_error(self, e, vrt): + if e.errno == 19: # No such device + raise e + vrt_str = "0x%02x" % (vrt) + if VRQS.has_key(vrt): + vrt_str += " (%s)" % (VRQS[vrt]) + print "%s: %s" % (vrt_str, str(e)) + + def vrt_get(self, vrt): + try: + return self.dev.ctrl_transfer(VRT_IN, vrt, 0, 0, self.max_buffer_size, self.timeout) + except usb.core.USBError, e: + self._handle_error(e, vrt) + return [] + + def vrt_set(self, vrt, data=""): + try: + return self.dev.ctrl_transfer(VRT_OUT, vrt, 0, 0, data, self.timeout) + except usb.core.USBError, e: + self._handle_error(e, vrt) + return None + + def get_log(self, with_log_index=True): + lines = [] + raw = self.vrt_get(B200_VREQ_GET_LOG) + if len(raw) == 0: + return lines + if raw[0] == 0: + return lines + self.log_read_count += 1 + raw = list(raw) + last = 0 + while raw[last] != 0: + try: + idx = raw.index(0, last) + self.log_index += 1 + line = "".join(map(chr, raw[last:idx])) + #print "[%05i %05i] %s" % (self.log_index, self.log_read_count, line) + if with_log_index: + lines += [(self.log_index, line)] + else: + lines += [line] + last = idx + 1 + if last >= len(raw): + break + except Exception, e: + print e + break + return lines + + def print_log(self): + lines = self.get_log() + if len(lines) == 0: + return + for l in lines: + #print l + print "[%05i %05i] %s" % (l[0], self.log_read_count, l[1]) + print + + def get_counters(self): + data = self.vrt_get(B200_VREQ_GET_COUNTERS) + if len(data) == 0: + return + self.counters_read_count += 1 + self.counters.update(data) + + def print_counters(self): + self.get_counters() + print "[%05i]" % (self.counters_read_count) + print self.counters + + def get_usb_event_log(self): + data = self.vrt_get(B200_VREQ_GET_USB_EVENT_LOG) + if len(data) == 0: + return [] + if len(data) == self.max_buffer_size: # ZLP when no new events have been recorded + return [] + if len(data) > 64: + raise Exception("USB event log data len = %i" % (len(data))) + self.usb_event_log_read_count += 1 + return _parse_usb_event_log(data) + + def print_usb_event_log(self): + l = self.get_usb_event_log() + if len(l) == 0: + return + print "\n".join(map(lambda x: ("[%05i] " % (self.usb_event_log_read_count)) + x[0] + ":\t" + x[1], l)) + print + +def run_log(dev, options): + items = [ + (options.log, dev.print_log), + (options.counters, dev.print_counters), + (options.usb_events, dev.print_usb_event_log) + ] + items = filter(lambda x: x[0] > 0, items) + smallest_interval = min(map(lambda x: x[0], items)) + time_now = time.time() + last = [time_now]*len(items) + + try: + for i in items: + if i[0] < 0: + i[1]() + while True: + time_now = time.time() + cleared = False + for i in range(len(items)): + time_last = last[i] + if time_now < (time_last + items[i][0]): + continue + if options.clear_screen and not cleared: + print chr(27) + "[2J" + cleared = True + #print items[i][1] + items[i][1]() + last[i] = time.time() + time.sleep(smallest_interval) + except KeyboardInterrupt: + return + +def hex_to_int(s): + radix = 10 + s = s.lower() + if (len(s) > 1 and s[0] == 'x') or (len(s) > 2 and s[0:2] == "0x"): + radix = 16 + return int(s, radix) + +def recv_serial_data(ser): + data = "" + usb_event_log_read_count = 0 + time_start = time.time() + while True: + c = ser.read() + data += c + #if c == '\n': + if len(data) >= 2 and data[-2:] == "\r\n": + time_now_str = "[%06d]" % (int(time.time() - time_start)) + data = data[0:-2] + if data == "": + #print "[Received an empty line]" + print + elif data[0] == ' ': + print time_now_str, data[1:] + elif data[0] == 'U': + data = data[1:] + cur_type = 0 + i = 0 + usb_events = [] + while len(data) > 0: + c = data[0] + + if cur_type == 0: + if c == 'a': + cur_type = 1 + elif (c >= 'A') and (c <= 'P'): + i = ord(c) - ord('A') + cur_type = 2 + else: + print time_now_str, "[Unknown type: '%s' (0x%02x) in '%s']" % (c, ord(c), data) + + elif cur_type == 1: + i = ord(c) - ord('a') + if (i < 0) or (i >= len(USB_PHY_ERROR_REGISTERS)): + print time_now_str, "[Unknown PHY error register index: '%s' (0x%02x) (%d) in '%s']" % (c, ord(c), i, data) + else: + print time_now_str, USB_PHY_ERROR_REGISTERS[i] + cur_type = 0 + + elif cur_type == 2: + i2 = ord(c) - ord('A') + if (c < 'A') or (c > 'P'): + print time_now_str, "[Unknown second USB event part: '%s' (0x%02x) (%d) in '%s']" % (c, ord(c), i2, data) + else: + i = (i << 4) | i2 + usb_events += [i] + + cur_type = 0 + + data = data[1:] + + if len(usb_events) > 0: + usb_event_log_read_count += 1 + l = _parse_usb_event_log(usb_events) + print "\n".join(map(lambda x: time_now_str + ("[%05i] " % (usb_event_log_read_count)) + x[0] + ":\t" + x[1], l)) + data = "" + +def main(): + parser = OptionParser(usage="%prog: [options]") #option_class=eng_option, + parser.add_option("-v", "--vid", type="string", default="0x2500", help="VID [default=%default]") + parser.add_option("-p", "--pid", type="string", default="0x0020", help="PID [default=%default]") + parser.add_option("-t", "--tty", type="string", default=None, help="TTY [default=%default]") + parser.add_option("-c", "--cmd", type="string", default="", help="Command (empty opens prompt)") + parser.add_option("-n", "--counters", type="float", default="5.0", help="Counter print interval [default=%default]") + parser.add_option("-l", "--log", type="float", default="0.25", help="Log print interval [default=%default]") + parser.add_option("-e", "--usb-events", type="float", default="0.25", help="USB event log print interval [default=%default]") + parser.add_option("-s", "--sb", type="string", default=None, help="Settings Bus write message [default=%default]") + parser.add_option("-d", "--sb-baud-div", type="int", default=None, help="Settings Bus baud rate divisor [default=%default]") + parser.add_option("-b", "--sb-baud", type="int", default=None, help="Settings Bus baud rate [default=%default]") + parser.add_option("-r", "--clear-screen", action="store_true", default=False, help="Clear screen [default=%default]") + parser.add_option("-R", "--reset-counters", action="store_true", default=False, help="Reset counters [default=%default]") + parser.add_option("-f", "--flush-data-eps", action="store_true", default=False, help="Flush data endpoints [default=%default]") + parser.add_option("-L", "--fe-loopback", type="int", default=None, help="Change AD9361 digital loopback [default=%default]") + (options, args) = parser.parse_args() + + if options.tty is not None and options.tty != "": + while True: + try: + ser = serial.Serial(port=options.tty, baudrate=115200, parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE, bytesize=serial.EIGHTBITS, timeout=None) # timeout: None (blocking), 0 (non-blocking) + print "Opened", options.tty + try: + recv_serial_data(ser) + except KeyboardInterrupt: + break + except Exception as e: + print e + break + else: + dev = usb_device() + while True: + try: + dev.open(idVendor=hex_to_int(options.vid), idProduct=hex_to_int(options.pid)) + + if options.flush_data_eps: + dev.vrt_set(B200_VREQ_FLUSH_DATA_EPS) + if options.sb_baud_div is not None: + dev.vrt_set(B200_VREQ_SET_SB_BAUD_DIV, struct.pack('H', options.sb_baud_div)) + if options.sb is not None and len(options.sb) > 0: + dev.vrt_set(B200_VREQ_WRITE_SB, " " + options.sb) + if options.reset_counters: + dev.vrt_set(B200_VREQ_CLEAR_COUNTERS) + if options.fe_loopback is not None: + dev.vrt_set(B200_VREQ_AD9361_LOOPBACK, struct.pack('B', int(options.fe_loopback))) + if len(options.cmd) == 0: + run_log(dev, options) + pass + else: + pass + break + except usb.core.USBError as e: + if e.errno == 19: # No such device + pass + print e + break + return 0 + +if __name__ == '__main__': + main() diff --git a/host/utils/octoclock_firmware_burner.cpp b/host/utils/octoclock_firmware_burner.cpp index d624095e6..eb8198a2b 100644 --- a/host/utils/octoclock_firmware_burner.cpp +++ b/host/utils/octoclock_firmware_burner.cpp @@ -1,5 +1,5 @@ // -// Copyright 2014 Ettus Research LLC +// Copyright 2014-2015 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -74,8 +74,23 @@ boost::uint8_t firmware_image[MAX_FIRMWARE_SIZE]; size_t firmware_size = 0; boost::uint8_t octoclock_data[udp_simple::mtu]; octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t *>(octoclock_data); -std::string firmware_path; +std::string firmware_path, actual_firmware_path; size_t num_blocks = 0; +bool hex = true; + +static uint16_t calculate_crc(boost::uint8_t* buffer, boost::uint16_t len){ + boost::uint16_t crc = 0xFFFF; + + for(size_t i = 0; i < len; i++){ + crc ^= buffer[i]; + for(boost::uint8_t j = 0; j < 8; ++j){ + if(crc & 1) crc = (crc >> 1) ^ 0xA001; + else crc = (crc >> 1); + } + } + + return crc; +} /* * Functions @@ -121,26 +136,25 @@ device_addrs_t bootloader_find(const std::string &ip_addr){ } void read_firmware(){ - std::ifstream firmware_file(firmware_path.c_str(), std::ios::binary); - firmware_file.seekg(0, std::ios::end); - firmware_size = size_t(firmware_file.tellg()); + std::ifstream firmware_file(actual_firmware_path.c_str(), std::ios::binary); + firmware_size = size_t(fs::file_size(actual_firmware_path)); if(firmware_size > MAX_FIRMWARE_SIZE){ firmware_file.close(); throw uhd::runtime_error(str(boost::format("Firmware file too large: %d > %d") % firmware_size % (MAX_FIRMWARE_SIZE))); } - firmware_file.seekg(0, std::ios::beg); firmware_file.read((char*)firmware_image, firmware_size); firmware_file.close(); - num_blocks = (firmware_size % BLOCK_SIZE) ? (firmware_size / BLOCK_SIZE) - : ((firmware_size / BLOCK_SIZE) + 1); + num_blocks = (firmware_size % BLOCK_SIZE) ? ((firmware_size / BLOCK_SIZE) + 1) + : (firmware_size / BLOCK_SIZE); } void burn_firmware(udp_simple::sptr udp_transport){ octoclock_packet_t pkt_out; pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); - pkt_out.len = uhd::htonx<boost::uint16_t>((boost::uint16_t)firmware_size); + pkt_out.len = (boost::uint16_t)firmware_size; + pkt_out.crc = calculate_crc(firmware_image, firmware_size); size_t len = 0, current_pos = 0; //Tell OctoClock not to jump to application, wait for us instead @@ -149,6 +163,7 @@ void burn_firmware(udp_simple::sptr udp_transport){ if(UHD_OCTOCLOCK_PACKET_MATCHES(FW_BURN_READY_ACK, pkt_out, pkt_in, len)) std::cout << "ready." << std::endl; else{ std::cout << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Could not get OctoClock in valid state for firmware download."); } @@ -165,7 +180,7 @@ void burn_firmware(udp_simple::sptr udp_transport){ << "% (" << (i+1) << "/" << num_blocks << " blocks)" << std::flush; memset(pkt_out.data, 0, BLOCK_SIZE); - memcpy((void*)(pkt_out.data), &firmware_image[i*BLOCK_SIZE], std::min(int(firmware_size-current_pos), BLOCK_SIZE)); + memcpy((void*)(pkt_out.data), &firmware_image[i*BLOCK_SIZE], BLOCK_SIZE); bool success = false; while(num_tries <= 5){ @@ -181,6 +196,7 @@ void burn_firmware(udp_simple::sptr udp_transport){ } if(not success){ std::cout << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Failed to burn firmware to OctoClock!"); } @@ -196,7 +212,6 @@ void verify_firmware(udp_simple::sptr udp_transport){ pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); size_t len = 0, current_pos = 0; - for(size_t i = 0; i < num_blocks; i++){ pkt_out.sequence++; pkt_out.addr = i*BLOCK_SIZE; @@ -208,11 +223,13 @@ void verify_firmware(udp_simple::sptr udp_transport){ if(memcmp((void*)(pkt_in->data), &firmware_image[i*BLOCK_SIZE], std::min(int(firmware_size-current_pos), BLOCK_SIZE))){ std::cout << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Failed to verify OctoClock firmware!"); } } else{ std::cout << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Failed to verify OctoClock firmware!"); } } @@ -230,6 +247,7 @@ bool reset_octoclock(const std::string &ip_addr){ UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, RESET_CMD, pkt_out, len, octoclock_data); if(not UHD_OCTOCLOCK_PACKET_MATCHES(RESET_ACK, pkt_out, pkt_in, len)){ std::cout << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Failed to place device in state to receive firmware."); } @@ -246,11 +264,13 @@ void finalize(udp_simple::sptr udp_transport){ UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, FINALIZE_BURNING_CMD, pkt_out, len, octoclock_data); if(not UHD_OCTOCLOCK_PACKET_MATCHES(FINALIZE_BURNING_ACK, pkt_out, pkt_in, len)){ std::cout << std::endl; + if(hex) fs::remove(actual_firmware_path); std::cout << "no ACK. Bootloader may not have loaded application." << std::endl; } } -int UHD_SAFE_MAIN(int argc, char *argv[]){ +int UHD_SAFE_MAIN(UHD_UNUSED(int argc), UHD_UNUSED(char *argv[])){ + std::string ip_addr; po::options_description desc("Allowed options"); desc.add_options() @@ -300,7 +320,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ throw uhd::runtime_error(str(boost::format("This filepath does not exist: %s") % firmware_path)); } } - else firmware_path = find_image_path("octoclock_r4_fw.bin"); + else firmware_path = find_image_path("octoclock_r4_fw.hex"); //If Intel hex file detected, convert to binary std::string ext = fs::extension(firmware_path); @@ -312,9 +332,11 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ % time_spec_t::get_system_time().get_full_secs())); Hex2Bin(firmware_path.c_str(), temp_bin.string().c_str(), false); - firmware_path = temp_bin.string(); + actual_firmware_path = temp_bin.string(); } else if(ext == ".bin"){ + hex = false; + actual_firmware_path = firmware_path; std::cout << "Found firmware at path: " << firmware_path << std::endl; } else throw uhd::runtime_error("The firmware file has in improper extension (must be .hex or .bin)."); @@ -327,6 +349,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ if(reset_octoclock(ip_addr)) std::cout << "successful." << std::endl; else{ std::cout << "failed." << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Failed to reset OctoClock device into its bootloader."); } } @@ -334,6 +357,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ } else{ std::cout << "failed." << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Could not find OctoClock with given IP address!"); } @@ -354,7 +378,8 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ if(octoclocks.size() == 1){ if(octoclocks[0]["type"] == "octoclock-bootloader"){ std::cout << std::endl; - throw uhd::runtime_error("OctoClock failed to leave bootloader state."); + if(hex) fs::remove(actual_firmware_path); + throw uhd::runtime_error("Firmware did not load properly."); } else{ std::cout << "found." << std::endl << std::endl @@ -363,8 +388,10 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ } else{ std::cout << std::endl; + if(hex) fs::remove(actual_firmware_path); throw uhd::runtime_error("Failed to reinitialize OctoClock."); } + if(hex) fs::remove(actual_firmware_path); return EXIT_SUCCESS; } diff --git a/tools/uhd_txrx_debug_prints/uhd_txrx_debug_prints_README.md b/tools/uhd_txrx_debug_prints/uhd_txrx_debug_prints_README.md new file mode 100644 index 000000000..1425a4d96 --- /dev/null +++ b/tools/uhd_txrx_debug_prints/uhd_txrx_debug_prints_README.md @@ -0,0 +1,17 @@ +UHD TX/RX DEBUG PRINTS +====================== + +A tool for extensive debugging with UHD. + +Install +------- +Activate it by ticking `UHD_TXRX_DEBUG_PRINTS` in cmake-gui for your UHD installation. Then recompile and reinstall UHD. + +Use +--- +Run your application and pipe stderr to a file. +this is mostly done by <br> +`app_call 2> dbg_print_file.txt`<br> +After finishing the application offline processing of the gathered data is done with a python script called<br> +`uhd_txrx_debug_prints_graph.py`<br> +There are a lot of functions that help to preprocess your data and that describe the actual meaning of all the data points. in the end though, it comes down to the users needs what he wants to plot and see.
\ No newline at end of file diff --git a/tools/uhd_txrx_debug_prints/uhd_txrx_debug_prints_graph.py b/tools/uhd_txrx_debug_prints/uhd_txrx_debug_prints_graph.py new file mode 100755 index 000000000..b0f6681f6 --- /dev/null +++ b/tools/uhd_txrx_debug_prints/uhd_txrx_debug_prints_graph.py @@ -0,0 +1,415 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- +# +# Copyright 2013-2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +""" +Plots the output of the streamers that is produced when DEBUG_TXRX +is enabled. +""" + +import argparse +import matplotlib.pyplot as plt +import numpy as np + +# This is a top level function to load a debug file. It will return a list of lists with all the data. +def get_data(filename): + res = [] + with open(filename) as f: + for line in f.readlines(): + line = line.rstrip('\n') + s = line.split(',') + res.append(s) + res = fix_known_data_corruption_patterns(res) + return res + +# Sometimes 'O' etc. get printed to stderr. This disturbs further processing. Thus, known pattern will be removed here. +def fix_known_data_corruption_patterns(data): + # Some lines might be corrupted in the way that e.g. UHD prints sth else in the same line. + # O, D, Press Enter... are known patterns. These should be fixed. + counts = {'O': 0, 'D': 0, 'exit_msg': 0} + for i in range(len(data)): + if data[i][0].startswith('O'): + counts['O'] += 1 + data[i][0] = data[i][0].replace('O', '') + if data[i][0].startswith('D'): + counts['D'] += 1 + data[i][0] = data[i][0].replace('D', '') + if data[i][0].startswith('Press Enter to quit: '): + counts['exit_msg'] += 1 + data[i][0] = data[i][0].replace('Press Enter to quit: ', '') + print counts + return data + +# Extract lines with a certain prefix. +def extract_lines(prefix, data): + res = [] + for line in data: + if line[0] == prefix: + res.append(line[1:]) + return res + +# boolean values are stored as true/false. Convert them to real booleans again. +def convert_to_bool(data): + res = [] + for d in data: + res.append(d == "true") + return res + +# The different outputs have different structures. With this function you can conert them back to their actual type. +def convert_data_set(data, reqtype): + zdata = zip(*data) + res = [] + if len(zdata) == 0: + return res + for i in range(len(reqtype)): + if reqtype[i] == np.bool: + res.append(np.asarray(convert_to_bool(zdata[i]), dtype=np.bool)) + else: + res.append(np.asarray(zdata[i], dtype=reqtype[i])) + return res + +# Wrapper for super_send_packet_handler data to be used with convert_data_set +def convert_super_send_packet_handler_data(data): + # wallclock, timeout, avail_samps, sent_samps, sob, eob, has_time_spec, time_spec (ticks) + reqtype = [np.uint64, np.float, np.int, np.int, np.bool, np.bool, np.bool, np.uint64] + cdata = convert_data_set(data, reqtype) + return cdata + +# same o' same o' +def convert_super_recv_packet_handler_data(data): + # wallclock, timeout, requested_samps, received_samps, one_packet, error_code, sob, eob, more_fragments, fragment_offset, has_timespec, time_spec + reqtype = [np.uint64, np.float, np.int, np.int, np.bool, np.int, np.bool, np.bool, np.bool, np.int, np.bool, np.uint64] + cdata = convert_data_set(data, reqtype) + return cdata + +def extract_super_recv_packet_handler_data(data): + pref1 = "super_recv_packet_handler" + pref2 = "recv" + super_recv = extract_lines(pref1, data) + recv = extract_lines(pref2, super_recv) + recv = convert_super_recv_packet_handler_data(recv) + return recv + +# Sometimes TX or RX is interrupted by system jiffies. Those are found by this function. +def find_jiffy(data, thr): + res = [] + last = data[0] + for i in range(len(data)): + if data[i] - last > thr: + res.append([last, data[i]]) + last = data[i] + return res + + +# Get difference between tx and rx wallclock +def get_diff(tx, rx): + print "get diff, len(rx) = ", len(rx) + diff = [0] * len(rx[0]) + for i in range(len(diff)): + r = rx[3][i] + idx = rx[0][i] - 1 # call count starts at 1. idx is 0 based. + t = tx[3][idx] + diff[i] = t - r + return diff + + +def bps(samps, time): + bp = [] + last = time[0]-1000 + for i in range(len(samps)): + td = time[i] - last + last = time[i] + td = td /1e6 + bp.append(samps[i] * 4 / td) + return bp + + +# same as the other wrappers this time for libusb1 +def extract_libusb(trx, data): + pr1 = "libusb1_zero_copy" + pr2 = "libusb_async_cb" + ldata = extract_lines(pr1, data) + edata = extract_lines(pr2, ldata) + d = extract_lines(trx, edata) + # buff_num, actual_length, status, end_time, start_time + reqtype = [np.int, np.int, np.int, np.uint64, np.uint64] + return convert_data_set(d, reqtype) + + +# Extract data for stream buffers. Typically there are 16 TX and 16 RX buffers. And there numbers are static. Though the number of buffers might be changed and the constant parameters must be adjusted in this case. +def extract_txrx(data): + tx = [[], [], [], [], []] + rx = [[], [], [], [], []] + for i in range(len(data[0])): + print data[0][i] + if data[0][i] > 31 and data[0][i] < 48: + rx[0].append(data[0][i]) + rx[1].append(data[1][i]) + rx[2].append(data[2][i]) + rx[3].append(data[3][i]) + rx[4].append(data[4][i]) + #print "tx\t", data[0][i], "\t", data[3][i], "\t", data[4][i] + if data[0][i] > 47 and data[0][i] < 64: + tx[0].append(data[0][i]) + tx[1].append(data[1][i]) + tx[2].append(data[2][i]) + tx[3].append(data[3][i]) + tx[4].append(data[4][i]) + #print "rx\t", data[0][i], "\t", data[3][i], "\t", data[4][i] + return [tx, rx] + +# Calculate momentary throughput +def throughput(data): + start = data[2][0] + total = data[1][-1] - data[2][0] + print total + thr = np.zeros(total) + + for i in range(len(data[0])): + s = data[2][i] - start + f = data[1][i] - start + ticks = data[1][i] - data[2][i] + pertick = 1. * data[0][i] / ticks + vals = [pertick] * ticks + thr[s:f] = np.add(thr[s:f], vals) + #print pertick + print np.shape(thr) + return thr + + +# Calculate a moving average +def ma(data, wl): + ap = np.zeros(wl) + data = np.concatenate((ap, data, ap)) + print np.shape(data) + res = np.zeros(len(data)-wl) + for i in range(len(data)-wl): + av = np.sum(data[i:i+wl]) / wl + res[i] = av + print i, "\t", av + return res + + +def get_x_axis(stamps): + scale = 10e-6 + return np.multiply(stamps, scale) + + +# plot status codes. +def plot_status_codes_over_time(data, fignum): + print "printing status numbers over time" + + # extract and convert the data + recv = extract_super_recv_packet_handler_data(data) + libusb_rx = extract_libusb("rx", data) + libusb_tx = extract_libusb("tx", data) + + # Plot all data + plt.figure(fignum) # Make sure these plots are printed to a new figure. + #plt.plot(get_x_axis(libusb_rx[3]), libusb_rx[2], marker='x', label='RX') + #plt.plot(get_x_axis(libusb_tx[3]), libusb_tx[2], marker='x', label='TX') + + pos = 5 + recv_error_codes = recv[pos] + plt.plot(get_x_axis(recv[0]), recv_error_codes, marker='x', label='recv') + plt.title("Status codes over timestamps") + plt.ylabel("status codes") + plt.xlabel("timestamps") + plt.grid() + plt.legend() + + for i in range(len(recv[0])): + if recv[pos][i] == 8: + xaxis = get_x_axis([recv[0][i]]) + plt.axvline(xaxis, color='b') + + + # Get some statistics and print them too + codes = [] + code_dict = {} + for i in range(len(recv_error_codes)): + if recv_error_codes[i] != 0: + code = rx_metadata_error_codes[recv_error_codes[i]] + pair = [i, code] + codes.append(pair) + if not code_dict.has_key(code): + code_dict[code] = 0 + code_dict[code] += 1 + print codes + print code_dict + + +# plot rtt times as peaks. That's the fast and easy way. +def plot_rtt_times(data, fignum): + print "plot RTT times" + rx = extract_libusb("rx", data) + tx = extract_libusb("tx", data) + + scale = 10e-6 + rx_diff = np.multiply(np.subtract(rx[3], rx[4]), scale) + tx_diff = np.multiply(np.subtract(tx[3], tx[4]), scale) + + plt.figure(fignum) + plt.plot(get_x_axis(rx[3]), rx_diff, marker='x', ls='', label="rx RTT") + plt.plot(get_x_axis(tx[3]), tx_diff, marker='x', ls='', label="tx RTT") + plt.title("Round trip times") + plt.ylabel("RTT (us)") + plt.grid() + plt.legend() + + +# plot RTT as actual lines as long as buffers are on the fly. +# This can take a long time if the function has to print a lot of small lines. Careful with this! +def plot_rtt_lines(data, fignum): + print "plot RTT lines" + rx = extract_libusb("rx", data) + #tx = extract_libusb("tx", data) + + if len(data) == 0 or len(rx) == 0: + return + + plt.figure(fignum) + for i in range(len(rx[0])): + if rx[0][i] > -1: + start = rx[4][i] + stop = rx[3][i] + status = rx[2][i] + + val = rx[0][i]#(stop - start) * scale + if not status == 0: + if status == 2: + print "status = ", status + val +=0.5 + xaxis = get_x_axis([start, stop]) + plt.plot(xaxis, [val, val], marker='x') + plt.ylabel('buffer number') + + # Careful with these lines here. + # Basically they should always have these values to separate CTRL, TX, RX buffer number blocks. + # But these values can be adjusted. Thus, it requires you to adjust these lines + plt.axhline(15.5) + plt.axhline(31.5) + plt.axhline(47.5) + plt.grid() + + +# only plot on-the-fly buffers. +def plot_buff_otf(trx, nrange, data): + d = extract_libusb(trx, data) + res = [[], []] + num = 0 + for i in range(len(d[0])): + if d[0][i] in nrange: + res + + +# If there are still unknown lines after cleanup, they can be caught and printed here. +# This way you can check what got caught but shouldn't have been caught. +def get_unknown_lines(data): + # These are the 3 known starting lines. More might be added in the future. + known = ['super_recv_packet_handler', 'super_send_packet_handler', 'libusb1_zero_copy'] + res = [] + for i in range(len(data)): + if not data[i][0] in known: + print data[i] + res.append(data[i]) + return res + +# LUT for all the return codes +rx_metadata_error_codes = {0x0: "NONE", 0x1: "TIMEOUT", 0x2: "LATE_COMMAND", 0x4: "BROKEN_CHAIN", 0x8: "OVERFLOW", + 0xc: "ALIGNMENT", 0xf: "BAD_PACKET"} + + +def parse_args(): + """ Parse args, yo """ + parser = argparse.ArgumentParser(description='Plot tool for debug prints.') + parser.add_argument('-f', '--filename', default=None, help='Debug output file') + return parser.parse_args() + +# Be really careful with the input files. They get pretty huge in a small time. +# Doing some of the plotting can eat up a lot of time then. +# Although this file contains a lot of functions by now, it is still left to the user to use everythin correctly. +def main(): + args = parse_args() + filename = args.filename + print "get data from: ", filename + #pref1 = "super_recv_packet_handler" + #pref2 = "recv" + + # Here you get the data from a file + data = get_data(filename) + #print "data len: ", len(data) + + # extract lines with unknown content. + unknown = get_unknown_lines(data) + + # plot status codes and RTT lines. + plot_status_codes_over_time(data, 0) + plot_rtt_lines(data, 0) + #plot_rtt_times(data, 0) + + #[tx, rx] = extract_txrx(data) + #print "txlen\t", len(tx[0]) + #print "rxlen\t", len(rx[0]) + + + #print "plot data" + #plt.title(filename) + #plt.plot(tx_data[0], tx_data[7], 'r', marker='o', label='TX') + #plt.plot(rx_data[0], rx_data[11], 'g', marker='x', label='RX') + #for j in jiffies: + # plt.axvline(x=j[0], color='r') + # plt.axvline(x=j[1], color='g') + # + #plt.xlabel('wallclock (us)') + #plt.ylabel('timestamp (ticks)') + #plt.legend() + + #lencal = 200000 + + # calculate and plot rx throughput + #rxthr = throughput([rx[1], rx[3], rx[4]]) + #plt.plot(rxthr[0:lencal]) + #rxav = ma(rxthr[0:lencal], 2000) + #plt.plot(rxav) + + # calculate and plot tx throughput + #txthr = throughput([tx[1], tx[3], tx[4]]) + #plt.plot(txthr[0:lencal]) + #txav = ma(txthr[0:lencal], 20) + #plt.plot(txav) + + + #bp = bps(data[1], data[2]) + #print np.sum(bp) + #ave = np.sum(bp)/len(bp) + #print ave + #plt.plot(tx_data[0], tx_data[2], 'r') + #plt.plot(rx_data[0], rx_data[2], 'b') + #plt.plot(bp, 'g', marker='+') + #plt.plot(np.multiply(data[1], 1e6), 'r', marker='o') + #plt.plot(np.multiply(data[3],1e2), 'b', marker='x') + #plt.plot(ave) + + # in the end, put a grid on the graph and show it. + plt.grid() + plt.show() + +if __name__ == '__main__': + print "[WARNING] This tool is in alpha status. Only use if you know what you're doing!" + main() + |