diff options
| -rw-r--r-- | host/docs/capi.dox | 2 | ||||
| -rw-r--r-- | host/docs/rd_testing.dox | 6 | ||||
| -rw-r--r-- | host/docs/usrp_n3xx.dox | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/host/docs/capi.dox b/host/docs/capi.dox index 717f5a78b..440e8e923 100644 --- a/host/docs/capi.dox +++ b/host/docs/capi.dox @@ -1,4 +1,4 @@ -/*! \page page_python C API +/*! \page page_capi C API UHD supports a C API, in case the C++ or Python APIs are not the right solution for your application. diff --git a/host/docs/rd_testing.dox b/host/docs/rd_testing.dox index 2708944bf..0f54af675 100644 --- a/host/docs/rd_testing.dox +++ b/host/docs/rd_testing.dox @@ -649,11 +649,11 @@ tbd | Test Code | Device | Peripherals | Manual Test Procedure | Automatic Test Procedure | |---------------------|-----------|---------------------|---------------------------------|-------------------------------| | BIST-N310-v1 | 1xN310 | DB-15 GPIO Loopback | \ref rdtesting_bist_n3x0_manual | \ref rdtesting_bist_n3x0_auto | -| BIST-N300-v1 | 1xN300 | DB-15 GPIO Loopback | \ref rdtesting_bist_n3x0_manual | \ref rdtesting_bist_n300_auto | +| BIST-N300-v1 | 1xN300 | DB-15 GPIO Loopback | \ref rdtesting_bist_n3x0_manual | \ref rdtesting_bist_n3x0_auto | Some of our devices have built-in self-tests (BISTs). -\subsection rdtesting_bist_n310_manual N300/N310 Manual Procedure +\subsection rdtesting_bist_n3x0_manual N300/N310 Manual Procedure Note: The N300 and N310 have identical BISTs. @@ -692,7 +692,7 @@ not desired, re-run `uhd_image_loader` to load whatever image is requested. Note: The N300 and N310 have identical BISTs. -Assuming the peripherals described in \ref rdtesting_bist_n310_manual are all +Assuming the peripherals described in \ref rdtesting_bist_n3x0_manual are all plugged in, the test can trivially be executed automatically by running $ n3xx_bist standard diff --git a/host/docs/usrp_n3xx.dox b/host/docs/usrp_n3xx.dox index 482a97e44..eb412a020 100644 --- a/host/docs/usrp_n3xx.dox +++ b/host/docs/usrp_n3xx.dox @@ -791,7 +791,7 @@ the initialization sequence, the following steps are performed: - All clocking is initialized - The JESD links are trained and brought up (between the FPGA and the AD9371) - The AD9371 is reset, its firmware is uploaded, and calibrations are - initialized (See also \section n3xx_mg_calibrations) + initialized (See also \ref n3xx_mg_calibrations) - N310 only: The multi-chip synchronization is performed to align all the RFICs to the common time and clock reference |