diff options
| -rw-r--r-- | usrp2/top/B100/B100.ucf | 3 | ||||
| -rw-r--r-- | usrp2/top/B100/B100.v | 5 |
2 files changed, 6 insertions, 2 deletions
diff --git a/usrp2/top/B100/B100.ucf b/usrp2/top/B100/B100.ucf index c86501e72..1c04c5d8d 100644 --- a/usrp2/top/B100/B100.ucf +++ b/usrp2/top/B100/B100.ucf @@ -25,6 +25,9 @@ NET "reset_n" LOC = "D5" ; NET "PPS_IN" LOC = "M14" ; NET "reset_codec" LOC = "B14" ; +## recycles fpga_cfg_cclk for reset from fw +NET "ext_reset" LOC = "R14" ; + ## GPIF NET "GPIF_D<15>" LOC = "P7" ; NET "GPIF_D<14>" LOC = "N8" ; diff --git a/usrp2/top/B100/B100.v b/usrp2/top/B100/B100.v index b5691d1c3..dcda974b4 100644 --- a/usrp2/top/B100/B100.v +++ b/usrp2/top/B100/B100.v @@ -41,7 +41,8 @@ module B100 input [11:0] adc, input RXSYNC, input PPS_IN, - input reset_n, output reset_codec + input reset_n, output reset_codec, + input ext_reset ); assign reset_codec = 1; // Believed to be active low @@ -55,7 +56,7 @@ module B100 BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); - reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset)); + reset_sync reset_sync(.clk(clk_fpga), .reset_in((~reset_n) | (~ext_reset)), .reset_out(reset)); // ///////////////////////////////////////////////////////////////////////// // SPI |