diff options
| -rw-r--r-- | host/lib/usrp/x300/x300_defaults.hpp | 107 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.cpp | 106 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.hpp | 62 |
3 files changed, 159 insertions, 116 deletions
diff --git a/host/lib/usrp/x300/x300_defaults.hpp b/host/lib/usrp/x300/x300_defaults.hpp new file mode 100644 index 000000000..5471b02c6 --- /dev/null +++ b/host/lib/usrp/x300/x300_defaults.hpp @@ -0,0 +1,107 @@ +// +// Copyright 2018 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: GPL-3.0-or-later +// + +#ifndef INCLUDED_X300_DEFAULTS_HPP +#define INCLUDED_X300_DEFAULTS_HPP + +#include <uhd/transport/udp_simple.hpp> //mtu +#include "../device3/device3_impl.hpp" +#include <string> + +#define NIUSRPRIO_DEFAULT_RPC_PORT "5444" + + +namespace uhd { +namespace usrp { +namespace x300 { + +static constexpr uint32_t RADIO_DEST_PREFIX_TX = 0; +static constexpr size_t XB_DST_E0 = 0; +static constexpr size_t XB_DST_E1 = 1; +static constexpr size_t XB_DST_PCI = 2; +static constexpr size_t XB_DST_R0 = 3; // Radio 0 -> Slot A +static constexpr size_t XB_DST_R1 = 4; // Radio 1 -> Slot B +static constexpr size_t XB_DST_CE0 = 5; + +static constexpr size_t SRC_ADDR0 = 0; +static constexpr size_t SRC_ADDR1 = 1; +static constexpr size_t DST_ADDR = 2; + +static constexpr double DEFAULT_TICK_RATE = 200e6; // Hz +static constexpr double BUS_CLOCK_RATE = 187.5e6; //Hz +static const std::vector<double> TICK_RATE_OPTIONS{120e6, 184.32e6, 200e6}; + +static const std::string FW_FILE_NAME = "usrp_x300_fw.bin"; + +// Clock & Time-related defaults +static const std::string DEFAULT_CLOCK_SOURCE = "internal"; +static const std::string DEFAULT_TIME_SOURCE = "internal"; +static const bool DEFAULT_TIME_OUTPUT = true; + +static const std::vector<std::string> CLOCK_SOURCE_OPTIONS{ + "internal", + "external", + "gpsdo" +}; +static const std::vector<std::string> TIME_SOURCE_OPTIONS{ + "internal", + "external", + "gpsdo" +}; +static const std::vector<double> EXTERNAL_FREQ_OPTIONS{10e6, 30.72e6, 200e6}; + +static constexpr size_t RX_SW_BUFF_SIZE_ETH = 0x2000000;//32MiB For an ~8k frame size any size >32MiB is just wasted buffer space +static constexpr size_t RX_SW_BUFF_SIZE_ETH_MACOS = 0x100000; //1Mib + +//The FIFO closest to the DMA controller is 1023 elements deep for RX and 1029 elements deep for TX +//where an element is 8 bytes. The buffers (number of frames * frame size) must be aligned to the +//memory page size. For the control, we are getting lucky because 64 frames * 256 bytes each aligns +//with the typical page size of 4096 bytes. Since most page sizes are 4096 bytes or some multiple of +//that, keep the number of frames * frame size aligned to it. +static constexpr size_t PCIE_RX_DATA_FRAME_SIZE = 4096; //bytes +static constexpr size_t PCIE_RX_DATA_NUM_FRAMES = 4096; +static constexpr size_t PCIE_TX_DATA_FRAME_SIZE = 4096; //bytes +static constexpr size_t PCIE_TX_DATA_NUM_FRAMES = 4096; +static constexpr size_t PCIE_MSG_FRAME_SIZE = 256; //bytes +static constexpr size_t PCIE_MSG_NUM_FRAMES = 64; +static constexpr size_t PCIE_MAX_CHANNELS = 6; +static constexpr size_t PCIE_MAX_MUXED_CTRL_XPORTS = 32; +static constexpr size_t PCIE_MAX_MUXED_ASYNC_XPORTS = 4; + +static const size_t DATA_FRAME_MAX_SIZE = 8000; // CHDR packet size in bytes +static const size_t XGE_DATA_FRAME_SEND_SIZE = 4000; // Reduced to make sure flow control packets are not blocked for too long at high rates +static const size_t XGE_DATA_FRAME_RECV_SIZE = 8000; +static const size_t GE_DATA_FRAME_SEND_SIZE = 1472; +static const size_t GE_DATA_FRAME_RECV_SIZE = 1472; + +static const size_t ETH_MSG_FRAME_SIZE = uhd::transport::udp_simple::mtu; //bytes +// MTU throttling for ethernet/TX (see above): +static constexpr size_t ETH_DATA_FRAME_MAX_TX_SIZE = 8000; + +static constexpr double RECV_OFFLOAD_BUFFER_TIMEOUT = 0.1; //seconds +static constexpr double THREAD_BUFFER_TIMEOUT = 0.1; // Time in seconds + +static constexpr size_t ETH_MSG_NUM_FRAMES = 64; +static constexpr size_t ETH_DATA_NUM_FRAMES = 32; +static constexpr double DEFAULT_SYSREF_RATE = 10e6; + +// Limit the number of initialization threads +static const size_t MAX_INIT_THREADS = 10; + +static const size_t MAX_RATE_PCIE = 800000000; // bytes/s +static const size_t MAX_RATE_10GIGE = (size_t)( // bytes/s + 10e9 / 8 * // wire speed multiplied by percentage of packets that is sample data + ( float(DATA_FRAME_MAX_SIZE - uhd::usrp::DEVICE3_TX_MAX_HDR_LEN) / + float(DATA_FRAME_MAX_SIZE + 8 /* UDP header */ + 20 /* Ethernet header length */ ))); +static const size_t MAX_RATE_1GIGE = (size_t)( // bytes/s + 10e9 / 8 * // wire speed multiplied by percentage of packets that is sample data + ( float(GE_DATA_FRAME_RECV_SIZE - uhd::usrp::DEVICE3_TX_MAX_HDR_LEN) / + float(GE_DATA_FRAME_RECV_SIZE + 8 /* UDP header */ + 20 /* Ethernet header length */ ))); + +}}} /* namespace uhd::usrp::x300 */ + +#endif /* INCLUDED_X300_DEFAULTS_HPP */ + diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index 069adfe73..9a112e900 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -35,10 +35,6 @@ #include <chrono> #include <thread> -#define NIUSRPRIO_DEFAULT_RPC_PORT "5444" - -#define X300_REV(x) ((x) - "A" + 1) - using namespace uhd; using namespace uhd::usrp; using namespace uhd::rfnoc; @@ -423,7 +419,7 @@ x300_impl::x300_impl(const uhd::device_addr_t &dev_addr) size_t num_usrps = 0; while (num_usrps < total_usrps) { - size_t init_usrps = std::min(total_usrps - num_usrps, X300_MAX_INIT_THREADS); + size_t init_usrps = std::min(total_usrps - num_usrps, x300::MAX_INIT_THREADS); boost::thread_group setup_threads; for (size_t i = 0; i < init_usrps; i++) { @@ -473,10 +469,10 @@ void x300_impl::mboard_members_t::discover_eth( // Choose the interface based on the index parity if (i % 2 == 0) { conn_iface.type = X300_IFACE_ETH0; - conn_iface.link_rate = loaded_fpga_image == "HG" ? X300_MAX_RATE_1GIGE : X300_MAX_RATE_10GIGE; + conn_iface.link_rate = loaded_fpga_image == "HG" ? x300::MAX_RATE_1GIGE : x300::MAX_RATE_10GIGE; } else { conn_iface.type = X300_IFACE_ETH1; - conn_iface.link_rate = X300_MAX_RATE_10GIGE; + conn_iface.link_rate = x300::MAX_RATE_10GIGE; } break; } @@ -494,19 +490,19 @@ void x300_impl::mboard_members_t::discover_eth( if (addr == boost::asio::ip::address_v4( uint32_t(X300_DEFAULT_IP_ETH0_1G)).to_string()) { conn_iface.type = X300_IFACE_ETH0; - conn_iface.link_rate = X300_MAX_RATE_1GIGE; + conn_iface.link_rate = x300::MAX_RATE_1GIGE; } else if (addr == boost::asio::ip::address_v4( uint32_t(X300_DEFAULT_IP_ETH1_1G)).to_string()) { conn_iface.type = X300_IFACE_ETH1; - conn_iface.link_rate = X300_MAX_RATE_1GIGE; + conn_iface.link_rate = x300::MAX_RATE_1GIGE; } else if (addr == boost::asio::ip::address_v4( uint32_t(X300_DEFAULT_IP_ETH0_10G)).to_string()) { conn_iface.type = X300_IFACE_ETH0; - conn_iface.link_rate = X300_MAX_RATE_10GIGE; + conn_iface.link_rate = x300::MAX_RATE_10GIGE; } else if (addr == boost::asio::ip::address_v4( uint32_t(X300_DEFAULT_IP_ETH1_10G)).to_string()) { conn_iface.type = X300_IFACE_ETH1; - conn_iface.link_rate = X300_MAX_RATE_10GIGE; + conn_iface.link_rate = x300::MAX_RATE_10GIGE; } else { throw uhd::assertion_error(str(boost::format( "X300 Initialization Error: Failed to match address %s with " @@ -616,12 +612,12 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) nirio_status_to_exception(status, "x300_impl: Could not initialize RIO session."); //Tell the quirks object which FIFOs carry TX stream data - const uint32_t tx_data_fifos[2] = {X300_RADIO_DEST_PREFIX_TX, X300_RADIO_DEST_PREFIX_TX + 3}; + const uint32_t tx_data_fifos[2] = {x300::RADIO_DEST_PREFIX_TX, x300::RADIO_DEST_PREFIX_TX + 3}; mb.rio_fpga_interface->get_kernel_proxy()->get_rio_quirks().register_tx_streams(tx_data_fifos, 2); - _tree->create<size_t>(mb_path / "mtu/recv").set(X300_PCIE_RX_DATA_FRAME_SIZE); - _tree->create<size_t>(mb_path / "mtu/send").set(X300_PCIE_TX_DATA_FRAME_SIZE); - _tree->create<double>(mb_path / "link_max_rate").set(X300_MAX_RATE_PCIE); + _tree->create<size_t>(mb_path / "mtu/recv").set(x300::PCIE_RX_DATA_FRAME_SIZE); + _tree->create<size_t>(mb_path / "mtu/send").set(x300::PCIE_TX_DATA_FRAME_SIZE); + _tree->create<double>(mb_path / "link_max_rate").set(x300::MAX_RATE_PCIE); } for(const std::string &key: dev_addr.keys()) @@ -656,7 +652,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) if (dev_addr.has_key("fw")) { const std::string x300_fw_image = find_image_path( - dev_addr.has_key("fw")? dev_addr["fw"] : X300_FW_FILE_NAME + dev_addr.has_key("fw")? dev_addr["fw"] : x300::FW_FILE_NAME ); x300_load_fw(mb.zpu_ctrl, x300_fw_image); } @@ -676,7 +672,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) mb.zpu_spi = spi_core_3000::make(mb.zpu_ctrl, SR_ADDR(SET0_BASE, ZPU_SR_SPI), SR_ADDR(SET0_BASE, ZPU_RB_SPI)); mb.zpu_i2c = i2c_core_100_wb32::make(mb.zpu_ctrl, I2C1_BASE); - mb.zpu_i2c->set_clock_rate(X300_BUS_CLOCK_RATE/2); + mb.zpu_i2c->set_clock_rate(x300::BUS_CLOCK_RATE/2); //////////////////////////////////////////////////////////////////// // print network routes mapping @@ -771,10 +767,10 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) frame_size_t req_max_frame_size; req_max_frame_size.recv_frame_size = (mb.recv_args.has_key("recv_frame_size")) \ ? boost::lexical_cast<size_t>(mb.recv_args["recv_frame_size"]) \ - : X300_DATA_FRAME_MAX_SIZE; + : x300::DATA_FRAME_MAX_SIZE; req_max_frame_size.send_frame_size = (mb.send_args.has_key("send_frame_size")) \ ? boost::lexical_cast<size_t>(mb.send_args["send_frame_size"]) \ - : X300_DATA_FRAME_MAX_SIZE; + : x300::DATA_FRAME_MAX_SIZE; #if defined UHD_PLATFORM_LINUX const std::string mtu_tool("ip link"); @@ -843,8 +839,8 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) { link_max_rate += conn.link_rate; - size_t rec_send_frame_size = conn.link_rate == X300_MAX_RATE_1GIGE ? X300_1GE_DATA_FRAME_SEND_SIZE : X300_10GE_DATA_FRAME_SEND_SIZE; - size_t rec_recv_frame_size = conn.link_rate == X300_MAX_RATE_1GIGE ? X300_1GE_DATA_FRAME_RECV_SIZE : X300_10GE_DATA_FRAME_RECV_SIZE; + size_t rec_send_frame_size = conn.link_rate == x300::MAX_RATE_1GIGE ? x300::GE_DATA_FRAME_SEND_SIZE : x300::XGE_DATA_FRAME_SEND_SIZE; + size_t rec_recv_frame_size = conn.link_rate == x300::MAX_RATE_1GIGE ? x300::GE_DATA_FRAME_RECV_SIZE : x300::XGE_DATA_FRAME_RECV_SIZE; if (_max_frame_sizes.send_frame_size < rec_send_frame_size) { @@ -926,7 +922,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) UHD_LOGGER_DEBUG("X300") << "Setting up RF frontend clocking..."; //Initialize clock control registers. NOTE: This does not configure the LMK yet. - const double requested_mcr = dev_addr.cast<double>("master_clock_rate", X300_DEFAULT_TICK_RATE); + const double requested_mcr = dev_addr.cast<double>("master_clock_rate", x300::DEFAULT_TICK_RATE); //Some daughterboards may require other rates, but these defaults //work best for all newer daughterboards (i.e. CBX, WBX, SBX, UBX, //and TwinRX). @@ -943,16 +939,16 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) mb.hw_rev, requested_mcr, dev_addr.cast<double>("dboard_clock_rate", default_dboard_clk_rate), - dev_addr.cast<double>("system_ref_rate", X300_DEFAULT_SYSREF_RATE)); + dev_addr.cast<double>("system_ref_rate", x300::DEFAULT_SYSREF_RATE)); mb.fw_regmap->ref_freq_reg.write( fw_regmap_t::ref_freq_reg_t::REF_FREQ, uint32_t(dev_addr.cast<double>("system_ref_rate", - X300_DEFAULT_SYSREF_RATE))); + x300::DEFAULT_SYSREF_RATE))); //Initialize clock source to use internal reference and generate //a valid radio clock. This may change after configuration is done. //This will configure the LMK and wait for lock - update_clock_source(mb, X300_DEFAULT_CLOCK_SOURCE); + update_clock_source(mb, x300::DEFAULT_CLOCK_SOURCE); //////////////////////////////////////////////////////////////////// // create clock properties @@ -1019,7 +1015,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) // setup clock sources and properties //////////////////////////////////////////////////////////////////// _tree->create<std::string>(mb_path / "clock_source" / "value") - .set(X300_DEFAULT_CLOCK_SOURCE) + .set(x300::DEFAULT_CLOCK_SOURCE) .add_coerced_subscriber([this, &mb](const std::string& clock_source){ this->update_clock_source(mb, clock_source); }) @@ -1080,8 +1076,8 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) enumerate_rfnoc_blocks( mb_i, n_rfnoc_blocks, - X300_XB_DST_PCI + 1, /* base port */ - uhd::sid_t(X300_SRC_ADDR0, 0, X300_DST_ADDR + mb_i, 0), + x300::XB_DST_PCI + 1, /* base port */ + uhd::sid_t(x300::SRC_ADDR0, 0, x300::DST_ADDR + mb_i, 0), dev_addr ); //////////////// RFNOC ///////////////// @@ -1182,7 +1178,7 @@ uint32_t x300_impl::mboard_members_t::allocate_pcie_dma_chan(const uhd::sid_t &t if (_dma_chan_pool.count(raw_sid) == 0) { size_t channel = _dma_chan_pool.size() + FIRST_DATA_CHANNEL; - if (channel > X300_PCIE_MAX_CHANNELS) { + if (channel > x300::PCIE_MAX_CHANNELS) { throw uhd::runtime_error("Trying to allocate more DMA channels than are available"); } _dma_chan_pool[raw_sid] = channel; @@ -1206,10 +1202,10 @@ static uhd::transport::muxed_zero_copy_if::sptr make_muxed_pcie_msg_xport size_t max_muxed_ports ) { zero_copy_xport_params buff_args; - buff_args.send_frame_size = X300_PCIE_MSG_FRAME_SIZE; - buff_args.recv_frame_size = X300_PCIE_MSG_FRAME_SIZE; - buff_args.num_send_frames = X300_PCIE_MSG_NUM_FRAMES * max_muxed_ports; - buff_args.num_recv_frames = X300_PCIE_MSG_NUM_FRAMES * max_muxed_ports; + buff_args.send_frame_size = x300::PCIE_MSG_FRAME_SIZE; + buff_args.recv_frame_size = x300::PCIE_MSG_FRAME_SIZE; + buff_args.num_send_frames = x300::PCIE_MSG_NUM_FRAMES * max_muxed_ports; + buff_args.num_recv_frames = x300::PCIE_MSG_NUM_FRAMES * max_muxed_ports; zero_copy_if::sptr base_xport = nirio_zero_copy::make( rio_fpga_interface, dma_channel_num, @@ -1222,7 +1218,7 @@ uhd::both_xports_t x300_impl::make_transport( const xport_type_t xport_type, const uhd::device_addr_t& args ) { - const size_t mb_index = address.get_dst_addr() - X300_DST_ADDR; + const size_t mb_index = address.get_dst_addr() - x300::DST_ADDR; mboard_members_t &mb = _mb[mb_index]; const uhd::device_addr_t& xport_args = (xport_type == CTRL) ? uhd::device_addr_t() : args; zero_copy_xport_params default_buff_args; @@ -1230,7 +1226,7 @@ uhd::both_xports_t x300_impl::make_transport( both_xports_t xports; xports.endianness = mb.if_pkt_is_big_endian ? ENDIANNESS_BIG : ENDIANNESS_LITTLE; if (mb.xport_path == "nirio") { - xports.send_sid = this->allocate_sid(mb, address, X300_SRC_ADDR0, X300_XB_DST_PCI); + xports.send_sid = this->allocate_sid(mb, address, x300::SRC_ADDR0, x300::XB_DST_PCI); xports.recv_sid = xports.send_sid.reversed(); uint32_t dma_channel_num = mb.allocate_pcie_dma_chan(xports.send_sid, xport_type); @@ -1242,7 +1238,7 @@ uhd::both_xports_t x300_impl::make_transport( mb.ctrl_dma_xport = make_muxed_pcie_msg_xport( mb.rio_fpga_interface, dma_channel_num, - X300_PCIE_MAX_MUXED_CTRL_XPORTS); + x300::PCIE_MAX_MUXED_CTRL_XPORTS); } //Create a virtual control transport xports.recv = mb.ctrl_dma_xport->make_stream(xports.recv_sid.get_dst()); @@ -1254,7 +1250,7 @@ uhd::both_xports_t x300_impl::make_transport( mb.async_msg_dma_xport = make_muxed_pcie_msg_xport( mb.rio_fpga_interface, dma_channel_num, - X300_PCIE_MAX_MUXED_ASYNC_XPORTS); + x300::PCIE_MAX_MUXED_ASYNC_XPORTS); } //Create a virtual async message transport xports.recv = mb.async_msg_dma_xport->make_stream(xports.recv_sid.get_dst()); @@ -1262,23 +1258,23 @@ uhd::both_xports_t x300_impl::make_transport( //Transport for data stream default_buff_args.send_frame_size = (xport_type == TX_DATA) - ? X300_PCIE_TX_DATA_FRAME_SIZE - : X300_PCIE_MSG_FRAME_SIZE; + ? x300::PCIE_TX_DATA_FRAME_SIZE + : x300::PCIE_MSG_FRAME_SIZE; default_buff_args.recv_frame_size = (xport_type == RX_DATA) - ? X300_PCIE_RX_DATA_FRAME_SIZE - : X300_PCIE_MSG_FRAME_SIZE; + ? x300::PCIE_RX_DATA_FRAME_SIZE + : x300::PCIE_MSG_FRAME_SIZE; default_buff_args.num_send_frames = (xport_type == TX_DATA) - ? X300_PCIE_TX_DATA_NUM_FRAMES - : X300_PCIE_MSG_NUM_FRAMES; + ? x300::PCIE_TX_DATA_NUM_FRAMES + : x300::PCIE_MSG_NUM_FRAMES; default_buff_args.num_recv_frames = (xport_type == RX_DATA) - ? X300_PCIE_RX_DATA_NUM_FRAMES - : X300_PCIE_MSG_NUM_FRAMES; + ? x300::PCIE_RX_DATA_NUM_FRAMES + : x300::PCIE_MSG_NUM_FRAMES; xports.recv = nirio_zero_copy::make( mb.rio_fpga_interface, dma_channel_num, @@ -1305,9 +1301,9 @@ uhd::both_xports_t x300_impl::make_transport( mb.next_src_addr; x300_eth_conn_t conn = mb.eth_conns[next_src_addr]; const uint32_t xbar_src_addr = - next_src_addr==0 ? X300_SRC_ADDR0 : X300_SRC_ADDR1; + next_src_addr==0 ? x300::SRC_ADDR0 : x300::SRC_ADDR1; const uint32_t xbar_src_dst = - conn.type==X300_IFACE_ETH0 ? X300_XB_DST_E0 : X300_XB_DST_E1; + conn.type==X300_IFACE_ETH0 ? x300::XB_DST_E0 : x300::XB_DST_E1; if (xport_type != TX_DATA) next_src_addr = (next_src_addr + 1) % mb.eth_conns.size(); xports.send_sid = this->allocate_sid(mb, address, xbar_src_addr, xbar_src_dst); @@ -1316,15 +1312,15 @@ uhd::both_xports_t x300_impl::make_transport( // Set size and number of frames size_t system_max_send_frame_size = (size_t) _max_frame_sizes.send_frame_size; size_t system_max_recv_frame_size = (size_t) _max_frame_sizes.recv_frame_size; - default_buff_args.send_frame_size = std::min(system_max_send_frame_size, X300_ETH_MSG_FRAME_SIZE); - default_buff_args.recv_frame_size = std::min(system_max_recv_frame_size, X300_ETH_MSG_FRAME_SIZE); + default_buff_args.send_frame_size = std::min(system_max_send_frame_size, x300::ETH_MSG_FRAME_SIZE); + default_buff_args.recv_frame_size = std::min(system_max_recv_frame_size, x300::ETH_MSG_FRAME_SIZE); default_buff_args.num_send_frames = 1; // never need multiple frames on send default_buff_args.num_recv_frames = 1; // only need multiple frames with offload thread default_buff_args.send_buff_size = conn.link_rate / 50; // 20ms - default_buff_args.recv_buff_size = std::max(conn.link_rate / 50, X300_ETH_MSG_NUM_FRAMES * X300_ETH_MSG_FRAME_SIZE); // enough to hold greater of 20ms or number of msg frames + default_buff_args.recv_buff_size = std::max(conn.link_rate / 50, x300::ETH_MSG_NUM_FRAMES * x300::ETH_MSG_FRAME_SIZE); // enough to hold greater of 20ms or number of msg frames if (xport_type == TX_DATA) { - size_t default_frame_size = conn.link_rate == X300_MAX_RATE_1GIGE ? X300_1GE_DATA_FRAME_SEND_SIZE : X300_10GE_DATA_FRAME_SEND_SIZE; + size_t default_frame_size = conn.link_rate == x300::MAX_RATE_1GIGE ? x300::GE_DATA_FRAME_SEND_SIZE : x300::XGE_DATA_FRAME_SEND_SIZE; default_buff_args.send_frame_size = args.cast<size_t>("send_frame_size", std::min(default_frame_size, system_max_send_frame_size)); if (default_buff_args.send_frame_size > system_max_send_frame_size) { @@ -1339,7 +1335,7 @@ uhd::both_xports_t x300_impl::make_transport( } else if (xport_type == RX_DATA) { - size_t default_frame_size = conn.link_rate == X300_MAX_RATE_1GIGE ? X300_1GE_DATA_FRAME_RECV_SIZE : X300_10GE_DATA_FRAME_RECV_SIZE; + size_t default_frame_size = conn.link_rate == x300::MAX_RATE_1GIGE ? x300::GE_DATA_FRAME_RECV_SIZE : x300::XGE_DATA_FRAME_RECV_SIZE; default_buff_args.recv_frame_size = args.cast<size_t>("recv_frame_size", std::min(default_frame_size, system_max_recv_frame_size)); if (default_buff_args.recv_frame_size > system_max_recv_frame_size) { @@ -1373,7 +1369,7 @@ uhd::both_xports_t x300_impl::make_transport( if (xport_type == RX_DATA) { xports.recv = zero_copy_recv_offload::make( xports.recv, - X300_RECV_OFFLOAD_BUFFER_TIMEOUT + x300::RECV_OFFLOAD_BUFFER_TIMEOUT ); } xports.send = xports.recv; @@ -1698,9 +1694,9 @@ x300_impl::frame_size_t x300_impl::determine_max_frame_size(const std::string &a //Reducing range of (min,max) by setting max value to 10gig max_frame_size as larger sizes are not supported size_t min_recv_frame_size = sizeof(x300_mtu_t); - size_t max_recv_frame_size = std::min(user_frame_size.recv_frame_size, X300_DATA_FRAME_MAX_SIZE) & size_t(~3); + size_t max_recv_frame_size = std::min(user_frame_size.recv_frame_size, x300::DATA_FRAME_MAX_SIZE) & size_t(~3); size_t min_send_frame_size = sizeof(x300_mtu_t); - size_t max_send_frame_size = std::min(user_frame_size.send_frame_size, X300_DATA_FRAME_MAX_SIZE) & size_t(~3); + size_t max_send_frame_size = std::min(user_frame_size.send_frame_size, x300::DATA_FRAME_MAX_SIZE) & size_t(~3); UHD_LOGGER_DEBUG("X300") << "Determining maximum frame size... "; while (min_recv_frame_size < max_recv_frame_size) diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index dfe038107..d339c7bd0 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -12,6 +12,7 @@ #include "x300_clock_ctrl.hpp" #include "x300_fw_common.h" #include "x300_regs.hpp" +#include "x300_defaults.hpp" #include "../device3/device3_impl.hpp" #include <uhd/property_tree.hpp> @@ -33,67 +34,6 @@ #include <boost/weak_ptr.hpp> #include <atomic> -static const std::string X300_FW_FILE_NAME = "usrp_x300_fw.bin"; -static const std::string X300_DEFAULT_CLOCK_SOURCE = "internal"; - -static const double X300_DEFAULT_TICK_RATE = 200e6; //Hz -static const double X300_BUS_CLOCK_RATE = 187.5e6; //Hz - -//The FIFO closest to the DMA controller is 1023 elements deep for RX and 1029 elements deep for TX -//where an element is 8 bytes. The buffers (number of frames * frame size) must be aligned to the -//memory page size. For the control, we are getting lucky because 64 frames * 256 bytes each aligns -//with the typical page size of 4096 bytes. Since most page sizes are 4096 bytes or some multiple of -//that, keep the number of frames * frame size aligned to it. -static const size_t X300_PCIE_RX_DATA_FRAME_SIZE = 4096; //bytes -static const size_t X300_PCIE_RX_DATA_NUM_FRAMES = 4096; -static const size_t X300_PCIE_TX_DATA_FRAME_SIZE = 4096; //bytes -static const size_t X300_PCIE_TX_DATA_NUM_FRAMES = 4096; -static const size_t X300_PCIE_MSG_FRAME_SIZE = 256; //bytes -static const size_t X300_PCIE_MSG_NUM_FRAMES = 64; -static const size_t X300_PCIE_MAX_CHANNELS = 6; -static const size_t X300_PCIE_MAX_MUXED_CTRL_XPORTS = 32; -static const size_t X300_PCIE_MAX_MUXED_ASYNC_XPORTS = 4; - -static const size_t X300_DATA_FRAME_MAX_SIZE = 8000; // CHDR packet size in bytes - -// Ethernet frame sizes -static const size_t X300_10GE_DATA_FRAME_SEND_SIZE = 4000; // Reduced to make sure flow control packets are not blocked for too long at high rates -static const size_t X300_10GE_DATA_FRAME_RECV_SIZE = 8000; -static const size_t X300_1GE_DATA_FRAME_SEND_SIZE = 1472; -static const size_t X300_1GE_DATA_FRAME_RECV_SIZE = 1472; -static const size_t X300_ETH_MSG_FRAME_SIZE = uhd::transport::udp_simple::mtu; //bytes -static const size_t X300_ETH_MSG_NUM_FRAMES = 64; - -static const double X300_RECV_OFFLOAD_BUFFER_TIMEOUT = 0.1; //seconds - -static const double X300_DEFAULT_SYSREF_RATE = 10e6; - -// Limit the number of initialization threads -static const size_t X300_MAX_INIT_THREADS = 10; - -static const size_t X300_MAX_RATE_PCIE = 800000000; // bytes/s -static const size_t X300_MAX_RATE_10GIGE = (size_t)( // bytes/s - 10e9 / 8 * // wire speed multiplied by percentage of packets that is sample data - ( float(X300_DATA_FRAME_MAX_SIZE - uhd::usrp::DEVICE3_TX_MAX_HDR_LEN) / - float(X300_DATA_FRAME_MAX_SIZE + 8 /* UDP header */ + 20 /* Ethernet header length */ ))); -static const size_t X300_MAX_RATE_1GIGE = (size_t)( // bytes/s - 1e9 / 8 * // wire speed multiplied by percentage of packets that is sample data - ( float(X300_DATA_FRAME_MAX_SIZE - uhd::usrp::DEVICE3_TX_MAX_HDR_LEN) / - float(X300_DATA_FRAME_MAX_SIZE + 8 /* UDP header */ + 20 /* Ethernet header length */ ))); - -#define X300_RADIO_DEST_PREFIX_TX 0 - -#define X300_XB_DST_E0 0 -#define X300_XB_DST_E1 1 -#define X300_XB_DST_PCI 2 -#define X300_XB_DST_R0 3 // Radio 0 -> Slot A -#define X300_XB_DST_R1 4 // Radio 1 -> Slot B -#define X300_XB_DST_CE0 5 - -#define X300_SRC_ADDR0 0 -#define X300_SRC_ADDR1 1 -#define X300_DST_ADDR 2 - // Ethernet ports enum x300_eth_iface_t { |