diff options
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/eiscat.py | 5 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n310.py | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py index 78dae0c1f..98cea47ce 100644 --- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py @@ -406,7 +406,10 @@ class EISCAT(DboardManagerBase): ",".join(['{}={}'.format(x, args[x]) for x in args]) )) self.log.trace("Getting uio...") - self.radio_regs = UIO(label="jesd204b-regs", read_only=False) + self.radio_regs = UIO( + label="dboard-regs-{}".format(self.slot_idx), + read_only=False + ) # Create JESD cores. They will also test the UIO regs on initialization. self.jesd_cores = [ JesdCoreEiscat( diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index 4663938b6..84a55c9d2 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -106,7 +106,9 @@ class n310(PeriphManagerBase): mboard_info = {"type": "n3xx"} dboard_eeprom_addr = "e0004000.i2c" dboard_eeprom_max_len = 64 - dboard_spimaster_addrs = ["e0006000.spi",] + # We're on a Zynq target, so the following two come from the Zynq standard + # device tree overlay (tree/arch/arm/boot/dts/zynq-7000.dtsi) + dboard_spimaster_addrs = ["e0006000.spi", "e0007000.spi"] chdr_interfaces = ['eth1', 'eth2'] # N310-specific settings eth_tables = {'eth1': 'misc-enet-regs0', 'eth2': 'misc-enet-regs1'} |