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-rw-r--r--images/manifest.txt2
-rw-r--r--mpm/python/usrp_mpm/periph_manager/n310.py14
2 files changed, 14 insertions, 2 deletions
diff --git a/images/manifest.txt b/images/manifest.txt
index 64211b0c6..e3d8686e6 100644
--- a/images/manifest.txt
+++ b/images/manifest.txt
@@ -9,7 +9,7 @@ x3xx_x300_fpga_default fpga-30cc152 x3xx/fpga-30cc152/x3xx_x300_
# E-Series
e3xx_e310_fpga_default fpga-30cc152 e3xx/fpga-30cc152/e3xx_e310_fpga_default.zip c2c996190be6c4ada2e176a0e2b647dfe7a56100cc3c140ca5bc702411747530
# N300-Series
-n3xx_n310_fpga_default fpga-30cc152 n3xx/fpga-30cc152/n3xx_n310_fpga_default.zip ca5667287913f37fe77480b9d309b102d525ff904b4ccfb70455d4ce93595d2c
+n3xx_n310_fpga_default fpga-76daf66 n3xx/fpga-76daf66/n3xx_n310_fpga_default.zip 6d74d9846ec191bb28902be2a21358c6b3190b6b4dd94220e9d8e696fba60e9f
n3xx_n310_fpga_aurora fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_fpga_aurora.zip c5327bb903e0797568e9b773f4d56bae9ce973a3db6e942b8027aa1ac71cf1e1
#n3xx_n310_cpld_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_cpld_default.zip 0
# N3XX Mykonos firmware
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py
index d6c836a9c..cb7d29f35 100644
--- a/mpm/python/usrp_mpm/periph_manager/n310.py
+++ b/mpm/python/usrp_mpm/periph_manager/n310.py
@@ -33,7 +33,7 @@ N3XX_DEFAULT_CLOCK_SOURCE = 'internal'
N3XX_DEFAULT_TIME_SOURCE = 'internal'
N3XX_DEFAULT_ENABLE_GPS = True
N3XX_DEFAULT_ENABLE_FPGPIO = True
-N3XX_FPGA_COMPAT = (4, 0)
+N3XX_FPGA_COMPAT = (5, 0)
N3XX_MONITOR_THREAD_INTERVAL = 1.0 # seconds
###############################################################################
@@ -337,6 +337,18 @@ class N310XportMgrUDP(XportMgrUDP):
xbar_port_map = {'eth1': 0, 'eth2': 1}
xbar_dev = "/dev/crossbar0"
iface_config = {
+ 'sfp0': {
+ 'label': 'misc-enet-regs0',
+ 'xbar': 0,
+ 'xbar_port': 0,
+ 'ctrl_src_addr': 0,
+ },
+ 'sfp1': {
+ 'label': 'misc-enet-regs1',
+ 'xbar': 0,
+ 'xbar_port': 1,
+ 'ctrl_src_addr': 1,
+ },
'eth1': {
'label': 'misc-enet-regs0',
'xbar': 0,