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-rw-r--r--mpm/python/usrp_mpm/cores/nijesdcore.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/cores/nijesdcore.py b/mpm/python/usrp_mpm/cores/nijesdcore.py
index 1cde45619..5d1f4e264 100644
--- a/mpm/python/usrp_mpm/cores/nijesdcore.py
+++ b/mpm/python/usrp_mpm/cores/nijesdcore.py
@@ -50,7 +50,7 @@ class NIMgJESDCore(object):
self.cplls_used = 0
self.rx_lanes = 4
self.tx_lanes = 4
- self.bypass_descrambler = True
+ self.bypass_descrambler = False
self.bypass_scrambler = True
self.lmfc_divider = 20 # Number of FPGA clock cycles per LMFC period.
self.tx_driver_swing = 0b1111 # See UG476, TXDIFFCTRL