diff options
| -rw-r--r-- | usrp2/fifo/dsp_framer36.v | 16 | ||||
| -rw-r--r-- | usrp2/models/IOBUF.v | 83 | ||||
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 2 | ||||
| -rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 9 |
4 files changed, 100 insertions, 10 deletions
diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index c2ae8f96c..58455cee1 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -1,9 +1,13 @@ -// Frame DSP packets with a header line to be handled by the protocol machine +// This has 3 functions: +// Correct the VITA packet length +// [optional] Frame DSP packets with an header line to be handled by the protocol machine +// Hold on to the packet until there is a complete one before allowing to leave module dsp_framer36 #(parameter BUF_SIZE = 9, - parameter PORT_SEL = 0) + parameter PORT_SEL = 0, + parameter PROT_ENG_FLAGS = 1) (input clk, input reset, input clear, input [35:0] data_i, input src_rdy_i, output dst_rdy_o, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); @@ -48,10 +52,10 @@ module dsp_framer36 always @(posedge clk) if(reset | clear) - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else if(do_xfer_out) if(dfifo_out_data[33]) // eof - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else pkt_len_out <= pkt_len_out + 1; @@ -59,8 +63,8 @@ module dsp_framer36 wire [1:0] port_sel_bits = PORT_SEL; - assign data_o = (pkt_len_out == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : - (pkt_len_out == 1) ? {4'b0000, dfifo_out_data[31:16],tfifo_data} : + assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : + (pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} : {dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] }; assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy; diff --git a/usrp2/models/IOBUF.v b/usrp2/models/IOBUF.v new file mode 100644 index 000000000..1195dfb17 --- /dev/null +++ b/usrp2/models/IOBUF.v @@ -0,0 +1,83 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.9 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer +// /___/ /\ Filename : IOBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF (O, IO, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IBUF_DELAY_VALUE = "0"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + inout IO; + input I, T; + + wire ts; + + //tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + end // initial begin + +endmodule + diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 3ec4c2dd2..8e6d74edf 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -136,7 +136,7 @@ module u1e_core .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9)) vita_rx_chain + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp), diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index d7498286d..28955d108 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -2,7 +2,8 @@ module vita_rx_chain #(parameter BASE=0, parameter UNIT=0, - parameter FIFOSIZE=10) + parameter FIFOSIZE=10, + parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, output overrun, @@ -15,7 +16,7 @@ module vita_rx_chain wire [31:0] vrc_debug, vrf_debug; wire [35:0] rx_data_int; - wire rx_src_rdy_int, rx_dst_rdy_in; + wire rx_src_rdy_int, rx_dst_rdy_int; vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), @@ -32,7 +33,9 @@ module vita_rx_chain .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .debug_rx(vrf_debug) ); - dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36 + dsp_framer36 #(.BUF_SIZE(FIFOSIZE), + .PORT_SEL(UNIT), + .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp0_framer36 (.clk(clk), .reset(reset), .clear(clear), .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); |