diff options
64 files changed, 3325 insertions, 215 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs index bc8e4d5bc..383ed97d8 100644 --- a/fpga/usrp2/control_lib/Makefile.srcs +++ b/fpga/usrp2/control_lib/Makefile.srcs @@ -42,4 +42,7 @@ pic.v \ longfifo.v \ shortfifo.v \ medfifo.v \ +nsgpio16LE.v \ +settings_bus_16LE.v \ +atr_controller16.v \ )) diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v new file mode 100644 index 000000000..3d8b5b1e9 --- /dev/null +++ b/fpga/usrp2/control_lib/atr_controller16.v @@ -0,0 +1,60 @@ + +// Automatic transmit/receive switching of control pins to daughterboards +// Store everything in registers for now, but could use a RAM for more +// complex state machines in the future + +module atr_controller16 + (input clk_i, input rst_i, + input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input run_rx, input run_tx, input [31:0] master_time, + output [31:0] ctrl_lines); + + reg [3:0] state; + reg [31:0] atr_ram [0:15]; // DP distributed RAM + + wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]), + (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) }; + + // WB Interface + always @(posedge clk_i) + if(we_i & stb_i & cyc_i) + begin + if(sel_int[3]) + atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8]; + if(sel_int[2]) + atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0]; + if(sel_int[1]) + atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; + if(sel_int[0]) + atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; + end // if (we_i & stb_i & cyc_i) + + always @(posedge clk_i) + dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + + always @(posedge clk_i) + ack_o <= stb_i & cyc_i & ~ack_o; + + // Control side of DP RAM + assign ctrl_lines = atr_ram[state]; + + // Put a more complex state machine with time delays and multiple states here + // if daughterboard requires more complex sequencing + localparam ATR_IDLE = 4'd0; + localparam ATR_TX = 4'd1; + localparam ATR_RX = 4'd2; + localparam ATR_FULL_DUPLEX = 4'd3; + + always @(posedge clk_i) + if(rst_i) + state <= ATR_IDLE; + else + case ({run_rx,run_tx}) + 2'b00 : state <= ATR_IDLE; + 2'b01 : state <= ATR_TX; + 2'b10 : state <= ATR_RX; + 2'b11 : state <= ATR_FULL_DUPLEX; + endcase // case({run_rx,run_tx}) + +endmodule // atr_controller16 diff --git a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v new file mode 100644 index 000000000..1bf03ab6e --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v @@ -0,0 +1,24 @@ + + +module fifo_pacer + (input clk, + input reset, + input [7:0] rate, + input enable, + input src1_rdy_i, output dst1_rdy_o, + output src2_rdy_o, input dst2_rdy_i, + output underrun, overrun); + + wire strobe; + + cic_strober strober (.clock(clk), .reset(reset), .enable(enable), + .rate(rate), .strobe_fast(1), .strobe_slow(strobe)); + + wire all_ready = src1_rdy_i & dst2_rdy_i; + assign dst1_rdy_o = all_ready & strobe; + assign src2_rdy_o = dst1_rdy_o; + + assign underrun = strobe & ~src1_rdy_i; + assign overrun = strobe & ~dst2_rdy_i; + +endmodule // fifo_pacer diff --git a/fpga/usrp2/control_lib/newfifo/packet32_tb.v b/fpga/usrp2/control_lib/newfifo/packet32_tb.v new file mode 100644 index 000000000..82bb09c29 --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet32_tb.v @@ -0,0 +1,27 @@ + + +module packet32_tb(); + + wire [35:0] data; + wire src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet32_tb.vcd"); + initial $dumpvars(0,packet32_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet32_tb diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator.v b/fpga/usrp2/control_lib/newfifo/packet_generator.v new file mode 100644 index 000000000..6e8b45ccd --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_generator.v @@ -0,0 +1,59 @@ + + +module packet_generator + (input clk, input reset, input clear, + output reg [7:0] data_o, output sof_o, output eof_o, + output src_rdy_o, input dst_rdy_i); + + localparam len = 32'd2000; + + reg [31:0] state; + reg [31:0] seq; + wire [31:0] crc_out; + wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); + + + always @(posedge clk) + if(reset | clear) + seq <= 0; + else + if(eof_o & src_rdy_o & dst_rdy_i) + seq <= seq + 1; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_o & dst_rdy_i) + if(state == (len - 1)) + state <= 32'hFFFF_FFFC; + else + state <= state + 1; + + always @* + case(state) + 0 : data_o <= len[7:0]; + 1 : data_o <= len[15:8]; + 2 : data_o <= len[23:16]; + 3 : data_o <= len[31:24]; + 4 : data_o <= seq[7:0]; + 5 : data_o <= seq[15:8]; + 6 : data_o <= seq[23:16]; + 7 : data_o <= seq[31:24]; + 32'hFFFF_FFFC : data_o <= crc_out[31:24]; + 32'hFFFF_FFFD : data_o <= crc_out[23:16]; + 32'hFFFF_FFFE : data_o <= crc_out[15:8]; + 32'hFFFF_FFFF : data_o <= crc_out[7:0]; + default : data_o <= state[7:0]; + endcase // case (state) + + assign src_rdy_o = 1; + assign sof_o = (state == 0); + assign eof_o = (state == 32'hFFFF_FFFF); + + wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; + + crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), + .calc(calc_crc), .crc_out(crc_out), .match()); + +endmodule // packet_generator diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator32.v b/fpga/usrp2/control_lib/newfifo/packet_generator32.v new file mode 100644 index 000000000..6f8004964 --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_generator32.v @@ -0,0 +1,21 @@ + + +module packet_generator32 + (input clk, input reset, input clear, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + wire [7:0] ll_data; + wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n; + + packet_generator pkt_gen + (.clk(clk), .reset(reset), .clear(clear), + .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), + .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); + + ll8_to_fifo36 ll8_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof), + .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n), + .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i)); + +endmodule // packet_generator32 diff --git a/fpga/usrp2/control_lib/newfifo/packet_tb.v b/fpga/usrp2/control_lib/newfifo/packet_tb.v new file mode 100644 index 000000000..3c423d2ba --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_tb.v @@ -0,0 +1,29 @@ + + +module packet_tb(); + + wire [7:0] data; + wire sof, eof, src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet_tb.vcd"); + initial $dumpvars(0,packet_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .sof_o(sof), .eof_o(eof), + .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .sof_i(sof), .eof_i(eof), + .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_tb diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier.v b/fpga/usrp2/control_lib/newfifo/packet_verifier.v new file mode 100644 index 000000000..b49ad1bbb --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_verifier.v @@ -0,0 +1,61 @@ + + +// Packet format -- +// Line 1 -- Length, 32 bits +// Line 2 -- Sequence number, 32 bits +// Last line -- CRC, 32 bits + +module packet_verifier + (input clk, input reset, input clear, + input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o, + + output reg [31:0] total, + output reg [31:0] crc_err, + output reg [31:0] seq_err, + output reg [31:0] len_err); + + reg [31:0] seq_num; + reg [31:0] length; + wire first_byte, last_byte; + reg second_byte, last_byte_d1; + + wire calc_crc = src_rdy_i & dst_rdy_o; + + crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), + .calc(calc_crc), .crc_out(), .match(match_crc)); + + assign first_byte = src_rdy_i & dst_rdy_o & sof_i; + assign last_byte = src_rdy_i & dst_rdy_o & eof_i; + assign dst_rdy_o = ~last_byte_d1; + + // stubs for now + wire match_seq = 1; + wire match_len = 1; + + always @(posedge clk) + if(reset | clear) + last_byte_d1 <= 0; + else + last_byte_d1 <= last_byte; + + always @(posedge clk) + if(reset | clear) + begin + total <= 0; + crc_err <= 0; + seq_err <= 0; + len_err <= 0; + end + else + if(last_byte_d1) + begin + total <= total + 1; + if(~match_crc) + crc_err <= crc_err + 1; + else if(~match_seq) + seq_err <= seq_err + 1; + else if(~match_len) + seq_err <= len_err + 1; + end + +endmodule // packet_verifier diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier32.v b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v new file mode 100644 index 000000000..06a13d242 --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v @@ -0,0 +1,30 @@ + + +module packet_verifier32 + (input clk, input reset, input clear, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); + + wire [7:0] ll_data; + wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_short #(.WIDTH(36)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + + fifo36_to_ll8 f36_to_ll8 + (.clk(clk), .reset(reset), .clear(clear), + .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), + .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); + + packet_verifier pkt_ver + (.clk(clk), .reset(reset), .clear(clear), + .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), + .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_verifier32 diff --git a/fpga/usrp2/control_lib/nsgpio16LE.v b/fpga/usrp2/control_lib/nsgpio16LE.v new file mode 100644 index 000000000..8aef0c7ae --- /dev/null +++ b/fpga/usrp2/control_lib/nsgpio16LE.v @@ -0,0 +1,123 @@ +// Modified from code originally by Richard Herveille, his copyright is below + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple General Purpose IO core //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +module nsgpio16LE + (input clk_i, input rst_i, + input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, + output reg [15:0] dat_o, output reg ack_o, + input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, + inout [31:0] gpio + ); + + reg [31:0] ctrl, line, ddr, dbg, lgpio; + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + begin + ctrl <= 32'h0; + line <= 32'h0; + ddr <= 32'h0; + dbg <= 32'h0; + end + else if (wb_wr) + case( adr_i[3:1] ) + 3'b000 : + line[15:0] <= dat_i; + 3'b001 : + line[31:16] <= dat_i; + 3'b010 : + ddr[15:0] <= dat_i; + 3'b011 : + ddr[31:16] <= dat_i; + 3'b100 : + ctrl[15:0] <= dat_i; + 3'b101 : + ctrl[31:16] <= dat_i; + 3'b110 : + dbg[15:0] <= dat_i; + 3'b111 : + dbg[31:16] <= dat_i; + endcase // case ( adr_i[3:1] ) + + always @(posedge clk_i) + case (adr_i[3:1]) + 3'b000 : + dat_o <= lgpio[15:0]; + 3'b001 : + dat_o <= lgpio[31:16]; + 3'b010 : + dat_o <= ddr[15:0]; + 3'b011 : + dat_o <= ddr[31:16]; + 3'b100 : + dat_o <= ctrl[15:0]; + 3'b101 : + dat_o <= ctrl[31:16]; + 3'b110 : + dat_o <= dbg[15:0]; + 3'b111 : + dat_o <= dbg[31:16]; + endcase // case (adr_i[3:1]) + + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= wb_acc & !ack_o; + + // latch GPIO input pins + always @(posedge clk_i) + lgpio <= gpio; + + // assign GPIO outputs + integer n; + reg [31:0] igpio; // temporary internal signal + + always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg) + for(n=0;n<32;n=n+1) + igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : + (ctrl[n] ? atr[n] : line[n]) ) + : 1'bz; + + assign gpio = igpio; + +endmodule + diff --git a/fpga/usrp2/control_lib/ram_2port_mixed_width.v b/fpga/usrp2/control_lib/ram_2port_mixed_width.v new file mode 100644 index 000000000..fae7d8de3 --- /dev/null +++ b/fpga/usrp2/control_lib/ram_2port_mixed_width.v @@ -0,0 +1,120 @@ + +module ram_2port_mixed_width + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output [15:0] do16, + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output [31:0] do32); + + wire en32a = en32 & ~addr32[9]; + wire en32b = en32 & addr32[9]; + wire en16a = en16 & ~addr16[10]; + wire en16b = en16 & addr16[10]; + + wire [31:0] do32a, do32b; + wire [15:0] do16a, do16b; + + assign do32 = addr32[9] ? do32b : do32a; + assign do16 = addr16[10] ? do16b : do16a; + + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output + .DOB(do16a), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32a), // Port A 1-bit RAM Enable Input + .ENB(en16a), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output + .DOB(do16b), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32b), // Port A 1-bit RAM Enable Input + .ENB(en16b), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + +endmodule // ram_2port_mixed_width + + + + +// ISE 10.1.03 chokes on the following + +/* + + reg [31:0] ram [(1<<AWIDTH)-1:0]; + integer i; + initial + for(i=0;i<512;i=i+1) + ram[i] <= 32'b0; + + always @(posedge clk16) + if (en16) + begin + if (we16) + if(addr16[0]) + ram[addr16[10:1]][15:0] <= di16; + else + ram[addr16[10:1]][31:16] <= di16; + do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16]; + end + + always @(posedge clk32) + if (en32) + begin + if (we32) + ram[addr32] <= di32; + do32 <= ram[addr32]; + end + +endmodule // ram_2port_mixed_width + + + */ diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v index fc960e456..aec179516 100644 --- a/fpga/usrp2/control_lib/settings_bus.v +++ b/fpga/usrp2/control_lib/settings_bus.v @@ -10,7 +10,7 @@ module settings_bus input wb_stb_i, input wb_we_i, output reg wb_ack_o, - output strobe, + output reg strobe, output reg [7:0] addr, output reg [31:0] data); @@ -19,18 +19,18 @@ module settings_bus always @(posedge wb_clk) if(wb_rst) begin - stb_int <= 1'b0; + strobe <= 1'b0; addr <= 8'd0; data <= 32'd0; end - else if(wb_we_i & wb_stb_i) + else if(wb_we_i & wb_stb_i & ~wb_ack_o) begin - stb_int <= 1'b1; + strobe <= 1'b1; addr <= wb_adr_i[9:2]; data <= wb_dat_i; end else - stb_int <= 1'b0; + strobe <= 1'b0; always @(posedge wb_clk) if(wb_rst) @@ -38,11 +38,4 @@ module settings_bus else wb_ack_o <= wb_stb_i & ~wb_ack_o; - always @(posedge wb_clk) - stb_int_d1 <= stb_int; - - //assign strobe = stb_int & ~stb_int_d1; - assign strobe = stb_int & wb_ack_o; - endmodule // settings_bus - diff --git a/fpga/usrp2/control_lib/settings_bus_16LE.v b/fpga/usrp2/control_lib/settings_bus_16LE.v new file mode 100644 index 000000000..76061e9e0 --- /dev/null +++ b/fpga/usrp2/control_lib/settings_bus_16LE.v @@ -0,0 +1,54 @@ + +// Grab settings off the wishbone bus, send them out to settings bus +// 16 bits little endian, but all registers need to be written 32 bits at a time. +// This means that you write the low 16 bits first and then the high 16 bits. +// The setting regs are strobed when the high 16 bits are written + +module settings_bus_16LE + #(parameter AWIDTH=16, RWIDTH=8) + (input wb_clk, + input wb_rst, + input [AWIDTH-1:0] wb_adr_i, + input [15:0] wb_dat_i, + input wb_stb_i, + input wb_we_i, + output reg wb_ack_o, + output strobe, + output reg [7:0] addr, + output reg [31:0] data); + + reg stb_int; + + always @(posedge wb_clk) + if(wb_rst) + begin + stb_int <= 1'b0; + addr <= 8'd0; + data <= 32'd0; + end + else if(wb_we_i & wb_stb_i) + begin + addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits + if(wb_adr_i[1]) + begin + stb_int <= 1'b1; // We now have both halves + data[31:16] <= wb_dat_i; + end + else + begin + stb_int <= 1'b0; // Don't strobe, we need other half + data[15:0] <= wb_dat_i; + end + end + else + stb_int <= 1'b0; + + always @(posedge wb_clk) + if(wb_rst) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + assign strobe = stb_int & wb_ack_o; + +endmodule // settings_bus_16LE diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v index 22f0e70a2..0dd58b5f5 100644 --- a/fpga/usrp2/control_lib/simple_uart.v +++ b/fpga/usrp2/control_lib/simple_uart.v @@ -1,11 +1,12 @@ module simple_uart #(parameter TXDEPTH = 1, - parameter RXDEPTH = 1) - (input clk_i, input rst_i, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, - output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); + parameter RXDEPTH = 1, + parameter CLKDIV_DEFAULT = 16'd0) + (input clk_i, input rst_i, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, + output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); // Register Map localparam SUART_CLKDIV = 0; @@ -30,7 +31,7 @@ module simple_uart always @(posedge clk_i) if (rst_i) - clkdiv <= 0; + clkdiv <= CLKDIV_DEFAULT; else if (wb_wr) case(adr_i) SUART_CLKDIV : clkdiv <= dat_i[15:0]; diff --git a/fpga/usrp2/fifo/.gitignore b/fpga/usrp2/fifo/.gitignore index cba7efc8e..866f1faad 100644 --- a/fpga/usrp2/fifo/.gitignore +++ b/fpga/usrp2/fifo/.gitignore @@ -1 +1,3 @@ +*.vcd +*.lxt a.out diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v index 5f9aeff9b..0e6bcea68 100644 --- a/fpga/usrp2/fifo/fifo19_to_fifo36.v +++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v @@ -1,26 +1,31 @@ +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. + module fifo19_to_fifo36 - (input clk, input reset, input clear, - input [18:0] f19_datain, - input f19_src_rdy_i, - output f19_dst_rdy_o, + #(parameter LE=0) + (input clk, input reset, input clear, + input [18:0] f19_datain, + input f19_src_rdy_i, + output f19_dst_rdy_o, - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i, - output [31:0] debug - ); + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i, + output [31:0] debug + ); - reg f36_sof, f36_eof, f36_occ; + reg f36_sof, f36_eof, f36_occ; - reg [1:0] state; - reg [15:0] dat0, dat1; + reg [1:0] state; + reg [15:0] dat0, dat1; - wire f19_sof = f19_datain[16]; - wire f19_eof = f19_datain[17]; - wire f19_occ = f19_datain[18]; + wire f19_sof = f19_datain[16]; + wire f19_eof = f19_datain[17]; + wire f19_occ = f19_datain[18]; - wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; always @(posedge clk) if(f19_src_rdy_i & ((state==0)|xfer_out)) @@ -68,7 +73,8 @@ module fifo19_to_fifo36 dat0 <= f19_datain; assign f19_dst_rdy_o = xfer_out | (state != 2); - assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; + assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : + {f36_occ,f36_eof,f36_sof,dat0,dat1}; assign f36_src_rdy_o = (state == 2); assign debug = state; diff --git a/fpga/usrp2/fifo/fifo36_to_fifo18.v b/fpga/usrp2/fifo/fifo36_to_fifo18.v deleted file mode 100644 index b636ab9ca..000000000 --- a/fpga/usrp2/fifo/fifo36_to_fifo18.v +++ /dev/null @@ -1,40 +0,0 @@ - -module fifo36_to_fifo18 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [17:0] f18_dataout, - output f18_src_rdy_o, - input f18_dst_rdy_i ); - - wire f36_sof = f36_datain[32]; - wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - - assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; - assign f18_dataout[16] = phase ? 0 : f36_sof; - assign f18_dataout[17] = phase ? f36_eof : half_line; - - assign f18_src_rdy_o = f36_src_rdy_i; - assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i; - - wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f36_xfer) - phase <= 0; - else if(f18_xfer) - phase <= 1; - - -endmodule // fifo36_to_fifo18 - diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v index de249aaeb..517a2a476 100644 --- a/fpga/usrp2/fifo/fifo36_to_fifo19.v +++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v @@ -1,33 +1,38 @@ -module fifo36_to_fifo19 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [18:0] f19_dataout, - output f19_src_rdy_o, - input f19_dst_rdy_i ); +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. +module fifo36_to_fifo19 + #(parameter LE=0) + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + wire f36_sof = f36_datain[32]; wire f36_eof = f36_datain[33]; wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16]; assign f19_dataout[16] = phase ? 0 : f36_sof; assign f19_dataout[17] = phase ? f36_eof : half_line; assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); assign f19_src_rdy_o = f36_src_rdy_i; assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; - - wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + always @(posedge clk) if(reset) phase <= 0; @@ -36,6 +41,5 @@ module fifo36_to_fifo19 else if(f19_xfer) phase <= 1; - + endmodule // fifo36_to_fifo19 - diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v index 0dee1dfc6..9604d0e38 100644 --- a/fpga/usrp2/fifo/fifo36_to_ll8.v +++ b/fpga/usrp2/fifo/fifo36_to_ll8.v @@ -55,6 +55,5 @@ module fifo36_to_ll8 assign advance = ll_src_rdy & ll_dst_rdy; assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); - assign debug = state; endmodule // ll8_to_fifo36 diff --git a/fpga/usrp2/gpmc/.gitignore b/fpga/usrp2/gpmc/.gitignore new file mode 100644 index 000000000..3e14fa4f7 --- /dev/null +++ b/fpga/usrp2/gpmc/.gitignore @@ -0,0 +1,2 @@ +*.gif + diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs new file mode 100644 index 000000000..bff6ae3e0 --- /dev/null +++ b/fpga/usrp2/gpmc/Makefile.srcs @@ -0,0 +1,20 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# SERDES Sources +################################################## +GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \ +dbsm.v \ +edge_sync.v \ +fifo_to_gpmc_async.v \ +fifo_to_gpmc_sync.v \ +fifo_watcher.v \ +gpmc_async.v \ +gpmc_sync.v \ +gpmc_to_fifo_async.v \ +gpmc_to_fifo_sync.v \ +gpmc_wb.v \ +ram_to_fifo.v \ +)) diff --git a/fpga/usrp2/gpmc/burst_data_write.txt b/fpga/usrp2/gpmc/burst_data_write.txt new file mode 100644 index 000000000..3b5dfc785 --- /dev/null +++ b/fpga/usrp2/gpmc/burst_data_write.txt @@ -0,0 +1,16 @@ +# OMAP burst writes to FPGA + +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA1. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA2. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA3. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA4. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/fpga/usrp2/gpmc/dbsm.v b/fpga/usrp2/gpmc/dbsm.v new file mode 100644 index 000000000..530af7205 --- /dev/null +++ b/fpga/usrp2/gpmc/dbsm.v @@ -0,0 +1,80 @@ + +module bsm + (input clk, input reset, input clear, + input write_done, + input read_done, + output readable, + output writeable); + + reg state; + localparam ST_WRITEABLE = 0; + localparam ST_READABLE = 1; + + always @(posedge clk) + if(reset | clear) + state <= ST_WRITEABLE; + else + case(state) + ST_WRITEABLE : + if(write_done) + state <= ST_READABLE; + ST_READABLE : + if(read_done) + state <= ST_WRITEABLE; + endcase // case (state) + + assign readable = (state == ST_READABLE); + assign writeable = (state == ST_WRITEABLE); + +endmodule // bsm + +module dbsm + (input clk, input reset, input clear, + output reg read_sel, output read_ready, input read_done, + output reg write_sel, output write_ready, input write_done); + + localparam NUM_BUFS = 2; + + wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf; + + // Two of these buffer state machines + genvar i; + generate + for(i=0;i<NUM_BUFS;i=i+1) + begin : BSMS + bsm bsm(.clk(clk), .reset(reset), .clear(clear), + .write_done((write_sel == i) & write_done), + .read_done((read_sel == i) & read_done), + .readable(readable[i]), .writeable(writeable[i])); + end + endgenerate + + reg full; + + always @(posedge clk) + if(reset | clear) + begin + write_sel <= 0; + full <= 0; + end + else + if(write_done & writeable[write_sel]) + if(write_sel ==(NUM_BUFS-1)) + write_sel <= 0; + else + write_sel <= write_sel + 1; + + always @(posedge clk) + if(reset | clear) + read_sel <= 0; + else + if(read_done & readable[read_sel]) + if(read_sel==(NUM_BUFS-1)) + read_sel <= 0; + else + read_sel <= read_sel + 1; + + assign write_ready = writeable[write_sel]; + assign read_ready = readable[read_sel]; + +endmodule // dbsm diff --git a/fpga/usrp2/gpmc/edge_sync.v b/fpga/usrp2/gpmc/edge_sync.v new file mode 100644 index 000000000..5d9417c08 --- /dev/null +++ b/fpga/usrp2/gpmc/edge_sync.v @@ -0,0 +1,22 @@ + + +module edge_sync + #(parameter POSEDGE = 1) + (input clk, + input rst, + input sig, + output trig); + + reg [1:0] delay; + + always @(posedge clk) + if(rst) + delay <= 2'b00; + else + delay <= {delay[0],sig}; + + assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10); + +endmodule // edge_sync + + diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v new file mode 100644 index 000000000..cf8b6e861 --- /dev/null +++ b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v @@ -0,0 +1,37 @@ + +// Assumes an asynchronous GPMC cycle +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_async + (input clk, input reset, input clear, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + output [15:0] EM_D, input EM_NCS, input EM_NOE, + input [15:0] frame_len); + + // Synchronize the async control signals + reg [2:0] cs_del, oe_del; + reg [15:0] counter; + + always @(posedge clk) + if(reset) + begin + cs_del <= 3'b11; + oe_del <= 3'b11; + end + else + begin + cs_del <= { cs_del[1:0], EM_NCS }; + oe_del <= { oe_del[1:0], EM_NOE }; + end + + wire do_read = ( (~cs_del[1] | ~cs_del[2]) & (oe_del[1:0] == 2'b01)); // change output on trailing edge + wire first_read = (counter == 0); + wire last_read = ((counter+1) == frame_len); + + assign EM_D = data_i[15:0]; + + assign dst_rdy_o = do_read; + +endmodule // fifo_to_gpmc_async diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v new file mode 100644 index 000000000..ef59d7137 --- /dev/null +++ b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -0,0 +1,26 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_sync + (input arst, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + input EM_CLK, output [15:0] EM_D, input EM_NCS, input EM_NOE, + output fifo_ready, + output reg bus_error); + + assign EM_D = data_i[15:0]; + wire read_access = ~EM_NCS & ~EM_NOE; + + assign dst_rdy_o = read_access; + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(dst_rdy_o & ~src_rdy_i) + bus_error <= 1; + + +endmodule // fifo_to_gpmc_sync diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v new file mode 100644 index 000000000..fe4e35de3 --- /dev/null +++ b/fpga/usrp2/gpmc/fifo_watcher.v @@ -0,0 +1,56 @@ + + +module fifo_watcher + (input clk, input reset, input clear, + input src_rdy1, input dst_rdy1, input sof1, input eof1, + input src_rdy2, input dst_rdy2, input sof2, input eof2, + output reg have_packet, output [15:0] length, output reg bus_error, + output [31:0] debug); + + wire write = src_rdy1 & dst_rdy1 & eof1; + wire read = src_rdy2 & dst_rdy2 & eof2; + wire have_packet_int; + reg [15:0] counter; + wire [4:0] pkt_count; + assign debug = pkt_count; + + fifo_short #(.WIDTH(16)) frame_lengths + (.clk(clk), .reset(reset), .clear(clear), + .datain(counter), .src_rdy_i(write), .dst_rdy_o(), + .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read), + .occupied(pkt_count), .space()); + + always @(posedge clk) + if(reset | clear) + counter <= 1; // Start at 1 + else if(src_rdy1 & dst_rdy1) + if(eof1) + counter <= 1; + else + counter <= counter + 1; + + always @(posedge clk) + if(reset | clear) + bus_error <= 0; + else if(dst_rdy2 & ~src_rdy2) + bus_error <= 1; + else if(read & ~have_packet_int) + bus_error <= 1; + + reg in_packet; + always @(posedge clk) + if(reset | clear) + have_packet <= 0; + else + have_packet <= (have_packet_int & ~in_packet) | (pkt_count>1) ; + + always @(posedge clk) + if(reset | clear) + in_packet <= 0; + else if(src_rdy2 & dst_rdy2) + if(eof2) + in_packet <= 0; + else + in_packet <= 1; + +endmodule // fifo_watcher diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v new file mode 100644 index 000000000..23bad56ae --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_async.v @@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc_async + #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + input [15:0] tx_frame_len, output [15:0] rx_frame_len, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + + always @(posedge fifo_clk) + if(fifo_rst | clear_tx | clear_rx) + bus_error <= 0; + else + bus_error <= bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space; + wire [35:0] tx36_data; + wire tx36_src_rdy, tx36_dst_rdy; + + gpmc_to_fifo_async gpmc_to_fifo_async + (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space; + wire [35:0] rx36_data; + wire rx36_src_rdy, rx36_dst_rdy; + wire dummy; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + + fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); + + fifo_to_gpmc_async fifo_to_gpmc_async + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .frame_len(rx_frame_len) ); + + wire [31:0] pkt_count; + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), + .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), + .debug(pkt_count)); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = pkt_count; + +endmodule // gpmc_async diff --git a/fpga/usrp2/gpmc/gpmc_sync.v b/fpga/usrp2/gpmc/gpmc_sync.v new file mode 100644 index 000000000..61c54a793 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_sync.v @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc_sync + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + assign bus_error = bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + + assign tx_frame_len = 10; + + gpmc_to_fifo_sync gpmc_to_fifo_sync + (.arst(arst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) tx_fifo + (.wclk(EM_CLK), .datain(tx18_data), + .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .rclk(fifo_clk), .dataout(tx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; + wire dummy; + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.wclk(fifo_clk), .datain(rx18_data), + .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .rclk(EM_CLK), .dataout(rx18b_data), + .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo_to_gpmc_sync fifo_to_gpmc_sync + (.arst(arst), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .fifo_ready(rx_have_data) ); + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), + .have_packet(), .length(), .next() ); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = 0; + +endmodule // gpmc_sync diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_async.v b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v new file mode 100644 index 000000000..55c0cef50 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v @@ -0,0 +1,68 @@ + +module gpmc_to_fifo_async + (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, + + input fifo_clk, input fifo_rst, input clear, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + + input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready, + output reg bus_error ); + + reg [15:0] counter; + // Synchronize the async control signals + reg [1:0] cs_del, we_del; + always @(posedge fifo_clk) + if(fifo_rst) + begin + cs_del <= 2'b11; + we_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + end + + wire do_write = (~cs_del[0] & (we_del == 2'b10)); + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + + always @(posedge fifo_clk) + if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge fifo_clk) + if(fifo_rst | clear) + src_rdy_o <= 0; + else if(do_write) + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken + + always @(posedge fifo_clk) + if(fifo_rst | clear) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + always @(posedge fifo_clk) + if(fifo_rst | clear) + fifo_ready <= 0; + else + fifo_ready <= /* first_write & */ (fifo_space > 16'd1023); + + always @(posedge fifo_clk) + if(fifo_rst | clear) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + +endmodule // gpmc_to_fifo_async diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v new file mode 100644 index 000000000..688de0e17 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v @@ -0,0 +1,57 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module gpmc_to_fifo_sync + (input arst, + input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + output reg bus_error); + + reg [10:0] counter; + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + wire do_write = ~EM_NCS & ~EM_NWE; + + always @(posedge EM_CLK or posedge arst) + if(arst) + data_o <= 0; + else if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge EM_CLK or posedge arst) + if(arst) + src_rdy_o <= 0; + else if(do_write & ~bus_error) // Don't put junk in if there is a bus error + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + + always @(posedge EM_CLK or posedge arst) + if(arst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + // must be reset to make the error go away + +endmodule // gpmc_to_fifo_sync diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v new file mode 100644 index 000000000..db6fbc6e9 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_wb.v @@ -0,0 +1,57 @@ + + +module gpmc_wb + (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, input EM_NOE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i); + + // //////////////////////////////////////////// + // Control Path, Wishbone bus bridge (wb master) + reg [1:0] cs_del, we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + oe_del <= { oe_del[0], EM_NOE }; + end + + always @(posedge wb_clk) + if(cs_del == 2'b10) // Falling Edge + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(we_del == 2'b10) // Falling Edge + begin + wb_dat_mosi <= EM_D_in; + wb_sel_o <= ~EM_NBE; + end + + reg [15:0] EM_D_hold; + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_hold <= wb_dat_miso; + + assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold; + + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if(~cs_del[0] & (we_del == 2'b10) ) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + // FIXME should this look at cs_del[1]? + always @(posedge wb_clk) + if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc_wb diff --git a/fpga/usrp2/gpmc/make_timing_diag b/fpga/usrp2/gpmc/make_timing_diag new file mode 100755 index 000000000..03166ad35 --- /dev/null +++ b/fpga/usrp2/gpmc/make_timing_diag @@ -0,0 +1,6 @@ +#!/bin/sh +drawtiming -o single_data_write.gif single_data_write.txt +drawtiming -o single_data_read.gif single_data_read.txt +drawtiming -o burst_data_write.gif burst_data_write.txt +#drawtiming -o burst_data_read.gif burst_data_read.txt + diff --git a/fpga/usrp2/gpmc/ram_to_fifo.v b/fpga/usrp2/gpmc/ram_to_fifo.v new file mode 100644 index 000000000..8549dcc35 --- /dev/null +++ b/fpga/usrp2/gpmc/ram_to_fifo.v @@ -0,0 +1,46 @@ + + +module ram_to_fifo + (input clk, input reset, + input [10:0] read_length, // From the dbsm (?) + output read_en, output reg [8:0] read_addr, input [31:0] read_data, input read_ready, output read_done, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + // read_length/2 = number of 32 bit lines, numbered 0 through read_length/2-1 + wire [8:0] last_line = (read_length[10:1]-1); + + reg read_phase, sop; + + assign read_en = (read_phase == 0) | dst_rdy_i; + assign src_rdy_o = (read_phase == 1); + + always @(posedge clk) + if(reset) + begin + read_addr <= 0; + read_phase <= 0; + sop <= 1; + end + else + if(read_phase == 0) + begin + read_addr <= read_ready; + read_phase <= read_ready; + end + else if(dst_rdy_i) + begin + sop <= 0; + if(read_addr == last_line) + begin + read_addr <= 0; + read_phase <= 0; + end + else + read_addr <= read_addr + 1; + end + + assign read_done = (read_phase == 1) & (read_addr == last_line) & dst_rdy_i; + wire eop = (read_addr == last_line); + assign data_o = { 2'b00, eop, sop, read_data }; + +endmodule // ram_to_fifo diff --git a/fpga/usrp2/gpmc/single_data_read.txt b/fpga/usrp2/gpmc/single_data_read.txt new file mode 100644 index 000000000..1dc0e3a78 --- /dev/null +++ b/fpga/usrp2/gpmc/single_data_read.txt @@ -0,0 +1,12 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nOE=0,nCS=0,DATA=RD_DATA. +CLK=1. +CLK=0. +CLK=1. +CLK=0,nOE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/fpga/usrp2/gpmc/single_data_write.txt b/fpga/usrp2/gpmc/single_data_write.txt new file mode 100644 index 000000000..287e3e2c1 --- /dev/null +++ b/fpga/usrp2/gpmc/single_data_write.txt @@ -0,0 +1,10 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/fpga/usrp2/models/gpmc_model_async.v b/fpga/usrp2/models/gpmc_model_async.v new file mode 100644 index 000000000..beeaee028 --- /dev/null +++ b/fpga/usrp2/models/gpmc_model_async.v @@ -0,0 +1,130 @@ +`timescale 1ps/1ps + +module gpmc_model_async + (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + assign EM_CLK = 0; + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + #23000; + EM_A <= addr[10:1]; + EM_D_int <= data; + #20100; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14000; + EM_NWE <= 0; + #77500; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + EM_NWE <= 1; + #60000; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #13000; + EM_A <= addr[10:1]; + #3000; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14000; + EM_NOE <= 0; + #77500; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254000; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000000; + GPMC_Write(1,36,16'hF00D); + #1000000; + GPMC_Read(1,36); + #1000000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + #1000000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'h9876); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + #1000000; + GPMC_Read(0,0); + #100000000; + $finish; + end + +endmodule // gpmc_model_async diff --git a/fpga/usrp2/models/gpmc_model_sync.v b/fpga/usrp2/models/gpmc_model_sync.v new file mode 100644 index 000000000..641720c15 --- /dev/null +++ b/fpga/usrp2/models/gpmc_model_sync.v @@ -0,0 +1,97 @@ + + +module gpmc_model_sync + (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_CLK <= 0; + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 0; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + EM_A <= addr[10:1]; + EM_D_int <= data; + #10; + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + #100; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #1.3; + EM_A <= addr[10:1]; + #3; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NOE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(1,36,16'hF00D); + #1000; + GPMC_Read(1,36); + #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + #100000; + $finish; + end + +endmodule // gpmc_model diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs index 30360a17d..1ccecf337 100644 --- a/fpga/usrp2/opencores/Makefile.srcs +++ b/fpga/usrp2/opencores/Makefile.srcs @@ -23,6 +23,5 @@ i2c/rtl/verilog/timescale.v \ spi/rtl/verilog/spi_clgen.v \ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ -spi/rtl/verilog/spi_top.v \ -spi/rtl/verilog/timescale.v \ +spi/rtl/verilog/spi_top16.v \ )) diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v index 7bc4f6e5e..2d9c34f40 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v @@ -39,12 +39,9 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); - parameter Tp = 1; - input clk_in; // input clock (system clock) input rst; // reset input enable; // clock enable @@ -68,40 +65,40 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; // Counter counts half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) - cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}}; + cnt <= {`SPI_DIVIDER_LEN{1'b1}}; else begin if(!enable || cnt_zero) - cnt <= #Tp divider; + cnt <= divider; else - cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; end end // clk_out is asserted every other half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) - clk_out <= #Tp 1'b0; + clk_out <= 1'b0; else - clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; end // Pos and neg edge signals - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) begin - pos_edge <= #Tp 1'b0; - neg_edge <= #Tp 1'b0; + pos_edge <= 1'b0; + neg_edge <= 1'b0; end else begin - pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); - neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); end end endmodule diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v index a6925918e..963a680a8 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -43,8 +43,8 @@ // low frequency of system clock this can be reduced. // Use SPI_DIVIDER_LEN for fine tuning theexact number. // -//`define SPI_DIVIDER_LEN_8 -`define SPI_DIVIDER_LEN_16 +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 //`define SPI_DIVIDER_LEN_24 //`define SPI_DIVIDER_LEN_32 @@ -66,9 +66,9 @@ // Use SPI_MAX_CHAR for fine tuning the exact number, when using // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. // -`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_128 //`define SPI_MAX_CHAR_64 -//`define SPI_MAX_CHAR_32 +`define SPI_MAX_CHAR_32 //`define SPI_MAX_CHAR_24 //`define SPI_MAX_CHAR_16 //`define SPI_MAX_CHAR_8 @@ -137,7 +137,7 @@ `define SPI_TX_2 2 `define SPI_TX_3 3 `define SPI_CTRL 4 -`define SPI_DEVIDE 5 +`define SPI_DIVIDE 5 `define SPI_SS 6 // diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v index b17ac8b1f..ac3bb3f48 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v @@ -39,15 +39,12 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, pos_edge, neg_edge, rx_negedge, tx_negedge, tip, last, p_in, p_out, s_clk, s_in, s_out); - parameter Tp = 1; - input clk; // system clock input rst; // reset input [3:0] latch; // latch signal for storing the data in shift register @@ -89,149 +86,149 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; // Character bit counter - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) - cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}}; else begin if(tip) - cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; else - cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; end end // Transfer in progress - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) - tip <= #Tp 1'b0; + tip <= 1'b0; else if(go && ~tip) - tip <= #Tp 1'b1; + tip <= 1'b1; else if(tip && last && pos_edge) - tip <= #Tp 1'b0; + tip <= 1'b0; end // Sending bits to the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) - s_out <= #Tp 1'b0; + s_out <= 1'b0; else - s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; end // Receiving bits from the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) - data <= #Tp {`SPI_MAX_CHAR{1'b0}}; + data <= {`SPI_MAX_CHAR{1'b0}}; `ifdef SPI_MAX_CHAR_128 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end else if (latch[2] && !tip) begin if (byte_sel[3]) - data[95:88] <= #Tp p_in[31:24]; + data[95:88] <= p_in[31:24]; if (byte_sel[2]) - data[87:80] <= #Tp p_in[23:16]; + data[87:80] <= p_in[23:16]; if (byte_sel[1]) - data[79:72] <= #Tp p_in[15:8]; + data[79:72] <= p_in[15:8]; if (byte_sel[0]) - data[71:64] <= #Tp p_in[7:0]; + data[71:64] <= p_in[7:0]; end else if (latch[3] && !tip) begin if (byte_sel[3]) - data[127:120] <= #Tp p_in[31:24]; + data[127:120] <= p_in[31:24]; if (byte_sel[2]) - data[119:112] <= #Tp p_in[23:16]; + data[119:112] <= p_in[23:16]; if (byte_sel[1]) - data[111:104] <= #Tp p_in[15:8]; + data[111:104] <= p_in[15:8]; if (byte_sel[0]) - data[103:96] <= #Tp p_in[7:0]; + data[103:96] <= p_in[7:0]; end `else `ifdef SPI_MAX_CHAR_64 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end `else else if (latch[0] && !tip) begin `ifdef SPI_MAX_CHAR_8 if (byte_sel[0]) - data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0]; + data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0]; `endif `ifdef SPI_MAX_CHAR_16 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8]; + data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8]; `endif `ifdef SPI_MAX_CHAR_24 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16]; + data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16]; `endif `ifdef SPI_MAX_CHAR_32 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[3]) - data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24]; + data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24]; `endif end `endif `endif else - data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; end endmodule diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v index 09b2e50e1..8289449a9 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v @@ -1,3 +1,6 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style + ////////////////////////////////////////////////////////////////////// //// //// //// spi_top.v //// @@ -40,7 +43,6 @@ `include "spi_defines.v" -`include "timescale.v" module spi_top ( @@ -52,8 +54,6 @@ module spi_top ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i ); - parameter Tp = 1; - // Wishbone signals input wb_clk_i; // master clock input input wb_rst_i; // synchronous active high reset @@ -101,7 +101,7 @@ module spi_top wire last_bit; // marks last character bit // Address decoder - assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE); assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); @@ -132,96 +132,96 @@ module spi_top `endif `endif `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; - `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; + `SPI_DIVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; default: wb_dat = 32'bx; endcase end // Wb data out - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - wb_dat_o <= #Tp 32'b0; + wb_dat_o <= 32'b0; else - wb_dat_o <= #Tp wb_dat; + wb_dat_o <= wb_dat; end // Wb acknowledge - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - wb_ack_o <= #Tp 1'b0; + wb_ack_o <= 1'b0; else - wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; end // Wb error assign wb_err_o = 1'b0; // Interrupt - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; else if (ie && tip && last_bit && pos_edge) - wb_int_o <= #Tp 1'b1; + wb_int_o <= 1'b1; else if (wb_ack_o) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; end // Divider register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; + divider <= {`SPI_DIVIDER_LEN{1'b0}}; else if (spi_divider_sel && wb_we_i && !tip) begin `ifdef SPI_DIVIDER_LEN_8 if (wb_sel_i[0]) - divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; + divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0]; `endif `ifdef SPI_DIVIDER_LEN_16 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; + divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8]; `endif `ifdef SPI_DIVIDER_LEN_24 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; + divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16]; `endif `ifdef SPI_DIVIDER_LEN_32 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[23:16] <= #Tp wb_dat_i[23:16]; + divider[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; + divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24]; `endif end end // Ctrl register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; else if(spi_ctrl_sel && wb_we_i && !tip) begin if (wb_sel_i[0]) - ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; if (wb_sel_i[1]) - ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; end else if(tip && last_bit && pos_edge) - ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; + ctrl[`SPI_CTRL_GO] <= 1'b0; end assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; @@ -233,39 +233,39 @@ module spi_top assign ass = ctrl[`SPI_CTRL_ASS]; // Slave select register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - ss <= #Tp {`SPI_SS_NB{1'b0}}; + ss <= {`SPI_SS_NB{1'b0}}; else if(spi_ss_sel && wb_we_i && !tip) begin `ifdef SPI_SS_NB_8 if (wb_sel_i[0]) - ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + ss <= wb_dat_i[`SPI_SS_NB-1:0]; `endif `ifdef SPI_SS_NB_16 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; + ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8]; `endif `ifdef SPI_SS_NB_24 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; + ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16]; `endif `ifdef SPI_SS_NB_32 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[23:16] <= #Tp wb_dat_i[23:16]; + ss[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; + ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24]; `endif end end diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v new file mode 100644 index 000000000..ee808a8ab --- /dev/null +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v @@ -0,0 +1,182 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style and +// allow 16-bit operation + +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" + +module spi_top16 + (input wb_clk_i, input wb_rst_i, + input [4:0] wb_adr_i, + input [15:0] wb_dat_i, + output reg [15:0] wb_dat_o, + input [1:0] wb_sel_i, + input wb_we_i, input wb_stb_i, input wb_cyc_i, + output reg wb_ack_o, output wb_err_o, output reg wb_int_o, + + // SPI signals + output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); + + // Internal signals + reg [15:0] divider; // Divider register + reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [15:0] ss; // Slave select register + reg [31:0] wb_dat; // wb data out + wire [31:0] rx; // Rx register + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len + wire go; // go + wire lsb; // lsb first on line + wire ie; // interrupt enable + wire ass; // automatic slave select + wire spi_divider_sel; // divider register select + wire spi_ctrl_sel; // ctrl register select + wire [3:0] spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + // Address decoder + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE); + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL); + assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0); + assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1); + assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2); + assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS); + + always @(wb_adr_i or rx or ctrl or divider or ss) + case (wb_adr_i[4:2]) + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; + `SPI_DIVIDE: wb_dat = {16'b0, divider}; + `SPI_SS: wb_dat = {16'b0, ss}; + default : wb_dat = 32'd0; + endcase // case (wb_adr_i[4:2]) + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_dat_o <= 32'b0; + else + wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0]; + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; + + assign wb_err_o = 1'b0; + + // Interrupt + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_int_o <= 1'b0; + else if (ie && tip && last_bit && pos_edge) + wb_int_o <= 1'b1; + else if (wb_ack_o) + wb_int_o <= 1'b0; + + // Divider register + always @(posedge wb_clk_i) + if (wb_rst_i) + divider <= 16'b0; + else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1]) + divider <= wb_dat_i; + + // Ctrl register + always @(posedge wb_clk_i) + if (wb_rst_i) + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; + else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; + if (wb_sel_i[1]) + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + end + else if(tip && last_bit && pos_edge) + ctrl[`SPI_CTRL_GO] <= 1'b0; + + assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; + assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; + assign go = ctrl[`SPI_CTRL_GO]; + assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; + assign lsb = ctrl[`SPI_CTRL_LSB]; + assign ie = ctrl[`SPI_CTRL_IE]; + assign ass = ctrl[`SPI_CTRL_ASS]; + + // Slave select register + always @(posedge wb_clk_i) + if (wb_rst_i) + ss <= 16'b0; + else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ss[7:0] <= wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= wb_dat_i[15:8]; + end + + assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}})); + + spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), + .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), + .neg_edge(neg_edge)); + + wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), + (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) }; + + + spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), + .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), + .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), + .tip(tip), .last(last_bit), + .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), + .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); + +endmodule // spi_top16 diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v b/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore index bf1b77066..0d90f1698 100644 --- a/fpga/usrp2/top/.gitignore +++ b/fpga/usrp2/top/.gitignore @@ -1 +1,2 @@ /*.sav +build* diff --git a/fpga/usrp2/top/u1e/.gitignore b/fpga/usrp2/top/u1e/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/fpga/usrp2/top/u1e/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/u1e/Makefile new file mode 100644 index 000000000..3cb9fd8f3 --- /dev/null +++ b/fpga/usrp2/top/u1e/Makefile @@ -0,0 +1,101 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e_core.v \ +u1e.v \ +u1e.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e/README b/fpga/usrp2/top/u1e/README new file mode 100644 index 000000000..14c7a4955 --- /dev/null +++ b/fpga/usrp2/top/u1e/README @@ -0,0 +1,4 @@ + +make clean +make sim +./tb_u1e -lxt2 diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/u1e/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + diff --git a/fpga/usrp2/top/u1e/make.sim b/fpga/usrp2/top/u1e/make.sim new file mode 100644 index 000000000..1c163884c --- /dev/null +++ b/fpga/usrp2/top/u1e/make.sim @@ -0,0 +1,7 @@ +all: sim + +sim: + iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e + +clean: + rm -f tb_u1e *.vcd *.lxt a.out diff --git a/fpga/usrp2/top/u1e/tb_u1e.v b/fpga/usrp2/top/u1e/tb_u1e.v new file mode 100644 index 000000000..5fc8134fb --- /dev/null +++ b/fpga/usrp2/top/u1e/tb_u1e.v @@ -0,0 +1,41 @@ +`timescale 1ps / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + xlnx_glbl glbl (.GSR(),.GTS()); + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0, rst_fpga = 1; + always #15625 clk_fpga = ~clk_fpga; + + initial #200000 + @(posedge clk_fpga) + rst_fpga <= 0; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model_async gpmc_model_async + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // tb_u1e diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/fpga/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/fpga/usrp2/top/u1e/u1e.ucf b/fpga/usrp2/top/u1e/u1e.ucf new file mode 100644 index 000000000..0c487a601 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e.ucf @@ -0,0 +1,259 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; + +## FTDI UART to USB converter +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; + +#NET "SYSEN" LOC = "C11" ; + +## I2C +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; + +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; + +### Clock Gen SPI +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; + +## Clock gen control +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; + +#NET "reset_codec" LOC = "C2" ; + +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; + +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; + +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; + +NET "PPS_IN" LOC = "M5" ; + +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; + +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; + +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/fpga/usrp2/top/u1e/u1e.v b/fpga/usrp2/top/u1e/u1e.v new file mode 100644 index 000000000..445b14a03 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e.v @@ -0,0 +1,141 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO + input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + + input PPS_IN + ); + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + wire clk_2x, dcm_rst, dcm_locked, clk_fb; + DCM #(.CLK_FEEDBACK ( "1X" ), + .CLKDV_DIVIDE ( 2 ), + .CLKFX_DIVIDE ( 2 ), + .CLKFX_MULTIPLY ( 2 ), + .CLKIN_DIVIDE_BY_2 ( "FALSE" ), + .CLKIN_PERIOD ( 15.625 ), + .CLKOUT_PHASE_SHIFT ( "NONE" ), + .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), + .DFS_FREQUENCY_MODE ( "LOW" ), + .DLL_FREQUENCY_MODE ( "LOW" ), + .DUTY_CYCLE_CORRECTION ( "TRUE" ), + .FACTORY_JF ( 16'h8080 ), + .PHASE_SHIFT ( 0 ), + .STARTUP_WAIT ( "FALSE" )) + clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), + .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), + .CLKDV(), .CLKFX(), .CLKFX180(), + .CLK2X(), .CLK2X180(), + .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), + .LOCKED(dcm_locked), .STATUS()); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(delay_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), + .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), + .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, + {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, + {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), + .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Local Debug + // assign debug_clk = {clk_fpga, clk_2x }; + // assign debug = { TXSYNC, TXBLANK, TX }; + +endmodule // u1e diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v new file mode 100644 index 000000000..619e44b8a --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -0,0 +1,459 @@ + + +//`define LOOPBACK 1 +//`define TIMED 1 +`define DSP 1 + +module u1e_core + (input clk_fpga, input rst_fpga, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + + input [11:0] misc_gpio, input pps_in + ); + + localparam TXFIFOSIZE = 13; + localparam RXFIFOSIZE = 13; + + localparam SR_RX_DSP = 0; // 5 regs + localparam SR_CLEAR_FIFO = 6; // 1 reg + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_TIME64 = 28; // 4 regs + + wire COMPAT_NUM = 8'd2; + + wire wb_clk = clk_fpga; + wire wb_rst = rst_fpga; + + wire pps_int; + wire [63:0] vita_time; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire [31:0] debug_vt; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; + wire [7:0] rate; + + wire bus_error; + + wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; + + setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); + assign clear_tx = clear_tx_int & do_clear; + assign clear_rx = clear_rx_int & do_clear; + + gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .debug(debug_gpmc)); + + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + +`ifdef LOOPBACK + wire [7:0] WHOAMI = 1; + + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + assign tx_underrun = 0; + assign rx_overrun = 0; + + wire run_tx, run_rx, strobe_tx, strobe_rx; +`endif // LOOPBACK + +`ifdef TIMED + wire [7:0] WHOAMI = 2; + + // TX side + wire tx_enable; + + fifo_pacer tx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), + .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), + .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), + .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // RX side + wire rx_enable; + + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), + .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), + .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + +`endif // `ifdef TIMED + +`ifdef DSP + wire [7:0] WHOAMI = 0; + + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx1_data; + wire run_rx; + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), + .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [15:0] tx_i_int, tx_q_int; + wire run_tx; + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + +`else // !`ifdef DSP + // Dummy DSP signal generator for test purposes + wire [23:0] tx_i_int, tx_q_int; + wire [23:0] freq = {reg_test,8'd0}; + reg [23:0] phase; + + always @(posedge wb_clk) + phase <= phase + freq; + + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); + + assign tx_i = tx_i_int[23:10]; + assign tx_q = tx_q_int[23:10]; +`endif // !`ifdef DSP + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s7_ack = 0; + assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + tx_frame_len <= 0; + xfer_rate <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_TX_FRAMELEN : + tx_frame_len <= s0_dat_mosi; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign tx_enable = xfer_rate[15]; + assign rx_enable = xfer_rate[14]; + assign rate = xfer_rate[7:0]; + + assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]}; + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #5 + + // only have 32 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), + .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { EM_CLK, clk_fpga }; + + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, + { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, + { EM_D } }; + + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + + assign debug_gpio_1 = debug_vt; + +/* + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, + {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, + {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, + {2'b0, bus_error, debug_gpmc[4:0] }, + {misc_gpio[7:0]} }; + */ +endmodule // u1e_core diff --git a/fpga/usrp2/top/u1e_ethdebug/.gitignore b/fpga/usrp2/top/u1e_ethdebug/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/fpga/usrp2/top/u1e_ethdebug/Makefile b/fpga/usrp2/top/u1e_ethdebug/Makefile new file mode 100644 index 000000000..751b52970 --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/Makefile @@ -0,0 +1,83 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e.v \ +u1e.ucf + +SOURCES = $(abspath $(TOP_SRCS)) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf new file mode 100644 index 000000000..d6a2ea4ed --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf @@ -0,0 +1,88 @@ + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; +NET "overo_gpio64" LOC = "A4" ; # nRESET +NET "overo_gpio176" LOC = "B4" ; # IRQ + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.v b/fpga/usrp2/top/u1e_ethdebug/u1e.v new file mode 100644 index 000000000..2a543a313 --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/u1e.v @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +//`define DCM 1 + +module u1e + (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, + + // GPMC + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_NADV_ALE, + + input overo_gpio64, input overo_gpio176 + ); + + assign debug_clk = {EM_CLK, EM_NADV_ALE}; + + assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; + + assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, + { EM_A[10], EM_A[7:1] }, + { EM_D[15:8] }, + { EM_D[7:0] } }; + + +endmodule // u1e diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/u1e_passthru/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile new file mode 100644 index 000000000..d1950629b --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/Makefile @@ -0,0 +1,99 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = passthru +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +passthru.v \ +passthru.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/u1e_passthru/passthru.ucf new file mode 100644 index 000000000..64e6f0440 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/passthru.ucf @@ -0,0 +1,6 @@ +NET "overo_gpio145" LOC = "C7" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; +NET "fpga_cfg_din" LOC = "W17" ; +NET "fpga_cfg_cclk" LOC = "V17" ; diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v new file mode 100644 index 000000000..12e4db017 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio145, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio145; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru |