diff options
| -rw-r--r-- | host/lib/usrp/e100/clock_ctrl.cpp | 37 | ||||
| -rw-r--r-- | host/lib/usrp/e100/clock_ctrl.hpp | 3 | ||||
| -rw-r--r-- | host/lib/usrp/e100/e100_impl.cpp | 9 |
3 files changed, 36 insertions, 13 deletions
diff --git a/host/lib/usrp/e100/clock_ctrl.cpp b/host/lib/usrp/e100/clock_ctrl.cpp index 6acb13528..0eb9eef8e 100644 --- a/host/lib/usrp/e100/clock_ctrl.cpp +++ b/host/lib/usrp/e100/clock_ctrl.cpp @@ -167,7 +167,9 @@ static clock_settings_type get_clock_settings(double rate){ **********************************************************************/ class e100_clock_ctrl_impl : public e100_clock_ctrl{ public: - e100_clock_ctrl_impl(spi_iface::sptr iface, double master_clock_rate){ + e100_clock_ctrl_impl(spi_iface::sptr iface, double master_clock_rate, const bool dboard_clocks_diff): + _dboard_clocks_diff(dboard_clocks_diff) + { _iface = iface; _chan_rate = 0.0; _out_rate = 0.0; @@ -319,10 +321,16 @@ public: * RX Dboard Clock Control (output 9, divider 3) **********************************************************************/ void enable_rx_dboard_clock(bool enb){ - _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; - _ad9522_regs.out9_cmos_configuration = (enb)? - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; + if (_dboard_clocks_diff){ + _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_LVDS; + _ad9522_regs.out9_lvds_power_down = enb? 0 : 1; + } + else{ + _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; + _ad9522_regs.out9_cmos_configuration = (enb)? + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; + } this->send_reg(0x0F9); this->latch_regs(); } @@ -357,10 +365,16 @@ public: * TX Dboard Clock Control (output 6, divider 2) **********************************************************************/ void enable_tx_dboard_clock(bool enb){ - _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; - _ad9522_regs.out6_cmos_configuration = (enb)? - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; + if (_dboard_clocks_diff){ + _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_LVDS; + _ad9522_regs.out6_lvds_power_down = enb? 0 : 1; + } + else{ + _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; + _ad9522_regs.out6_cmos_configuration = (enb)? + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; + } this->send_reg(0x0F6); this->latch_regs(); } @@ -420,6 +434,7 @@ public: private: spi_iface::sptr _iface; + const bool _dboard_clocks_diff; ad9522_regs_t _ad9522_regs; double _out_rate; //rate at the fpga and codec double _chan_rate; //rate before final dividers @@ -505,6 +520,6 @@ private: /*********************************************************************** * Clock Control Make **********************************************************************/ -e100_clock_ctrl::sptr e100_clock_ctrl::make(spi_iface::sptr iface, double master_clock_rate){ - return sptr(new e100_clock_ctrl_impl(iface, master_clock_rate)); +e100_clock_ctrl::sptr e100_clock_ctrl::make(spi_iface::sptr iface, double master_clock_rate, const bool dboard_clocks_diff){ + return sptr(new e100_clock_ctrl_impl(iface, master_clock_rate, dboard_clocks_diff)); } diff --git a/host/lib/usrp/e100/clock_ctrl.hpp b/host/lib/usrp/e100/clock_ctrl.hpp index 7c16649d3..538ea65d8 100644 --- a/host/lib/usrp/e100/clock_ctrl.hpp +++ b/host/lib/usrp/e100/clock_ctrl.hpp @@ -36,9 +36,10 @@ public: * Make a new clock control object. * \param iface the spi iface object * \param master clock rate the FPGA rate + * param dboard_clocks_diff are they differential? * \return the clock control object */ - static sptr make(uhd::spi_iface::sptr iface, double master_clock_rate); + static sptr make(uhd::spi_iface::sptr iface, double master_clock_rate, const bool dboard_clocks_diff); /*! * Set the rate of the fpga clock line. diff --git a/host/lib/usrp/e100/e100_impl.cpp b/host/lib/usrp/e100/e100_impl.cpp index 5c7ff04fd..b80ee0836 100644 --- a/host/lib/usrp/e100/e100_impl.cpp +++ b/host/lib/usrp/e100/e100_impl.cpp @@ -139,9 +139,16 @@ e100_impl::e100_impl(const uhd::device_addr_t &device_addr){ } //setup clock control here to ensure that the FPGA has a good clock before we continue + bool dboard_clocks_diff = true; + if (mb_eeprom.get("revision", "0") == "3") dboard_clocks_diff = false; + else if (mb_eeprom.get("revision", "0") == "4") dboard_clocks_diff = true; + else UHD_MSG(warning) + << "Unknown E1XX revision number!\n" + << "defaulting to differential dboard clocks to be safe.\n" + << std::endl; const double master_clock_rate = device_addr.cast<double>("master_clock_rate", E100_DEFAULT_CLOCK_RATE); _aux_spi_iface = e100_ctrl::make_aux_spi_iface(); - _clock_ctrl = e100_clock_ctrl::make(_aux_spi_iface, master_clock_rate); + _clock_ctrl = e100_clock_ctrl::make(_aux_spi_iface, master_clock_rate, dboard_clocks_diff); //Perform wishbone readback tests, these tests also write the hash bool test_fail = false; |