diff options
| -rw-r--r-- | host/lib/usrp/usrp_e100/io_impl.cpp | 23 | ||||
| -rw-r--r-- | host/lib/usrp/usrp_e100/usrp_e100_iface.cpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/usrp_e100/usrp_e100_impl.hpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/usrp_e100/usrp_e100_regs.hpp | 12 |
4 files changed, 33 insertions, 10 deletions
diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/usrp_e100/io_impl.cpp index 2388482c7..58faeafb0 100644 --- a/host/lib/usrp/usrp_e100/io_impl.cpp +++ b/host/lib/usrp/usrp_e100/io_impl.cpp @@ -35,7 +35,8 @@ zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface); /*********************************************************************** * Constants **********************************************************************/ -static const size_t tx_async_report_sid = 1; +static const size_t rx_data_inline_sid = 1; +static const size_t tx_async_report_sid = 2; static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; static const bool recv_debug = false; @@ -110,8 +111,17 @@ void usrp_e100_impl::io_impl::recv_pirate_loop(usrp_e100_clock_ctrl::sptr clock_ const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>(); vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); + //handle an rx data packet or inline message + if (if_packet_info.sid == rx_data_inline_sid){ + if (recv_debug) std::cout << "this is rx_data_inline_sid\n"; + //same number of frames as the data transport -> always immediate + recv_pirate_booty->push_with_wait(buff); + continue; + } + //handle a tx async report message if (if_packet_info.sid == tx_async_report_sid and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + if (recv_debug) std::cout << "this is tx_async_report_sid\n"; //fill in the async metadata async_metadata_t metadata; @@ -128,8 +138,7 @@ void usrp_e100_impl::io_impl::recv_pirate_loop(usrp_e100_clock_ctrl::sptr clock_ continue; } - //same number of frames as the data transport -> always immediate - recv_pirate_booty->push_with_wait(buff); + if (recv_debug) std::cout << "this is unknown packet\n"; }catch(const std::exception &e){ std::cerr << "Error (usrp-e recv pirate loop): " << e.what() << std::endl; @@ -153,17 +162,20 @@ void usrp_e100_impl::io_init(void){ //setup before the registers (transport called to calculate max spp) _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface)); + //clear state machines + _iface->poke32(UE_REG_CTRL_RX_CLEAR, 0); + _iface->poke32(UE_REG_CTRL_TX_CLEAR, 0); + //setup rx data path _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); - _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer | (0x3 << 22) //integer time other | (0x1 << 20) //fractional time sample count ); - _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, 0); + _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, rx_data_inline_sid); _iface->poke32(UE_REG_CTRL_RX_VRT_TRAILER, 0); //setup the tx policy @@ -185,7 +197,6 @@ void usrp_e100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ void usrp_e100_impl::handle_overrun(size_t){ std::cerr << "O"; //the famous OOOOOOOOOOO - _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 0); if (_io_impl->continuous_streaming){ this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); } diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp index 40c7afabb..ad36dd97a 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010 Ettus Research LLC +// Copyright 2010-2011 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -16,6 +16,7 @@ // #include "usrp_e100_iface.hpp" +#include "usrp_e100_regs.hpp" #include <uhd/utils/assert.hpp> #include <sys/ioctl.h> //ioctl #include <fcntl.h> //open, close @@ -108,6 +109,9 @@ public: throw std::runtime_error("Failed to open " + node); } + //very first thing, reset all the wishbone, always do first! + this->poke32(UE_REG_CLEAR_GLOBAL, 0); + mb_eeprom = mboard_eeprom_t(get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100); } diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp index df8e5dc9f..864e82099 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp @@ -30,7 +30,7 @@ #ifndef INCLUDED_USRP_E100_IMPL_HPP #define INCLUDED_USRP_E100_IMPL_HPP -static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; //make this 3 then the mainline fpga image gets fixed for embedded +static const boost::uint16_t USRP_E_COMPAT_NUM = 0x03; //! load an fpga image from a bin file into the usrp-e fpga extern void usrp_e100_load_fpga(const std::string &bin_file); diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp index 7dc3a4ba8..a030462d0 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp @@ -126,6 +126,14 @@ #define UE_REG_SR_MISC_TEST32 UE_REG_SETTINGS_BASE_ADDR(52) ///////////////////////////////////////////////// +// Magic reset regs +//////////////////////////////////////////////// +#define UE_REG_CLEAR_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(48) + (4*(n))) +#define UE_REG_CLEAR_RX UE_REG_CLEAR_ADDR(0) +#define UE_REG_CLEAR_TX UE_REG_CLEAR_ADDR(1) +#define UE_REG_CLEAR_GLOBAL UE_REG_CLEAR_ADDR(2) + +///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// #define UE_REG_DSP_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(16) + (4*(n))) @@ -145,7 +153,7 @@ #define UE_REG_CTRL_RX_STREAM_CMD UE_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) #define UE_REG_CTRL_RX_TIME_SECS UE_REG_CTRL_RX_ADDR(1) #define UE_REG_CTRL_RX_TIME_TICKS UE_REG_CTRL_RX_ADDR(2) -#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_CTRL_RX_ADDR(3) // write anything to clear overrun +#define UE_REG_CTRL_RX_CLEAR UE_REG_CTRL_RX_ADDR(3) // write anything to clear #define UE_REG_CTRL_RX_VRT_HEADER UE_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter #define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_CTRL_RX_ADDR(5) // word 1 of packet. #define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_CTRL_RX_ADDR(6) @@ -167,7 +175,7 @@ //////////////////////////////////////////////// #define UE_REG_CTRL_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) #define UE_REG_CTRL_TX_NCHANNELS UE_REG_CTRL_TX_ADDR(0) -#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_CTRL_TX_ADDR(1) +#define UE_REG_CTRL_TX_CLEAR UE_REG_CTRL_TX_ADDR(1) #define UE_REG_CTRL_TX_REPORT_SID UE_REG_CTRL_TX_ADDR(2) #define UE_REG_CTRL_TX_POLICY UE_REG_CTRL_TX_ADDR(3) |