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| -rw-r--r-- | host/docs/usrp_e3x0.dox | 445 |
7 files changed, 386 insertions, 130 deletions
diff --git a/host/docs/gpio_api.dox b/host/docs/gpio_api.dox index 96d2a14be..febd1f7a8 100644 --- a/host/docs/gpio_api.dox +++ b/host/docs/gpio_api.dox @@ -1,17 +1,17 @@ -/*! \page page_gpio_api X3x0 GPIO API +/*! \page page_gpio_api E3x0/X3x0 GPIO API \tableofcontents -\section xgpio_fpanel The X3x0 Front Panel GPIO +\section xgpio_fpanel The E3x0/X3x0 Front Panel GPIO -The X3x0 is the first USRP device to offer an auxiliary GPIO connection +The E3x0/X3x0 are the first USRP devices to offer an auxiliary GPIO connection on the motherboard itself (independent of the daughterboards). These GPIO pins are controlled directly by the FPGA, where they are controlled by an ATR (Automatic Transmit / Receive). This allows them to be toggled simultaneously with other radio-level changes (e.g., enabling or disabling a TX or RX mixer). -\subsection xgpio_fpanel_gpio Front Panel GPIO +\subsection xgpio_fpanel_gpio X3x0 Front Panel GPIO \subsubsection xgpio_fpanel_conn Connector @@ -35,6 +35,26 @@ disabling a TX or RX mixer). - Pin 14: 0V - Pin 15: 0V +\subsection egpio_internal_gpio E3x0 Internal GPIO + +\subsubsection egpio_internal_conn Connector + +\image html e3x0_gpio_conn.png "E3x0 GPIO Connector" + +### Pin Mapping + +- Pin 1: +3.3V +- Pin 2: Reserved +- Pin 3: Data[5] +- Pin 4: Reserved +- Pin 5: Data[4] +- Pin 6: Data[0] +- Pin 7: Data[3] +- Pin 8: Data[1] +- Pin 9: 0V +- Pin 10: Data[2] + + \subsection xgpio_fpanel_atr Explaining ATR ATR works by defining the value of the GPIO pins for certain states of @@ -69,12 +89,12 @@ one more: \subsection xgpio_fpanel_xample An Example The front panel X3x0 GPIO bank is enumerated in the motherboard property -tree ('*<mb_path>/gpio/FP0/\*'), and so is easily accessible through +tree ('*<mb_path>/gpio/FP0/\*'), the E3x0 internal GPIO bank as ('*<mb_path>/gpio/INT0/\*') and so are easily accessible through the standard uhd::usrp::multi_usrp UHD interface. You can discover this using the uhd::usrp::multi_usrp::get_gpio_banks() function. This will tell you that there is a GPIO bank on your -X3x0 called "FP0". This is the bank we want to set-up. +X3x0 called "FP0" (for E3x0 this will be called "INT0"). This is the bank we want to set-up. Let's say we want to use GPIO6 for an external amp. We want it to be automatically controlled by ATR as an output, and we want it to be high @@ -115,5 +135,42 @@ After the above code is run, the ATR in the FPGA will automatically control GPIO6, as we have described, based on the radio state, and we have direct manual control over GPIO4. +The following example has been modified to work with he E3x0's internal +GPIO bank, where the controlled GPIO is now GPIO3 instead of GPIO6. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + // set up our masks, defining the pin numbers + #define AMP_GPIO_MASK (1 << 3) + #define MAN_GPIO_MASK (1 << 4) + + #define ATR_MASKS (AMP_GPIO_MASK | MAN_GPIO_MASK) + + // set up our values for ATR control: 1 for ATR, 0 for manual + #define ATR_CONTROL (AMP_GPIO_MASK & ~MAN_GPIO_MASK) + + // set up the GPIO directions: 1 for output, 0 for input + #define GPIO_DDR (AMP_GPIO_MASK & ~MAN_GPIO_MASK) + + // assume an existing USRP device handle, called "usrp_e300" + + // now, let's do the basic ATR setup + usrp_e300->set_gpio_attr("INT0", "CTRL", ATR_CONTROL, ATR_MASKS); + usrp_e300->set_gpio_attr("INT0", "DDR", GPIO_DDR, ATR_MASKS); + + // let's manually set GPIO4 high + usrp_e300->set_gpio_attr("INT0", "OUT", 1, MAN_GPIO_MASK); + + // finally, let's set up GPIO6 as we described above + usrp_e300->set_gpio_attr("INT0", "ATR_0X", 0, AMP_GPIO_MASK); + usrp_e300->set_gpio_attr("INT0", "ATR_RX", 0, AMP_GPIO_MASK); + usrp_e300->set_gpio_attr("INT0", "ATR_TX", 0, AMP_GPIO_MASK); + usrp_e300->set_gpio_attr("INT0", "ATR_XX", 0, AMP_GPIO_MASK); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +After the above code is run, the ATR in the FPGA will automatically +control GPIO3, as we have described, based on the radio state, and we +have direct manual control over GPIO4. + + */ // vim:ft=doxygen: diff --git a/host/docs/images.dox b/host/docs/images.dox index 2b7894300..321452b87 100644 --- a/host/docs/images.dox +++ b/host/docs/images.dox @@ -80,7 +80,7 @@ depending on the device. The build requires that you have a UNIX-like environment with `Make`. Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`. -- Xilinx ISE 14.7: USRP X3x0 Series, USRP B2x0 +- Xilinx ISE 14.4: USRP X3x0 Series, USRP B2x0 See `<uhd-repo-path>/fpga/usrp3/top/`. diff --git a/host/docs/res/e3x0_fp_overlay.png b/host/docs/res/e3x0_fp_overlay.png Binary files differnew file mode 100644 index 000000000..dacfb683e --- /dev/null +++ b/host/docs/res/e3x0_fp_overlay.png diff --git a/host/docs/res/e3x0_gpio_conn.png b/host/docs/res/e3x0_gpio_conn.png Binary files differnew file mode 100644 index 000000000..219bb1894 --- /dev/null +++ b/host/docs/res/e3x0_gpio_conn.png diff --git a/host/docs/res/e3x0_jtag_conn.png b/host/docs/res/e3x0_jtag_conn.png Binary files differnew file mode 100644 index 000000000..405896e4d --- /dev/null +++ b/host/docs/res/e3x0_jtag_conn.png diff --git a/host/docs/res/e3x0_rp_overlay.png b/host/docs/res/e3x0_rp_overlay.png Binary files differnew file mode 100644 index 000000000..62ad104c8 --- /dev/null +++ b/host/docs/res/e3x0_rp_overlay.png diff --git a/host/docs/usrp_e3x0.dox b/host/docs/usrp_e3x0.dox index bfa9ebf11..40e8daeab 100644 --- a/host/docs/usrp_e3x0.dox +++ b/host/docs/usrp_e3x0.dox @@ -2,7 +2,7 @@ \tableofcontents -\section e3x0_feature_list Comparative features list +\section e3x0_feature_list Comparative features list - E300/E310 - Hardware Capabilities: Integrated RF frontend (70 MHz - 6 GHz) @@ -16,11 +16,15 @@ - USB UART - Zynq-7020 FPGA - FPGA Capabilities: - - 2 RX DDC chains in FPGA - - 2 TX DUC chain in FPGA + - E310 Only: + - 2 RX DDC chains in FPGA + - 2 TX DUC chain in FPGA + - E300 Only: + - 1 RX DDC chains in FPGA + - 1 TX DUC chain in FPGA - Timed commands in FPGA - Timed sampling in FPGA - - 16-bit and sample modes (sc16) + - 16-bit fixed point sample mode (sc16) - Up to 10 MHz of RF bandwidth with 16-bit samples \section e3x0_getting_started Getting started @@ -30,8 +34,6 @@ up and running. \subsection e3x0_first_boot First boot -After unpacking and assembling your USRP E300/E310 insert the micro sd card into the micro sd card slot. - There are two different methods to connect to the device - using the onboard serial to usb connector @@ -61,7 +63,7 @@ On Microsoft Windows the serial connection can be established using a tool such In both cases you should see boot messages fly by and finally end up with a login prompt similar to the following: -TODO!! + ettus-e300 login: Note: The username is 'root' and the default password is empty. @@ -87,147 +89,194 @@ You should be presented with a shell similar to the following root@ettus-e300:~# -\section e3x0_hw Hardware Setup +\section e3x0_sdk Using the SDK -\section e3x0_load_fpga_imgs Load FPGA Images onto the Device +In order to facilitate software development for the integrated ARM Cortex-A9 processor, a <a href="http://www.yoctoproject.org">Yocto Project</a> based SDK is provided in the download section of our website. +This SDK contains a cross-compiler, a cross-linker as well as a cross-debugger and can be used to develop your user space applications for the Ettus USRP-E300/E310 devices. -The USRP-X Series device ships with a bitstream pre-programmed in the flash, -which is automatically loaded onto the FPGA during device power-up. However, -a new FPGA image can be configured over the PCI Express interface or the -on-board USB-JTAG programmer. This process can be seen as a "one-time load", in -that if you power-cycle the device, it will not retain the FPGA image. -Please note that this process is *different* than replacing the FPGA image -stored in the flash, which will then be automatically loaded the next time the -device is reset. +\subsection e3x0_sdk_installation Installation +The following section will guide you through the installation of the provided SDK on a Linux development machine. -\subsection e3x0_load_fpga_imgs_jtag Use JTAG to load FPGA images +\subsubsection e3x0_sdk_installation_download Obtaining the correct SDK +It is necessary for the SDK version and the image version to match, to ensure the versions of the software installed on the device and the version of the software the SDK will build against match. -The USRP-E Series device features an on-board JTAG connector that can be accessed on the PCB -of the device. The iMPACT tool in the <a href="http://www.xilinx.com/support/download/index.htm">Xilinx Programming Tools (ISE, iMPACT)</a> package can be used to load an image over the JTAG interface. This can be useful for unbricking devices. +If you are not sure which image is installed on your device, upgrading to the latest stable version is recommended. See \ref e3x0_rootfs_upgrade_restore for details on upgrading. -If you have iMPACT installed, you can use the `impact_jtag_programmer.sh` tool to install images. Make sure your e3x0 is powered on and connected to your computer using the internal JTAG connector. Then run the tool: +\subsubsection e3x0_sdk_installation_install Obtaining the right toolchain - <path_to_uhd_tools>/impact_jtag_programmer.sh --fpga-path=<fpga_image_path> +To install the toolchain you downloaded type: -\subsection e3x0_setup_change_ip Change the USRP's IP address + $ ./oecore-${TCLIBC}-${SDK_ARCH}-${IMAGE_BASENAME}-${TUNE_PKGARCH}.sh -You may need to change the USRP's IP address for several reasons: -- to satisfy your particular network configuration -- to use multiple USRP-E Series devices with the same host computer -- to set a known IP address into USRP (in case you forgot) +This will prompt you for an installation path. +Please ensure you have sufficient disk space, as each of the SDKs may require several gigabytes of disk space (depends on the image flavor selected). -\section e3x0_addressing Addressing the Device +This will allow you to compile UHD as well as (depending on the image flavor) other software. -\subsection e3x0_addressing_singledev Single device configuration +Please note, that while several toolchains can be installed in parallel, they have to be installed to different directories. -In a single-device configuration, -the USRP device must have a unique IPv4 address on the host computer. -The USRP can be identified through its IPv4 address or resolvable hostname. -See the application notes on \ref page_identification. -Use this addressing scheme with the uhd::usrp::multi_usrp interface (not a typo!). +\subsection e3x0_sdk_usage Usage -Example device address string representation for a USRP-E Series device with IPv4 address 192.168.10.2: +Having installed the toolchain in the last step, +in order to build software for your device open a new shell and type: - addr=192.168.10.2 + $ . <yoursdkinstallpath>/environment-setup-armv7ahf-vfp-neon-oe-linux-gnueabi -\subsection e3x0_addressing_multidevcfg Multiple device configuration +This will modifiy the PATH, CC, CXX etc, environment variables and allow you to compile software for your USRP E300/E310 device. +To verify all went well you can try: -In a multi-device configuration, -each USRP device must have a unique IPv4 address on the host computer. -The device address parameter keys must be suffixed with the device index. -Each parameter key should be of the format \<key\>\<index\>. -Use this addressing scheme with the uhd::usrp::multi_usrp interface. + $ $CC -dumpmachine -- The order in which devices are indexed corresponds to the indexing of the transmit and receive channels. -- The key indexing provides the same granularity of device identification as in the single device case. +which should return 'arm-oe-linux-gnueabi'. -Example device address string representation for 2 USRPs with IPv4 addresses **192.168.10.2** and **192.168.20.2**: +\subsubsection e3x0_sdk_usage_uhd Building UHD - addr0=192.168.10.2, addr1=192.168.20.2 +-# Obtain the UHD source code via git or tarball +-# Setup your environment as described in \ref e3x0_sdk_usage +-# Type the following in the build directory (assuming a build in host/build): + $ cmake -DCMAKE_TOOLCHAIN_FILE=<youruhdsrc>/host/cmake/Toolchains/oe-sdk_cross.cmake -DENABLE_E300 .. + $ make -\section e3x0_comm_problems Communication Problems +\subsubsection e3x0_sdk_usage_gnuradio Building GNU Radio -When setting up a development machine for the first time, -you may have various difficulties communicating with the USRP device. -The following tips are designed to help narrow down and diagnose the problem. +-# Obtain the gnuradio source code via git. +-# Setup the environment as described in \ref e3x0_sdk_usage +-# Use the following commands to create a build directory, configure and compile gnuradio. You only need create the build directory once. -\subsection e3x0_comm_problems_runtimeerr RuntimeError: no control response +\code{.sh} +$ mkdir build-arm +$ cmake -Wno-dev -DCMAKE_TOOLCHAIN_FILE=../cmake/Toolchains/oe-sdk_cross.cmake \-DCMAKE_INSTALL_PREFIX=/usr -DENABLE_GR_VOCODER=OFF -DGR_ENABLE_ATSC=OFF \ +-DENABLE_GR_DTV=OFF -DENABLE_DOXYGEN=OFF ../ +\endcode -This is a common error that occurs when you have set the subnet of your network -interface to a different subnet than the network interface of the USRP device. For -example, if your network interface is set to **192.168.20.1**, and the USRP device is **192.168.10.2** -(note the difference in the third numbers of the IP addresses), you -will likely see a 'no control response' error message. +Several GNU Radio components depend on running binaries built for the build +machine during compile. These binaries can be built and used for cross +compiling, but this is an advanced topic. -Fixing this is simple - just set the your host PC's IP address to the same -subnet as that of your USRP device. Instructions for setting your IP address are in the -previous section of this documentation. +\section e3x0_image_building Rebuilding the file system -\subsection e3x0_comm_problems_firewall Firewall issues +The file system images are built using OpenEmbedded Core. The `repo` tool is +used to manage the versions of the various layers that supply recipes for +building the image. For more documentation see http://www.yoctoproject.org. +These notes will show you how to rebuild the files used to create the SD +card included with the E310. These instructions assume you ahve a working +knowledge of Linux. -When the IP address is not specified, -the device discovery broadcasts UDP packets from each Ethernet interface. -Many firewalls will block the replies to these broadcast packets. -If disabling your system's firewall -or specifying the IP address yields a discovered device, -then your firewall may be blocking replies to UDP broadcast packets. -If this is the case, we recommend that you disable the firewall -or create a rule to allow all incoming packets with UDP source port **49152**. +-# Install `repo`. +\code{.sh} + $ curl http://commondatastorage.googleapis.com/git-repo-downloads/repo > repo + $ chmod a+x repo + $ sudo mv repo /usr/local/bin +\endcode -\subsection e3x0_comm_problems_ping Ping the device -The USRP device will reply to ICMP echo requests ("ping"). -A successful ping response means that the device has booted properly -and that it is using the expected IP address. +-# Configure the repo manifest that controls the build. +\code{.sh} + $ mkdir e300-oe-build + $ cd e300-oe-build + $ repo init -u git://github.com/EttusResearch/e300-manifest.git -b release1 +\endcode + +-# Initialize the environment. This will take a little while. +\code{.sh} + $ repo sync + $ TEMPLATECONF=`pwd`/meta-ettus/conf source ./oe-core/oe-init-build-env ./build ./bitbake +\endcode + +At this point you should review the file in conf/local.conf and make sure +path names make sense for your machine. + +-# Build an image. This will take a few hours, especially the first run since +it will download all the required sources. (These are saved locally for future +builds) +\code{.sh} + $ export MACHINE="ettus-e300" + $ bitbake gnuradio-dev-image +\endcode + +When this completes, the files needed to create the sd card are in +`tmp-glibc/deploy/images/ettus-e300` + +-# Build the toolchain. +\code{.sh} + $ bitbake -c populate_sdk gnuradio-dev-image +\endcode + +The sdk is in `tmp-glibc/deploy/sdk` + +Note that you can set the `MACHINE` variable in `local.conf so that you no +longer need to set it from the command line. + +When you log back in, you will need to setup the OpenEmbedded environment +again by: + +\code{.sh} + $ cd e300-oe-build/oe-core + $ . oe-core/oe-init-build-env ./build ./bitbake +\endcode + +\section e3x0_load_fpga_imgs Specifying a Non-standard FPGA Image + +\subsection e3x0_load_fpga_imgs_uhd Using UHD to load FPGA images + +UHD software will automatically select the USRP E300/E310 images from the +installed images package. The image selection can be overridden with the +`fpga` device address parameter. + +Example device address string representations to specify non-standard +image: + + $ uhd_usrp_probe --args='fpga=usrp_e310_fpga.bit' + +\subsection e3x0_load_fpga_imgs_jtag Using JTAG to load FPGA images + +The USRP-E Series device features an on-board JTAG connector (see \ref e3x0_hw_chipscope) that can be accessed on the PCB +of the device. The iMPACT tool in the <a href="http://www.xilinx.com/support/download/index.htm">Xilinx Programming Tools (ISE, iMPACT)</a> package can be used to load an image over the JTAG interface. + +If you have iMPACT installed, you can use the `impact_jtag_programmer.sh` tool to install images. Make sure your e3x0 is powered on and connected to your computer using the internal JTAG connector. Then run the tool: + + <path_to_uhd_tools>/impact_jtag_programmer.sh --fpga-path=<fpga_image_path> + +\subsection e3x0_setup_change_ip Change the USRP's IP address + +You may need to change the USRP's IP address for several reasons: +- to satisfy your particular network configuration +- to use multiple USRP-E Series devices with the same host computer +- to set a known IP address into USRP (in case you forgot) - ping 192.168.10.2 -\subsection e3x0_comm_problems_monitor Monitor the host network traffic -Use Wireshark to monitor packets sent to and received from the device. -\subsection e3x0_comm_problems_leds Observe Ethernet port LEDs -When there is network traffic arriving at the Ethernet port, LEDs will light up. -You can use this to make sure the network connection is correctly set up, e.g. -by pinging the USRP and making sure the LEDs start to blink. \section e3x0_hw Hardware Notes \subsection e3x0_hw_fpanel Front Panel -\image html e3x0_fp_overlay.png "e3x0" +\image html e3x0_fp_overlay.png "USRP E300/E310 Front panel" - **RF A Group** - + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard A - + **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard A -- **REF**: Indicates that the external Reference Clock is locked -- **PPS**: Indicates a valid PPS signal by pulsing once per second -- **AUX I/O**: Front panel GPIO connector. -- **GPS**: Indicates that GPS reference is locked -- **LINK**: Indicates that the host computer is communicating with the device (Activity) + + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on frontend side A + + **RX2 LED**: Indicates that data is streaming on the RX2 channel on frontend side A - **RF B Group** - + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard B - + **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard B + + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on frontend B + + **RX2 LED**: Indicates that data is streaming on the RX2 channel on frontend B - **PWR**: Power switch -\subsection e3x0_hw_rear_panel Rear Panel - -\image html e3x0_rp_overlay.png "e3x0 Rear Panel" +- **SYNC**: Input port for external PPS signal -- **PWR**: Connector for the USRP-X Series power supply -- **1G/10G ETH**: SFP+ ports for Ethernet interfaces -- **REF OUT**: Output port for the exported reference clock -- **REF IN**: Reference clock input -- **PCIe x4**: Connector for Cabled PCI Express link -- **PPS/TRIG OUT**: Output port for the PPS signal -- **PPS/TRIG IN**: Input port for the PPS signal - **GPS**: Connection for the GPS antenna -\subsection e3x0_hw_e3x0_hw_ref10M Ref Clock - 10 MHz +- **AUDIO**: Audio input / output + +\subsection e3x0_hw_rear_panel Rear Panel + +\image html e3x0_rp_overlay.png "USRP E300/E310 Rear Panel" -Using an external 10 MHz reference clock, a square wave will offer the best phase -noise performance, but a sinusoid is acceptable. The power level of the reference clock cannot exceed +15 dBm. +- **PWR**: Locking connector for the USRP-E Series power supply +- **1G ETH**: RJ45 port for Ethernet interfaces +- **USB**: USB 2.0 Port +- **SERIAL**: Micro USB connection for serial uart console \subsection e3x0_hw_pps PPS - Pulse Per Second Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude. @@ -241,52 +290,108 @@ To test the PPS input, you can use the following tool from the UHD examples: \subsection e3x0_hw_gpsdo Internal GPSDO -Please see \ref page_gpsdo_e3x0 for information on configuring and using the internal GPSDO. +Your USRP-E Series device comes with an internal GPSDO. +In order to get a lock on a satellite an external GPS antenna is required. + +The device provides a 3.3V supply voltage to an external antenna connected to the *GPS* port +of your device. Note that this supply voltage is turned off in order to safe power upon destruction of the software object. \subsection e3x0_hw_gpio Internal GPIO ### Connector -\image html e3x0_gpio_conn.png "e3x0 GPIO Connector" +\image html e3x0_gpio_conn.png "E3x0 GPIO Connector" ### Pin Mapping -- Pin 1: +3.3V -- Pin 2: Data[0] -- Pin 3: Data[1] -- Pin 4: Data[2] -- Pin 5: Data[3] -- Pin 6: Data[4] -- Pin 7: Data[5] -- Pin 8: Data[6] -- Pin 9: Data[7] -- Pin 10: Data[8] -TODO: - +- Pin 1: +3.3V +- Pin 2: Reserved +- Pin 3: Data[5] +- Pin 4: Reserved +- Pin 5: Data[4] +- Pin 6: Data[0] +- Pin 7: Data[3] +- Pin 8: Data[1] +- Pin 9: 0V +- Pin 10: Data[2] Please see the \ref page_gpio_api for information on configuring and using the GPIO bus. +\subsection e3x0_hw_audio Audio connectors + \subsection e3x0_hw_chipscope Debugging custom FPGA designs with Xilinx Chipscope +### Connector + +\image html e3x0_jtag_conn.png "E3x0 JTAG Connector" + +### Pin Mapping + +- Pin 1: TDO +- Pin 2: 3.3V +- Pin 3: TCK +- Pin 4: TDI +- Pin 5: 0V +- Pin 6: TMS + + Xilinx chipscope allows for debugging custom FPGA designs similar to a logic analyzer. USRP-E series devices can be used with Xilinx chipscope using the internal JTAG connector. -Further information on how to use Chipscope can be found in the Xilinx Chipscope Pro Software and Cores User Guide (UG029). +Further information on how to use Chipscope can be found in the *Xilinx Chipscope Pro Software and Cores User Guide (UG029)*. + +\section e3x0_dboards Daughterboard notes + +\subsection e3x0_dboard_e310 E310 MIMO XCVR board + +The USRP E310 MIMO XCVR daughterboard features an integrated MIMO capable RF frontend. + +\subsubsection e3x0_dboard_e310_tuning Frontend tuning + +The RF frontend has individually tunable receive and transmit chains. +Both transmit and receive can be used in a MIMO configuration. For +the MIMO case, both receive frontends share the RX LO, and both transmit +frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz. + +\subsubsection e3x0_dboard_e310_gain Frontend gain + +All frontends have individual analog gain controls. The receive +frontends have 73 dB of available gain; and the transmit frontends have +89.5 dB of available gain. Gain settings are application specific, but +it is recommended that users consider using at least half of the +available gain to get reasonable dynamic range. + +\subsubsection e3x0_dboard_e310_pll Frontend LO lock status + +The frontends provide a *lo-locked* sensor that can be queried through the UHD API. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} +// assumes 'usrp' is a valid uhd::usrp::multi_usrp::sptr instance + +// get status for rx frontend +usrp->get_rx_sensor("lo-locked"); + +// get status for tx frontend +usrp->get_tx_sensor("lo-locked"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + \section e3x0_misc Miscellaneous \subsection e3x0_misc_multirx Multiple RX channels There are two complete DDC and DUC DSP chains in the FPGA. In the single channel case, -only one chain is ever used. To receive from both channels, the user must set the **RX** or **TX** +only one chain is ever used. To receive / transmit from both channels, the user must set the **RX** or **TX** subdevice specification. -In the following example, a TVRX2 is installed. -Channel 0 is sourced from subdevice **RX1**, -and channel 1 is sourced from subdevice **RX2** (**RX1** and **RX2** are antenna connectors on the TVRX2 daughterboard). +In the following example, a E310 MIMO XCVR is installed. +Channel 0 is sourced from subdevice **A**, +and channel 1 is sourced from subdevice **B** ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} -usrp->set_rx_subdev_spec("A:RX1 A:RX2"); +// assumes 'usrp' is a valid uhd::usrp::multi_usrp::sptr instance + +usrp->set_rx_subdev_spec("A:A A:B"); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ \subsection e3x0_misc_sensors Available Sensors @@ -296,7 +401,101 @@ they can be queried through the API. - **fe_locked** - rx / tx frontend pll locked - **temp** - processor temperature value -- Other sensors are added when the GPSDO is enabled +- **gps_time** and **gps_locked** sensors are added when the GPSDO is found + +\subsection e3x0_network_mode Network Mode + +Your USRP-E series device can be used in network mode for narrow band signal observation, evaluation and debugging purposes. + +Please note that when compared with normal operation as a standalone device the usable bandwidth is limited and therefore Network Mode is not the recommended mode of operation. + +In order to use the device in network mode it is necessary to start the *usrp_e3x0_network_mode* executable on the device. +In order to start the executable please log into your device either via SSH or serial console(see \ref e3x0_first_boot) and type + + $ usrp_e3x0_network_mode + +Your device should now be discoverable by your host computer via the usual UHD tools. If you are having trouble communicating with your device see the \ref e3x0_comm_problems section. + +\subsubsection e3x0_addressing Addressing the Device + +### Single device configuration + +In a single-device configuration, +the USRP device must have a unique IPv4 address on the host computer. +The USRP can be identified through its IPv4 address or resolvable hostname. +See the application notes on \ref page_identification. +Use this addressing scheme with the uhd::usrp::multi_usrp interface (not a typo!). + +Example device address string representation for a USRP-E Series device with IPv4 address 192.168.10.2: + + addr=192.168.10.2 + +### Multiple device configuration + +In a multi-device configuration, +each USRP device must have a unique IPv4 address on the host computer. +The device address parameter keys must be suffixed with the device index. +Each parameter key should be of the format \<key\>\<index\>. +Use this addressing scheme with the uhd::usrp::multi_usrp interface. + +- The order in which devices are indexed corresponds to the indexing of the transmit and receive channels. +- The key indexing provides the same granularity of device identification as in the single device case. + +Example device address string representation for 2 USRPs with IPv4 addresses **192.168.10.2** and **192.168.20.2**: + + addr0=192.168.10.2, addr1=192.168.20.2 + +\section e3x0_comm_problems Communication Problems + +When setting up a development machine for the first time, +you may have various difficulties communicating with the USRP device. +The following tips are designed to help narrow down and diagnose the problem. + +\subsection e3x0_comm_problems_runtimeerr RuntimeError: no control response + +This is a common error that occurs when you have set the subnet of your network +interface to a different subnet than the network interface of the USRP device. For +example, if your network interface is set to **192.168.20.1**, and the USRP device is **192.168.10.2** +(note the difference in the third numbers of the IP addresses), you +will likely see a 'no control response' error message. + +Fixing this is simple - just set the your host PC's IP address to the same +subnet as that of your USRP device. Instructions for setting your IP address are in the +previous section of this documentation. + +\subsection e3x0_comm_problems_firewall Firewall issues + +When the IP address is not specified, +the device discovery broadcasts UDP packets from each Ethernet interface. +Many firewalls will block the replies to these broadcast packets. +If disabling your system's firewall +or specifying the IP address yields a discovered device, +then your firewall may be blocking replies to UDP broadcast packets. +If this is the case, we recommend that you disable the firewall +or create a rule to allow all incoming packets with UDP source port **49152**. + +\subsection e3x0_comm_problems_ping Ping the device +The USRP device will reply to ICMP echo requests ("ping"). +A successful ping response means that the device has booted properly +and that it is using the expected IP address. + + ping 192.168.10.2 + +\subsection e3x0_comm_problems_monitor Monitor the host network traffic +Use Wireshark to monitor packets sent to and received from the device. + +\subsection e3x0_comm_problems_leds Observe Ethernet port LEDs +When there is network traffic arriving at the Ethernet port, LEDs will light up. +You can use this to make sure the network connection is correctly set up, e.g. +by pinging the USRP and making sure the LEDs start to blink. + + +\subsection e3x0 Frequently Asked Questions + + - Communication + -# How do I enable X forwarding so I can run X apps on the e3x0?\n + In the file `/etc/ssh/sshd_config`, unmcomment the line `#X11Forwarding no` + and change "no" to "yes". */ // vim:ft=doxygen: |
