diff options
| -rw-r--r-- | usrp2/opencores/zpu/core/zpu_config.vhd | 2 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/usrp2/opencores/zpu/core/zpu_config.vhd b/usrp2/opencores/zpu/core/zpu_config.vhd index 61949c592..796c5b75d 100644 --- a/usrp2/opencores/zpu/core/zpu_config.vhd +++ b/usrp2/opencores/zpu/core/zpu_config.vhd @@ -15,6 +15,6 @@ package zpu_config is -- start byte address of stack.
-- point to top of RAM - 2*words
- constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8";
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"0003ff8";
end zpu_config;
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 787aa4c2f..26e2cc4ab 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -321,13 +321,14 @@ module u2_core //assign bus_error = m0_err | m0_rty; + wire [63:0] zpu_status; zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(1'b1), // Data Wishbone bus to system bus fabric .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .interrupt(proc_int)); + .zpu_status(zpu_status), .interrupt(proc_int)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone |