diff options
| -rw-r--r-- | fpga/usrp2/sdr_lib/rx_frontend.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/sdr_lib/tx_frontend.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/u1e_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/N2x0/u2plus_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/USRP2/u2_core.v | 2 |
6 files changed, 8 insertions, 8 deletions
diff --git a/fpga/usrp2/sdr_lib/rx_frontend.v b/fpga/usrp2/sdr_lib/rx_frontend.v index 5b64737b2..ebe19240c 100644 --- a/fpga/usrp2/sdr_lib/rx_frontend.v +++ b/fpga/usrp2/sdr_lib/rx_frontend.v @@ -55,12 +55,12 @@ module rx_frontend add2_and_clip_reg #(.WIDTH(24)) add_clip_i (.clk(clk), .rst(rst), - .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1), .sum(i_out), .strobe_out()); add2_and_clip_reg #(.WIDTH(24)) add_clip_q (.clk(clk), .rst(rst), - .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1), .sum(q_out), .strobe_out()); end // if (IQCOMP_EN == 1) else diff --git a/fpga/usrp2/sdr_lib/tx_frontend.v b/fpga/usrp2/sdr_lib/tx_frontend.v index 17a6e35e0..dea8e010a 100644 --- a/fpga/usrp2/sdr_lib/tx_frontend.v +++ b/fpga/usrp2/sdr_lib/tx_frontend.v @@ -50,12 +50,12 @@ module tx_frontend add2_and_clip_reg #(.WIDTH(24)) add_clip_i (.clk(clk), .rst(rst), - .in1(tx_i), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .in1(tx_i), .in2(corr_i[35:12]), .strobe_in(1'b1), .sum(i_bal), .strobe_out()); add2_and_clip_reg #(.WIDTH(24)) add_clip_q (.clk(clk), .rst(rst), - .in1(tx_q), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .in1(tx_q), .in2(corr_q[35:12]), .strobe_in(1'b1), .sum(q_bal), .strobe_out()); // DC Offset diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 86bf747a0..c883c5ca8 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -391,7 +391,7 @@ module u1plus_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd8, 16'd0}; //major, minor + localparam compat_num = {16'd8, 16'd1}; //major, minor wire [31:0] reg_test32; diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v index 496a7ef4c..aede63bac 100644 --- a/fpga/usrp2/top/E1x0/u1e_core.v +++ b/fpga/usrp2/top/E1x0/u1e_core.v @@ -436,7 +436,7 @@ module u1e_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd8, 16'd0}; //major, minor + localparam compat_num = {16'd8, 16'd1}; //major, minor wire [31:0] reg_test32; diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index dd3d33b37..ba9569778 100644 --- a/fpga/usrp2/top/N2x0/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -435,7 +435,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd8, 16'd0}; //major, minor + localparam compat_num = {16'd8, 16'd1}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index d3524c304..bc651978d 100644 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -441,7 +441,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd8, 16'd0}; //major, minor + localparam compat_num = {16'd8, 16'd1}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), |