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-rw-r--r--usrp2/fifo/packet_router.v28
-rw-r--r--usrp2/top/u2_rev3/u2_core.v24
-rw-r--r--usrp2/vrt/vita_rx_chain.v16
-rw-r--r--usrp2/vrt/vita_rx_control.v2
-rw-r--r--usrp2/vrt/vita_rx_framer.v11
5 files changed, 26 insertions, 55 deletions
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
index e10a8f23d..edaa506b1 100644
--- a/usrp2/fifo/packet_router.v
+++ b/usrp2/fifo/packet_router.v
@@ -69,6 +69,8 @@ module packet_router
//setting register for mode control
wire [31:0] _sreg_mode_ctrl;
+ wire master_mode_flag;
+
setting_reg #(.my_addr(CTRL_BASE+0), .width(1)) sreg_mode_ctrl(
.clk(stream_clk),.rst(stream_rst),
.strobe(set_stb),.addr(set_addr),.in(set_data),
@@ -179,16 +181,11 @@ module packet_router
////////////////////////////////////////////////////////////////////
// Communication output source combiner (feeds UDP proto machine)
- // - DSP framer
+ // - DSP input
// - CPU input
// - ERR input
////////////////////////////////////////////////////////////////////
- //streaming signals from the dsp framer to the combiner
- wire [35:0] dsp0_frm_data, dsp1_frm_data;
- wire dsp0_frm_valid, dsp1_frm_valid;
- wire dsp0_frm_ready, dsp1_frm_ready;
-
//dummy signals to join the the muxes below
wire [35:0] _combiner0_data, _combiner1_data;
wire _combiner0_valid, _combiner1_valid;
@@ -205,8 +202,8 @@ module packet_router
fifo36_mux #(.prio(0)) // No priority, fair sharing
_com_output_combiner1(
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
- .data0_i(dsp0_frm_data), .src0_rdy_i(dsp0_frm_valid), .dst0_rdy_o(dsp0_frm_ready),
- .data1_i(dsp1_frm_data), .src1_rdy_i(dsp1_frm_valid), .dst1_rdy_o(dsp1_frm_ready),
+ .data0_i(dsp0_inp_data), .src0_rdy_i(dsp0_inp_valid), .dst0_rdy_o(dsp0_inp_ready),
+ .data1_i(dsp1_inp_data), .src1_rdy_i(dsp1_inp_valid), .dst1_rdy_o(dsp1_inp_ready),
.data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready)
);
@@ -462,21 +459,6 @@ module packet_router
);
////////////////////////////////////////////////////////////////////
- // DSP input framer
- ////////////////////////////////////////////////////////////////////
- dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(0)) dsp0_framer36(
- .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
- .data_i(dsp0_inp_data), .src_rdy_i(dsp0_inp_valid), .dst_rdy_o(dsp0_inp_ready),
- .data_o(dsp0_frm_data), .src_rdy_o(dsp0_frm_valid), .dst_rdy_i(dsp0_frm_ready)
- );
-
- dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(2)) dsp1_framer36(
- .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
- .data_i(dsp1_inp_data), .src_rdy_i(dsp1_inp_valid), .dst_rdy_o(dsp1_inp_ready),
- .data_o(dsp1_frm_data), .src_rdy_o(dsp1_frm_valid), .dst_rdy_i(dsp1_frm_ready)
- );
-
- ////////////////////////////////////////////////////////////////////
// UDP TX Protocol machine
////////////////////////////////////////////////////////////////////
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index 7504efeb3..eb07ed42f 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -569,8 +569,7 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
wire [31:0] sample_rx0;
- wire [35:0] rx0_data;
- wire clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy;
+ wire clear_rx0, strobe_rx0;
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
@@ -587,24 +586,18 @@ module u2_core
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
.out(),.changed(clear_rx0));
- vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0
+ vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
(.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
- .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy),
+ .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
.debug() );
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
- .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy),
- .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
-
// /////////////////////////////////////////////////////////////////////////
// DSP RX 1
wire [31:0] sample_rx1;
- wire [35:0] rx1_data;
- wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy;
+ wire clear_rx1, strobe_rx1;
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
@@ -621,19 +614,14 @@ module u2_core
.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
.out(),.changed(clear_rx1));
- vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1
+ vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(1),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
(.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
- .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy),
+ .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
.debug() );
- fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
- .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
- .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o));
-
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index f5578eb15..2410dcc37 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -1,6 +1,8 @@
module vita_rx_chain
- #(parameter BASE=0)
+ #(parameter BASE=0,
+ parameter UNIT=0,
+ parameter FIFOSIZE=10)
(input clk, input reset, input clear,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [63:0] vita_time, output overrun,
@@ -9,8 +11,8 @@ module vita_rx_chain
output [31:0] debug );
wire [100:0] sample_data;
- wire sample_dst_rdy, sample_src_rdy;
- wire [31:0] vrc_debug, vrf_debug;
+ wire sample_dst_rdy, sample_src_rdy;
+ wire [31:0] vrc_debug, vrf_debug;
vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control
(.clk(clk), .reset(reset), .clear(clear),
@@ -24,10 +26,14 @@ module vita_rx_chain
(.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.sample_fifo_i(sample_data), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy),
- .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i),
- .fifo_occupied(), .fifo_full(), .fifo_empty(),
+ .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int),
.debug_rx(vrf_debug) );
+ dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36
+ (.clk(clk), .reset(reset), .clear(clear),
+ .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int),
+ .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) );
+
assign debug = vrc_debug; // | vrf_debug;
endmodule // vita_rx_chain
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v
index 0769f3a24..4c0cef50d 100644
--- a/usrp2/vrt/vita_rx_control.v
+++ b/usrp2/vrt/vita_rx_control.v
@@ -196,4 +196,4 @@ module vita_rx_control
{ go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl },
{ 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
-endmodule // rx_control
+endmodule // vita_rx_control
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index bce8fe334..04b636778 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -15,11 +15,6 @@ module vita_rx_framer
input sample_fifo_src_rdy_i,
output sample_fifo_dst_rdy_o,
- // FIFO Levels
- output [15:0] fifo_occupied,
- output fifo_full,
- output fifo_empty,
-
output [31:0] debug_rx
);
@@ -200,8 +195,8 @@ module vita_rx_framer
(.clk(clk), .reset(reset), .clear(clear),
.datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy),
.dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
- .space(),.occupied(fifo_occupied[4:0]) );
- assign fifo_occupied[15:5] = 0;
+ .space(),.occupied() );
+
assign data_o[35:34] = 2'b00; // Always write full lines
assign sample_fifo_dst_rdy_o = pkt_fifo_rdy &
( ((vita_state==VITA_PAYLOAD) &
@@ -211,4 +206,4 @@ module vita_rx_framer
assign debug_rx = vita_state;
-endmodule // rx_control
+endmodule // vita_rx_framer
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 02:19:31 +0000