diff options
| -rw-r--r-- | host/lib/usrp/usrp2/dboard_impl.cpp | 5 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/dboard_interface.cpp | 15 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/dsp_impl.cpp | 23 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 19 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 112 |
5 files changed, 67 insertions, 107 deletions
diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp index 86ee52594..29fb32eeb 100644 --- a/host/lib/usrp/usrp2/dboard_impl.cpp +++ b/host/lib/usrp/usrp2/dboard_impl.cpp @@ -20,7 +20,6 @@ #include "usrp2_regs.hpp" #include <uhd/utils/assert.hpp> #include <boost/format.hpp> -#include <cstddef> using namespace uhd; using namespace uhd::usrp; @@ -80,7 +79,7 @@ void usrp2_impl::update_rx_mux_config(void){ rx_mux = (((rx_mux >> 0) & 0x3) << 2) | (((rx_mux >> 2) & 0x3) << 0); } - this->poke(offsetof(dsp_rx_regs_t, rx_mux) + DSP_RX_BASE, rx_mux); + this->poke(FR_DSP_RX_MUX, rx_mux); } void usrp2_impl::update_tx_mux_config(void){ @@ -93,7 +92,7 @@ void usrp2_impl::update_tx_mux_config(void){ tx_mux = (((tx_mux >> 0) & 0x1) << 1) | (((tx_mux >> 1) & 0x1) << 0); } - this->poke(offsetof(dsp_tx_regs_t, tx_mux) + DSP_TX_BASE, tx_mux); + this->poke(FR_DSP_TX_MUX, tx_mux); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/dboard_interface.cpp b/host/lib/usrp/usrp2/dboard_interface.cpp index f5fe68152..4160ad467 100644 --- a/host/lib/usrp/usrp2/dboard_interface.cpp +++ b/host/lib/usrp/usrp2/dboard_interface.cpp @@ -21,7 +21,6 @@ #include <uhd/utils/assert.hpp> #include <boost/assign/list_of.hpp> #include <algorithm> -#include <cstddef> using namespace uhd::usrp; @@ -103,22 +102,22 @@ void usrp2_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t valu | (boost::uint32_t(value) << shift); //or'ed in the new bits //poke in the value and shadow - _impl->poke(offsetof(gpio_regs_t, ddr) + 0xC800, new_ddr_val); + _impl->poke(FR_GPIO_DDR, new_ddr_val); _ddr_shadow = new_ddr_val; } boost::uint16_t usrp2_dboard_interface::read_gpio(gpio_bank_t bank){ - boost::uint32_t data = _impl->peek(offsetof(gpio_regs_t, io) + 0xC800); + boost::uint32_t data = _impl->peek(FR_GPIO_IO); return boost::uint16_t(data >> bank_to_shift(bank)); } void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost::uint16_t value){ //map the atr reg to an offset in register space - static const uhd::dict<atr_reg_t, int> reg_to_offset = boost::assign::map_list_of - (ATR_REG_IDLE, ATR_IDLE) (ATR_REG_TXONLY, ATR_TX) - (ATR_REG_RXONLY, ATR_RX) (ATR_REG_BOTH, ATR_FULL) + static const uhd::dict<atr_reg_t, int> reg_to_addr = boost::assign::map_list_of + (ATR_REG_IDLE, FR_ATR_IDLE) (ATR_REG_TXONLY, FR_ATR_TX) + (ATR_REG_RXONLY, FR_ATR_RX) (ATR_REG_BOTH, FR_ATR_FULL) ; - int offset = reg_to_offset[reg]; + ASSERT_THROW(reg_to_addr.has_key(reg)); //ensure a value exists in the shadow if (not _atr_reg_shadows.has_key(reg)) _atr_reg_shadows[reg] = 0; @@ -130,7 +129,7 @@ void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost: | (boost::uint32_t(value) << shift); //or'ed in the new bits //poke in the value and shadow - _impl->poke(offsetof(atr_regs_t, v) + 0xE400 + offset, new_atr_val); + _impl->poke(reg_to_addr[reg], new_atr_val); _atr_reg_shadows[reg] = new_atr_val; } diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp index 6edfec61a..d50c1ad56 100644 --- a/host/lib/usrp/usrp2/dsp_impl.cpp +++ b/host/lib/usrp/usrp2/dsp_impl.cpp @@ -21,7 +21,6 @@ #include <boost/format.hpp> #include <boost/assign/list_of.hpp> #include <boost/math/special_functions/round.hpp> -#include <cstddef> using namespace uhd; @@ -75,14 +74,11 @@ void usrp2_impl::init_ddc_config(void){ void usrp2_impl::update_ddc_config(void){ //set the decimation - this->poke( - offsetof(dsp_rx_regs_t, decim_rate) + DSP_RX_BASE, _ddc_decim - ); + this->poke(FR_DSP_RX_DECIM_RATE, _ddc_decim); //set the scaling static const boost::int16_t default_rx_scale_iq = 1024; - this->poke( - offsetof(dsp_rx_regs_t, scale_iq) + DSP_RX_BASE, + this->poke(FR_DSP_RX_SCALE_IQ, calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); } @@ -174,8 +170,7 @@ void usrp2_impl::ddc_set(const wax::obj &key, const wax::obj &val){ ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0); ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0); _ddc_freq = new_freq; //shadow - this->poke( //set the cordic - offsetof(dsp_rx_regs_t, freq) + DSP_RX_BASE, + this->poke(FR_DSP_RX_FREQ, calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq()) ); return; @@ -216,15 +211,10 @@ void usrp2_impl::update_duc_config(void){ boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed)); //set the interpolation - this->poke( - offsetof(dsp_tx_regs_t, interp_rate) + DSP_TX_BASE, _ddc_decim - ); + this->poke(FR_DSP_TX_INTERP_RATE, _ddc_decim); //set the scaling - this->poke( - offsetof(dsp_tx_regs_t, scale_iq) + DSP_TX_BASE, - calculate_iq_scale_word(scale, scale) - ); + this->poke(FR_DSP_TX_SCALE_IQ, calculate_iq_scale_word(scale, scale)); } /*********************************************************************** @@ -298,8 +288,7 @@ void usrp2_impl::duc_set(const wax::obj &key, const wax::obj &val){ ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0); ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0); _duc_freq = new_freq; //shadow - this->poke( //set the cordic - offsetof(dsp_tx_regs_t, freq) + DSP_TX_BASE, + this->poke(FR_DSP_TX_FREQ, calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq()) ); return; diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index eff53c5b2..7b658b22d 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -20,7 +20,6 @@ #include <uhd/utils/assert.hpp> #include <uhd/types/mac_addr.hpp> #include <uhd/types/dict.hpp> -#include <cstddef> using namespace uhd; @@ -53,32 +52,32 @@ void usrp2_impl::update_clock_config(void){ //translate pps source enums switch(_clock_config.pps_source){ - case clock_config_t::PPS_SMA: pps_flags |= PPS_FLAG_SMA; break; - case clock_config_t::PPS_MIMO: pps_flags |= PPS_FLAG_MIMO; break; + case clock_config_t::PPS_SMA: pps_flags |= FRF_TIME64_PPS_SMA; break; + case clock_config_t::PPS_MIMO: pps_flags |= FRF_TIME64_PPS_MIMO; break; default: throw std::runtime_error("usrp2: unhandled clock configuration pps source"); } //translate pps polarity enums switch(_clock_config.pps_polarity){ - case clock_config_t::PPS_POS: pps_flags |= PPS_FLAG_POSEDGE; break; - case clock_config_t::PPS_NEG: pps_flags |= PPS_FLAG_NEGEDGE; break; + case clock_config_t::PPS_POS: pps_flags |= FRF_TIME64_PPS_POSEDGE; break; + case clock_config_t::PPS_NEG: pps_flags |= FRF_TIME64_PPS_NEGEDGE; break; default: throw std::runtime_error("usrp2: unhandled clock configuration pps polarity"); } //set the pps flags - this->poke(offsetof(sr_time64_t, flags) + TIME64_BASE, pps_flags); + this->poke(FR_TIME64_FLAGS, pps_flags); //TODO clock source ref 10mhz (spi ad9510) } void usrp2_impl::set_time_spec(const time_spec_t &time_spec, bool now){ //set ticks and seconds - this->poke(offsetof(sr_time64_t, secs) + TIME64_BASE, time_spec.secs); - this->poke(offsetof(sr_time64_t, ticks) + TIME64_BASE, time_spec.ticks); + this->poke(FR_TIME64_SECS, time_spec.secs); + this->poke(FR_TIME64_TICKS, time_spec.ticks); //set the register to latch it all in - boost::uint32_t imm_flags = (now)? TIME64_LATCH_NOW : TIME64_LATCH_NEXT_PPS; - this->poke(offsetof(sr_time64_t, imm) + TIME64_BASE, imm_flags); + boost::uint32_t imm_flags = (now)? FRF_TIME64_LATCH_NOW : FRF_TIME64_LATCH_NEXT_PPS; + this->poke(FR_TIME64_IMM, imm_flags); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index b7fd239a6..10545d712 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -28,10 +28,10 @@ #define MISC_OUTPUT_BASE 0xD400 -#define TX_PROTOCOL_ENGINE_BASE 0xD480 -#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 -#define BUFFER_POOL_CTRL_BASE 0xD500 -#define LAST_SETTING_REG 0xD7FC // last valid setting register +//#define TX_PROTOCOL_ENGINE_BASE 0xD480 +//#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 +//#define BUFFER_POOL_CTRL_BASE 0xD500 +//#define LAST_SETTING_REG 0xD7FC // last valid setting register #define SR_MISC 0 #define SR_TX_PROT_ENG 32 @@ -46,7 +46,7 @@ #define SR_SIMTIMER 198 #define SR_LAST 255 -#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) +#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(boost::uint32_t)) ///////////////////////////////////////////////// // SPI Slave Constants @@ -64,9 +64,6 @@ ///////////////////////////////////////////////// // VITA49 64 bit time (write only) //////////////////////////////////////////////// - -#define TIME64_BASE _SR_ADDR(SR_TIME64) - /*! * \brief Time 64 flags * @@ -83,34 +80,27 @@ * * </pre> */ -typedef struct { - boost::uint32_t secs; // value to set absolute secs to on next PPS - boost::uint32_t ticks; // value to set absolute ticks to on next PPS - boost::uint32_t flags; // flags - see chart above - boost::uint32_t imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0) -} sr_time64_t; +#define FR_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS +#define FR_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS +#define FR_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above +#define FR_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) //pps flags (see above) -#define PPS_FLAG_NEGEDGE (0 << 0) -#define PPS_FLAG_POSEDGE (1 << 0) -#define PPS_FLAG_SMA (0 << 1) -#define PPS_FLAG_MIMO (1 << 1) +#define FRF_TIME64_PPS_NEGEDGE (0 << 0) +#define FRF_TIME64_PPS_POSEDGE (1 << 0) +#define FRF_TIME64_PPS_SMA (0 << 1) +#define FRF_TIME64_PPS_MIMO (1 << 1) -#define TIME64_LATCH_NOW 1 -#define TIME64_LATCH_NEXT_PPS 0 +#define FRF_TIME64_LATCH_NOW 1 +#define FRF_TIME64_LATCH_NEXT_PPS 0 ///////////////////////////////////////////////// // DSP TX Regs //////////////////////////////////////////////// +#define FR_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0) +#define FR_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q} +#define FR_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2) -#define DSP_TX_BASE _SR_ADDR(SR_TX_DSP) - -typedef struct { - boost::int32_t freq; - boost::uint32_t scale_iq; // {scale_i,scale_q} - boost::uint32_t interp_rate; - boost::uint32_t _padding0; // padding for the tx_mux - // NOT freq, scale, interp /*! * \brief output mux configuration. * @@ -145,24 +135,17 @@ typedef struct { * The default value is 0x10 * </pre> */ - boost::uint32_t tx_mux; - -} dsp_tx_regs_t; +#define FR_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4) ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// - -#define DSP_RX_BASE _SR_ADDR(SR_RX_DSP) - -typedef struct { - boost::int32_t freq; - boost::uint32_t scale_iq; // {scale_i,scale_q} - boost::uint32_t decim_rate; - boost::uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode, using lower 14 bits, - // otherwise it is automatic - boost::uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode, using lower 14 bits - +#define FR_DSP_RX_FREQ _SR_ADDR(SR_RX_DSP + 0) +#define FR_DSP_RX_SCALE_IQ _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q} +#define FR_DSP_RX_DECIM_RATE _SR_ADDR(SR_RX_DSP + 2) +#define FR_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits, + // otherwise it is automatic +#define FR_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits /*! * \brief input mux configuration. * @@ -184,42 +167,33 @@ typedef struct { * The default value is 0x4 * </pre> */ - boost::uint32_t rx_mux; // called adc_mux in dsp_core_rx.v - -} dsp_rx_regs_t; +#define FR_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v //////////////////////////////////////////////// // GPIO, Slave 4 +//////////////////////////////////////////////// // // These go to the daughterboard i/o pins - -#define GPIO_BASE 0xC800 - -typedef struct { - boost::uint32_t io; // tx data in high 16, rx in low 16 - boost::uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 - boost::uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB - boost::uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB -} gpio_regs_t; +// +#define _FR_GPIO_ADDR(off) (0xC800 + (off) * sizeof(boost::uint32_t)) +#define FR_GPIO_IO _FR_GPIO_ADDR(0) // tx data in high 16, rx in low 16 +#define FR_GPIO_DDR _FR_GPIO_ADDR(1) // 32 bits, 1 means output. tx in high 16, rx in low 16 +#define FR_GPIO_TX_SEL _FR_GPIO_ADDR(2) // 16 2-bit fields select which source goes to TX DB +#define FR_GPIO_RX_SEL _FR_GPIO_ADDR(3) // 16 2-bit fields select which source goes to RX DB // each 2-bit sel field is layed out this way -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric +#define FRF_GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define FRF_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define FRF_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define FRF_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric /////////////////////////////////////////////////// // ATR Controller, Slave 11 - -#define ATR_BASE 0xE400 - -typedef struct { - boost::uint32_t v[16]; -} atr_regs_t; - -#define ATR_IDLE 0x0 // indicies into v -#define ATR_TX 0x1 -#define ATR_RX 0x2 -#define ATR_FULL 0x3 +//////////////////////////////////////////////// +#define _FR_ATR_ADDR(off) (0xE400 + (off) * sizeof(boost::uint32_t)) +#define FR_ATR_IDLE _FR_ATR_ADDR(0) // tx data in high 16, rx in low 16 +#define FR_ATR_TX _FR_ATR_ADDR(1) +#define FR_ATR_RX _FR_ATR_ADDR(2) +#define FR_ATR_FULL _FR_ATR_ADDR(3) #endif /* INCLUDED_USRP2_REGS_HPP */ |