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-rw-r--r--host/CMakeLists.txt2
-rw-r--r--host/apps/omap_debug/usrp-e-crc-rw.c143
-rw-r--r--host/apps/omap_debug/usrp-e-mm-loopback.c2
-rw-r--r--host/apps/omap_debug/usrp_e.h11
-rw-r--r--host/lib/usrp/usrp_e100/clock_ctrl.cpp275
-rw-r--r--host/lib/usrp/usrp_e100/clock_ctrl.hpp7
-rw-r--r--host/lib/usrp/usrp_e100/usrp_e100_regs.hpp86
-rw-r--r--host/usrp_e_utils/CMakeLists.txt51
-rw-r--r--host/usrp_e_utils/clkgen-config.cpp305
-rw-r--r--host/usrp_e_utils/fpga-downloader.cpp (renamed from host/utils/fpga-downloader.cpp)0
-rw-r--r--host/usrp_e_utils/usrp-e-debug-pins.c (renamed from host/utils/usrp-e-debug-pins.c)0
-rw-r--r--host/usrp_e_utils/usrp-e-i2c.c (renamed from host/utils/usrp-e-i2c.c)0
-rw-r--r--host/usrp_e_utils/usrp-e-loopback.c (renamed from host/utils/usrp-e-loopback.c)0
-rw-r--r--host/usrp_e_utils/usrp-e-spi.c (renamed from host/utils/usrp-e-spi.c)0
-rw-r--r--host/usrp_e_utils/usrp-e-wb-test.cpp115
-rw-r--r--host/utils/CMakeLists.txt16
-rw-r--r--host/utils/clkgen-config.cpp296
17 files changed, 838 insertions, 471 deletions
diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt
index e64c1031f..6b2ac4e64 100644
--- a/host/CMakeLists.txt
+++ b/host/CMakeLists.txt
@@ -183,6 +183,8 @@ IF(ENABLE_UTILS)
ADD_SUBDIRECTORY(utils)
ENDIF(ENABLE_UTILS)
+ADD_SUBDIRECTORY(usrp_e_utils)
+
########################################################################
# Print Summary
########################################################################
diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c
index c3ae45cc1..9e3e7eb5d 100644
--- a/host/apps/omap_debug/usrp-e-crc-rw.c
+++ b/host/apps/omap_debug/usrp-e-crc-rw.c
@@ -8,11 +8,19 @@
#include <stdlib.h>
#include <unistd.h>
#include <stddef.h>
+#include <poll.h>
+#include <sys/mman.h>
#include "usrp_e.h"
// max length #define PKT_DATA_LENGTH 1016
static int packet_data_length;
+struct ring_buffer_info (*rxi)[];
+struct ring_buffer_info (*txi)[];
+__u8 *rx_buf;
+__u8 *tx_buf;
+static struct usrp_e_ring_buffer_size_t rb_size;
+
static int fp;
static u_int32_t crc_tab[256];
@@ -44,8 +52,7 @@ static u_int32_t chksum_crc32_gentab(void)
static void *read_thread(void *threadid)
{
int cnt;
- struct usrp_transfer_frame *rx_data;
- int rx_pkt_cnt;
+ int rx_pkt_cnt, rb_read;
int i;
unsigned long crc;
unsigned int rx_crc;
@@ -53,70 +60,54 @@ static void *read_thread(void *threadid)
struct timeval start_time, finish_time;
__u8 *p;
- __u32 *pi;
printf("Greetings from the reading thread!\n");
// IMPORTANT: must assume max length packet from fpga
- rx_data = malloc(2048);
-
+
rx_pkt_cnt = 0;
+ rb_read = 0;
bytes_transfered = 0;
gettimeofday(&start_time, NULL);
while (1) {
- cnt = read(fp, rx_data, 2048);
- if (cnt < 0)
- printf("Error returned from read: %d\n", cnt);
-
- rx_pkt_cnt++;
-
-#if 0
- if (rx_pkt_cnt == 512) {
- printf(".");
- fflush(stdout);
- rx_pkt_cnt = 0;
+ while (!((*rxi)[rb_read].flags & RB_USER)) {
+ struct pollfd pfd;
+ pfd.fd = fp;
+ pfd.events = POLLIN;
+ ssize_t ret = poll(&pfd, 1, -1);
}
-#endif
+ (*rxi)[rb_read].flags = RB_USER_PROCESS;
- if (rx_data->status & RB_OVERRUN)
- printf("O");
-
- printf("rx_data->len = %d\n", rx_data->len);
+ rx_pkt_cnt++;
+ cnt = (*rxi)[rb_read].len;
+ p = rx_buf + (rb_read * 2048);
-
+ rx_crc = *(int *) &p[cnt-4];
crc = 0xFFFFFFFF;
- for (i = 0; i < rx_data->len - 4; i+=2) {
+ for (i = 0; i < cnt - 4; i+=2) {
crc = ((crc >> 8) & 0x00FFFFFF) ^
- crc_tab[(crc ^ rx_data->buf[i+1]) & 0xFF];
-printf("idx = %d, data = %X, crc = %X\n", i, rx_data->buf[i+1],crc);
+ crc_tab[(crc ^ p[i+1]) & 0xFF];
+//printf("idx = %d, data = %X, crc = %X\n", i, p[i+1],crc);
crc = ((crc >> 8) & 0x00FFFFFF) ^
- crc_tab[(crc ^ rx_data->buf[i]) & 0xFF];
-printf("idx = %d, data = %X, crc = %X\n", i, rx_data->buf[i],crc);
+ crc_tab[(crc ^ p[i]) & 0xFF];
+//printf("idx = %d, data = %X, crc = %X\n", i, p[i],crc);
}
- p = &rx_data->buf[rx_data->len - 4];
- pi = (__u32 *) p;
- rx_crc = *pi;
-
-#if 1
- printf("rx_data->len = %d\n", rx_data->len);
- printf("rx_data->status = %d\n", rx_data->status);
- for (i = 0; i < rx_data->len; i++)
- printf("idx = %d, data = %X\n", i, rx_data->buf[i]);
- printf("calc crc = %lX, rx crc = %X\n", crc, rx_crc);
- fflush(stdout);
- break;
-#endif
+ (*rxi)[rb_read].flags = RB_KERNEL;
if (rx_crc != (crc & 0xFFFFFFFF)) {
printf("CRC Error, calc crc: %X, rx_crc: %X\n",
(crc & 0xFFFFFFFF), rx_crc);
}
- bytes_transfered += rx_data->len;
+ rb_read++;
+ if (rb_read == rb_size.num_rx_frames)
+ rb_read = 0;
+
+ bytes_transfered += cnt;
if (bytes_transfered > (100 * 1000000)) {
gettimeofday(&finish_time, NULL);
@@ -135,17 +126,17 @@ printf("idx = %d, data = %X, crc = %X\n", i, rx_data->buf[i],crc);
static void *write_thread(void *threadid)
{
- int seq_number, i, cnt, tx_pkt_cnt;
+ int i, tx_pkt_cnt, rb_write;
int tx_len;
unsigned long crc;
- struct usrp_transfer_frame *tx_data;
unsigned long bytes_transfered, elapsed_seconds;
struct timeval start_time, finish_time;
+ __u8 *p;
printf("Greetings from the write thread!\n");
+ rb_write = 0;
tx_pkt_cnt = 0;
- tx_data = malloc(2048);
bytes_transfered = 0;
gettimeofday(&start_time, NULL);
@@ -153,6 +144,14 @@ static void *write_thread(void *threadid)
while (1) {
tx_pkt_cnt++;
+ p = tx_buf + (rb_write * 2048);
+
+// printf("p = %p\n", p);
+
+ if (packet_data_length > 0)
+ tx_len = packet_data_length;
+ else
+ tx_len = (random() & 0x1ff) + (2044 - 512);
#if 0
if (tx_pkt_cnt == 512) {
@@ -170,25 +169,33 @@ static void *write_thread(void *threadid)
}
#endif
- tx_len = 2048 - sizeof(struct usrp_transfer_frame) - sizeof(int);
- tx_data->len = tx_len + sizeof(int);
+// printf("Checking for space at rb entry = %d\n", rb_write);
+ while (!((*txi)[rb_write].flags & RB_KERNEL)) {
+ struct pollfd pfd;
+ pfd.fd = fp;
+ pfd.events = POLLOUT;
+ ssize_t ret = poll(&pfd, 1, -1);
+ }
+// printf("Got space\n");
crc = 0xFFFFFFFF;
- for (i = 0; i < tx_len; i++) {
- tx_data->buf[i] = i & 0xFF;
+ for (i = 0; i < tx_len-4; i++) {
+ p[i] = i & 0xFF;
crc = ((crc >> 8) & 0x00FFFFFF) ^
- crc_tab[(crc ^ tx_data->buf[i]) & 0xFF];
+ crc_tab[(crc ^ p[i]) & 0xFF];
}
- *((int *) &tx_data[tx_len]) = crc;
+ *(int *) &p[tx_len-4] = crc;
- cnt = write(fp, tx_data, 2048);
- if (cnt < 0)
- printf("Error returned from write: %d\n", cnt);
+ (*txi)[rb_write].len = tx_len;
+ (*txi)[rb_write].flags = RB_USER;
+ rb_write++;
+ if (rb_write == rb_size.num_tx_frames)
+ rb_write = 0;
- bytes_transfered += tx_data->len;
+ bytes_transfered += tx_len;
if (bytes_transfered > (100 * 1000000)) {
gettimeofday(&finish_time, NULL);
@@ -196,7 +203,7 @@ static void *write_thread(void *threadid)
printf("Bytes transfered = %d, elapsed seconds = %d\n", bytes_transfered, elapsed_seconds);
printf("TX data transfer rate = %f K Samples/second\n",
- (float) bytes_transfered / (float) elapsed_seconds / 250);
+ (float) bytes_transfered / (float) elapsed_seconds / 4000);
start_time = finish_time;
@@ -213,6 +220,9 @@ int main(int argc, char *argv[])
pthread_t tx, rx;
long int t;
int fpga_config_flag ,decimation;
+ int ret, map_size, page_size;
+ void *rb;
+
struct usrp_e_ctl16 d;
struct sched_param s = {
.sched_priority = 1
@@ -231,6 +241,29 @@ int main(int argc, char *argv[])
fp = open("/dev/usrp_e0", O_RDWR);
printf("fp = %d\n", fp);
+ page_size = getpagesize();
+
+ ret = ioctl(fp, USRP_E_GET_RB_INFO, &rb_size);
+
+ map_size = (rb_size.num_pages_rx_flags + rb_size.num_pages_tx_flags) * page_size +
+ (rb_size.num_rx_frames + rb_size.num_tx_frames) * (page_size >> 1);
+
+ rb = mmap(0, map_size, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0);
+ if (rb == MAP_FAILED) {
+ perror("mmap failed");
+ return -1;
+ }
+
+ printf("rb = %X\n", rb);
+
+ rxi = rb;
+ rx_buf = rb + (rb_size.num_pages_rx_flags * page_size);
+ txi = rb + (rb_size.num_pages_rx_flags * page_size) +
+ (rb_size.num_rx_frames * page_size >> 1);
+ tx_buf = rb + (rb_size.num_pages_rx_flags * page_size) +
+ (rb_size.num_rx_frames * page_size >> 1) +
+ (rb_size.num_pages_tx_flags * page_size);
+
fpga_config_flag = 0;
if (strcmp(argv[1], "w") == 0)
fpga_config_flag |= (1 << 15);
diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c
index f5fc83c87..b67eecd21 100644
--- a/host/apps/omap_debug/usrp-e-mm-loopback.c
+++ b/host/apps/omap_debug/usrp-e-mm-loopback.c
@@ -75,6 +75,8 @@ static void *read_thread(void *threadid)
ssize_t ret = poll(&pfd, 1, -1);
}
+ (*rxi)[rb_read].flags = RB_USER_PROCESS;
+
// printf("pkt received, rb_read = %d\n", rb_read);
cnt = (*rxi)[rb_read].len;
diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h
index f96706c4a..4c6a5dd89 100644
--- a/host/apps/omap_debug/usrp_e.h
+++ b/host/apps/omap_debug/usrp_e.h
@@ -34,16 +34,13 @@ struct usrp_e_ctl32 {
#define UE_SPI_TXRX 1
/* Defines for spi ctrl register */
-#define UE_SPI_CTRL_TXNEG (BIT(10))
-#define UE_SPI_CTRL_RXNEG (BIT(9))
+#define UE_SPI_CTRL_TXNEG (1<<10)
+#define UE_SPI_CTRL_RXNEG (1<<9)
#define UE_SPI_PUSH_RISE 0
#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG
#define UE_SPI_LATCH_RISE 0
#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG
-#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28)
-
-#define USRP_E_COMPAT_NUMBER 1
struct usrp_e_spi {
__u8 readback;
@@ -68,12 +65,16 @@ struct usrp_e_i2c {
#define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c)
#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c)
#define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t)
+#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28)
+
+#define USRP_E_COMPAT_NUMBER 1
/* Flag defines */
#define RB_USER (1<<0)
#define RB_KERNEL (1<<1)
#define RB_OVERRUN (1<<2)
#define RB_DMA_ACTIVE (1<<3)
+#define RB_USER_PROCESS (1<<4)
struct ring_buffer_info {
int flags;
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
index 1fb1a7125..dd7f8507b 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
@@ -1,5 +1,5 @@
//
-// Copyright 2010 Ettus Research LLC
+// Copyright 2010-2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -22,11 +22,25 @@
#include "usrp_e100_regs.hpp" //spi slave constants
#include <boost/assign/list_of.hpp>
#include <boost/foreach.hpp>
+#include <boost/format.hpp>
+#include <boost/operators.hpp>
+#include <boost/math/common_factor_rt.hpp> //gcd
+#include <algorithm>
#include <utility>
#include <iostream>
using namespace uhd;
+/***********************************************************************
+ * Constants
+ **********************************************************************/
+static const bool ENABLE_THE_TEST_OUT = false;
+static const double REFERENCE_INPUT_RATE = 10e6;
+static const double DEFAULT_OUTPUT_RATE = 64e6;
+
+/***********************************************************************
+ * Helpers
+ **********************************************************************/
template <typename div_type, typename bypass_type> static void set_clock_divider(
size_t divider, div_type &low, div_type &high, bypass_type &bypass
){
@@ -36,24 +50,80 @@ template <typename div_type, typename bypass_type> static void set_clock_divider
}
/***********************************************************************
- * Constants
+ * Clock rate calculation stuff:
+ * Using the internal VCO between 1400 and 1800 MHz
**********************************************************************/
-static const bool enable_test_clock = false;
-static const size_t ref_clock_doubler = 2; //enabled below
-static const double ref_clock_rate = 10e6 * ref_clock_doubler;
+struct clock_settings_type : boost::totally_ordered<clock_settings_type>{
+ size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider;
+ size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;}
+ double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;}
+ double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();}
+ double get_chan_rate(void) const{return get_vco_rate()/vco_divider;}
+ double get_out_rate(void) const{return get_chan_rate()/chan_divider;}
+ std::string to_pp_string(void) const{
+ return str(boost::format(
+ " r_counter: %d\n"
+ " a_counter: %d\n"
+ " b_counter: %d\n"
+ " prescaler: %d\n"
+ " vco_divider: %d\n"
+ " chan_divider: %d\n"
+ " vco_rate: %fMHz\n"
+ " chan_rate: %fMHz\n"
+ " out_rate: %fMHz\n"
+ )
+ % r_counter
+ % a_counter
+ % b_counter
+ % prescaler
+ % vco_divider
+ % chan_divider
+ % (get_vco_rate()/1e6)
+ % (get_chan_rate()/1e6)
+ % (get_out_rate()/1e6)
+ );
+ }
+};
-static const size_t r_counter = 1;
-static const size_t a_counter = 0;
-static const size_t b_counter = 20 / ref_clock_doubler;
-static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz
-static const size_t vco_divider = 5; //set below with enum
+bool operator<(const clock_settings_type &lhs, const clock_settings_type &rhs){
+ if (lhs.get_out_rate() != rhs.get_out_rate()) //sort small to large out rates
+ return lhs.get_out_rate() < rhs.get_out_rate();
-static const size_t n_counter = prescaler * b_counter + a_counter;
-static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz
-static const double master_clock_rate = vco_clock_rate/vco_divider;
+ if (lhs.r_counter != rhs.r_counter) //sort small to large r dividers
+ return lhs.r_counter < rhs.r_counter;
+
+ if (lhs.get_vco_rate() != rhs.get_vco_rate()) //sort large to small vco rates
+ return lhs.get_vco_rate() > rhs.get_vco_rate();
+
+ return false; //whatever case
+}
-static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6);
-static const size_t codec_clock_divider = size_t(master_clock_rate/64e6);
+static std::vector<clock_settings_type> _get_clock_settings(void){
+ std::vector<clock_settings_type> clock_settings;
+
+ clock_settings_type cs;
+ cs.ref_clock_doubler = 2; //always doubling
+ cs.prescaler = 8; //set to 8 when input is under 2400 MHz
+
+ for (cs.r_counter = 1; cs.r_counter <= 3; cs.r_counter++){
+ for (cs.b_counter = 3; cs.b_counter <= 10; cs.b_counter++){
+ for (cs.a_counter = 0; cs.a_counter <= 10; cs.a_counter++){
+ for (cs.vco_divider = 2; cs.vco_divider <= 6; cs.vco_divider++){
+ for (cs.chan_divider = 1; cs.chan_divider <= 32; cs.chan_divider++){
+ if (cs.get_vco_rate() > 1800e6) continue;
+ if (cs.get_vco_rate() < 1400e6) continue;
+ if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface
+ clock_settings.push_back(cs);
+ }}}}}
+
+ std::sort(clock_settings.begin(), clock_settings.end());
+ return clock_settings;
+}
+
+static std::vector<clock_settings_type> &get_clock_settings(void){
+ static std::vector<clock_settings_type> clock_settings = _get_clock_settings();
+ return clock_settings;
+}
/***********************************************************************
* Clock Control Implementation
@@ -62,35 +132,70 @@ class usrp_e100_clock_ctrl_impl : public usrp_e100_clock_ctrl{
public:
usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface){
_iface = iface;
+ _chan_rate = 0.0;
+ _out_rate = 0.0;
//init the clock gen registers
//Note: out0 should already be clocking the FPGA or this isnt going to work
_ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO;
_ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler
_ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin
- _ad9522_regs.status_pin_control = 0x1; //n divider
+ _ad9522_regs.status_pin_control = 0x2; //r divider
_ad9522_regs.ld_pin_control = 0x00; //dld
_ad9522_regs.refmon_pin_control = 0x12; //show ref2
+ _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_255CYC;
- _ad9522_regs.enable_ref2 = 1;
- _ad9522_regs.enable_ref1 = 0;
- _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2;
+ this->use_internal_ref();
+
+ this->set_fpga_clock_rate(DEFAULT_OUTPUT_RATE); //initialize to something
+
+ this->enable_test_clock(ENABLE_THE_TEST_OUT);
+ this->enable_rx_dboard_clock(false);
+ this->enable_tx_dboard_clock(false);
+ }
+
+ ~usrp_e100_clock_ctrl_impl(void){
+ this->enable_test_clock(ENABLE_THE_TEST_OUT);
+ this->enable_rx_dboard_clock(false);
+ this->enable_tx_dboard_clock(false);
+ }
- _ad9522_regs.set_r_counter(r_counter);
- _ad9522_regs.a_counter = a_counter;
- _ad9522_regs.set_b_counter(b_counter);
+ /***********************************************************************
+ * Clock rate control:
+ * - set clock rate w/ internal VCO
+ * - set clock rate w/ external VCXO
+ **********************************************************************/
+ void set_clock_settings_with_internal_vco(const clock_settings_type &cs){
+ //set the rates to private variables so the implementation knows!
+ _chan_rate = cs.get_chan_rate();
+ _out_rate = cs.get_out_rate();
+
+ _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0;
+
+ _ad9522_regs.set_r_counter(cs.r_counter);
+ _ad9522_regs.a_counter = cs.a_counter;
+ _ad9522_regs.set_b_counter(cs.b_counter);
+ UHD_ASSERT_THROW(cs.prescaler == 8); //assumes this below:
_ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9;
_ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL;
_ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA;
_ad9522_regs.vco_calibration_now = 1; //calibrate it!
- _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5;
+ _ad9522_regs.bypass_vco_divider = 0;
+ switch(cs.vco_divider){
+ case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break;
+ case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break;
+ case 3: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV3; break;
+ case 4: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV4; break;
+ case 5: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; break;
+ case 6: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV6; break;
+ }
_ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO;
//setup fpga master clock
_ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
- set_clock_divider(fpga_clock_divider,
+ set_clock_divider(cs.chan_divider,
_ad9522_regs.divider0_low_cycles,
_ad9522_regs.divider0_high_cycles,
_ad9522_regs.divider0_bypass
@@ -98,52 +203,82 @@ public:
//setup codec clock
_ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS;
- set_clock_divider(codec_clock_divider,
+ set_clock_divider(cs.chan_divider,
_ad9522_regs.divider1_low_cycles,
_ad9522_regs.divider1_high_cycles,
_ad9522_regs.divider1_bypass
);
- //setup test clock (same divider as codec clock)
- _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS;
- _ad9522_regs.out4_cmos_configuration = (enable_test_clock)?
- ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON :
- ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF;
+ this->send_all_regs();
+ }
- //setup a list of register ranges to write
- typedef std::pair<boost::uint16_t, boost::uint16_t> range_t;
- static const std::vector<range_t> ranges = boost::assign::list_of
- (range_t(0x000, 0x000)) (range_t(0x010, 0x01F))
- (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B))
- (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230))
- ;
+ void set_clock_settings_with_external_vcxo(double rate){
+ //set the rates to private variables so the implementation knows!
+ _chan_rate = rate;
+ _out_rate = rate;
- //write initial register values and latch/update
- BOOST_FOREACH(const range_t &range, ranges){
- for(boost::uint16_t addr = range.first; addr <= range.second; addr++){
- this->send_reg(addr);
+ _ad9522_regs.enable_clock_doubler = 1; //doubler always on
+ const double ref_rate = REFERENCE_INPUT_RATE*2;
+
+ //bypass prescaler such that N = B
+ long gcd = boost::math::gcd(long(ref_rate), long(rate));
+ _ad9522_regs.set_r_counter(int(ref_rate/gcd));
+ _ad9522_regs.a_counter = 0;
+ _ad9522_regs.set_b_counter(int(rate/gcd));
+ _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1;
+
+ //setup external vcxo
+ _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL;
+ _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA;
+ _ad9522_regs.bypass_vco_divider = 1;
+ _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL;
+
+ //setup fpga master clock
+ _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
+ _ad9522_regs.divider0_bypass = 1;
+
+ //setup codec clock
+ _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS;
+ _ad9522_regs.divider1_bypass = 1;
+
+ this->send_all_regs();
+ }
+
+ void set_fpga_clock_rate(double rate){
+ if (_out_rate == rate) return;
+
+ if (rate == 61.44e6){
+ set_clock_settings_with_external_vcxo(rate);
+ }
+ else{
+ BOOST_FOREACH(const clock_settings_type &cs, get_clock_settings()){
+ //std::cout << cs.to_pp_string() << std::endl;
+ if (rate != cs.get_out_rate()) continue;
+ std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl;
+ set_clock_settings_with_internal_vco(cs);
+ return; //done here, exits loop
}
+ throw std::runtime_error(str(boost::format(
+ "USRP-E100 clock control: could not find settings for clock rate %fMHz"
+ ) % (rate/1e6)));
}
- this->latch_regs();
- //test read:
- //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b);
- //boost::uint32_t result = _iface->transact_spi(
- // UE_SPI_SS_AD9522,
- // spi_config_t::EDGE_RISE,
- // reg, 24, true /*no*/
- //);
- //std::cout << "result " << std::hex << result << std::endl;
- this->enable_rx_dboard_clock(false);
- this->enable_tx_dboard_clock(false);
}
- ~usrp_e100_clock_ctrl_impl(void){
- this->enable_rx_dboard_clock(false);
- this->enable_tx_dboard_clock(false);
+ double get_fpga_clock_rate(void){
+ return this->_out_rate;
}
- double get_fpga_clock_rate(void){
- return master_clock_rate/fpga_clock_divider;
+ /***********************************************************************
+ * Special test clock output
+ **********************************************************************/
+ void enable_test_clock(bool enb){
+ //setup test clock (same divider as codec clock)
+ _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS;
+ _ad9522_regs.out4_cmos_configuration = (enb)?
+ ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON :
+ ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF;
+ this->send_reg(0x0F0);
+ this->latch_regs();
}
/***********************************************************************
@@ -161,13 +296,13 @@ public:
std::vector<double> get_rx_dboard_clock_rates(void){
std::vector<double> rates;
for(size_t div = 1; div <= 16+16; div++)
- rates.push_back(master_clock_rate/div);
+ rates.push_back(this->_chan_rate/div);
return rates;
}
void set_rx_dboard_clock_rate(double rate){
assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate");
- size_t divider = size_t(master_clock_rate/rate);
+ size_t divider = size_t(this->_chan_rate/rate);
//set the divider registers
set_clock_divider(divider,
_ad9522_regs.divider3_low_cycles,
@@ -197,7 +332,7 @@ public:
void set_tx_dboard_clock_rate(double rate){
assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate");
- size_t divider = size_t(master_clock_rate/rate);
+ size_t divider = size_t(this->_chan_rate/rate);
//set the divider registers
set_clock_divider(divider,
_ad9522_regs.divider2_low_cycles,
@@ -238,6 +373,8 @@ public:
private:
usrp_e100_iface::sptr _iface;
ad9522_regs_t _ad9522_regs;
+ double _out_rate; //rate at the fpga and codec
+ double _chan_rate; //rate before final dividers
void latch_regs(void){
_ad9522_regs.io_update = 1;
@@ -253,6 +390,24 @@ private:
reg, 24, false /*no rb*/
);
}
+
+ void send_all_regs(void){
+ //setup a list of register ranges to write
+ typedef std::pair<boost::uint16_t, boost::uint16_t> range_t;
+ static const std::vector<range_t> ranges = boost::assign::list_of
+ (range_t(0x000, 0x000)) (range_t(0x010, 0x01F))
+ (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B))
+ (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230))
+ ;
+
+ //write initial register values and latch/update
+ BOOST_FOREACH(const range_t &range, ranges){
+ for(boost::uint16_t addr = range.first; addr <= range.second; addr++){
+ this->send_reg(addr);
+ }
+ }
+ this->latch_regs();
+ }
};
/***********************************************************************
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
index d613d1473..1f9960ce4 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
@@ -40,6 +40,13 @@ public:
static sptr make(usrp_e100_iface::sptr iface);
/*!
+ * Set the rate of the fpga clock line.
+ * Throws if rate is not valid.
+ * \param rate the new rate in Hz
+ */
+ virtual void set_fpga_clock_rate(double rate) = 0;
+
+ /*!
* Get the rate of the fpga clock line.
* \return the fpga clock rate in Hz
*/
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp
index a57fe5171..7dc3a4ba8 100644
--- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp
+++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp
@@ -17,7 +17,6 @@
// Slave pointers
#define UE_REG_SLAVE(n) ((n)<<7)
-#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n)))
/////////////////////////////////////////////////////
// Slave 0 -- Misc Regs
@@ -89,16 +88,6 @@
#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric
#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric
-
-////////////////////////////////////////////////////
-// Slave 5 -- Settings Bus
-//
-// Output-only, no readback, 32 registers total
-// Each register must be written 32 bits at a time
-// First the address xxx_xx00 and then xxx_xx10
-
-#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5)
-
///////////////////////////////////////////////////
// Slave 6 -- ATR Controller
// 16 regs
@@ -123,48 +112,64 @@
#define UE_REG_RB_TIME_NOW_TICKS UE_REG_RB_MUX_32_BASE + 4
#define UE_REG_RB_TIME_PPS_SECS UE_REG_RB_MUX_32_BASE + 8
#define UE_REG_RB_TIME_PPS_TICKS UE_REG_RB_MUX_32_BASE + 12
+#define UE_REG_RB_MISC_TEST32 UE_REG_RB_MUX_32_BASE + 16
+
+////////////////////////////////////////////////////
+// Slave 8 -- Settings Bus
+//
+// Output-only, no readback, 64 registers total
+// Each register must be written 64 bits at a time
+// First the address xxx_xx00 and then xxx_xx10
+
+#define UE_REG_SETTINGS_BASE_ADDR(n) (UE_REG_SLAVE(8) + (4*(n)))
+
+#define UE_REG_SR_MISC_TEST32 UE_REG_SETTINGS_BASE_ADDR(52)
/////////////////////////////////////////////////
// DSP RX Regs
////////////////////////////////////////////////
-#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0)
-#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q}
-#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate
-#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic
-#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits
-#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5)
+#define UE_REG_DSP_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(16) + (4*(n)))
+#define UE_REG_DSP_RX_FREQ UE_REG_DSP_RX_ADDR(0)
+#define UE_REG_DSP_RX_SCALE_IQ UE_REG_DSP_RX_ADDR(1) // {scale_i,scale_q}
+#define UE_REG_DSP_RX_DECIM_RATE UE_REG_DSP_RX_ADDR(2) // hb and decim rate
+#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_DSP_RX_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic
+#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_DSP_RX_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits
+#define UE_REG_DSP_RX_MUX UE_REG_DSP_RX_ADDR(5)
///////////////////////////////////////////////////
// VITA RX CTRL regs
///////////////////////////////////////////////////
+#define UE_REG_CTRL_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(0) + (4*(n)))
// The following 3 are logically a single command register.
// They are clocked into the underlying fifo when time_ticks is written.
-#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30)
-#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9)
-#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10)
-#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun
-#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter
-#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet.
-#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14)
-#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15)
-#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources
+#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30)
+#define UE_REG_CTRL_RX_TIME_SECS UE_REG_CTRL_RX_ADDR(1)
+#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_CTRL_RX_ADDR(2)
+#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_CTRL_RX_ADDR(3) // write anything to clear overrun
+#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter
+#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_CTRL_RX_ADDR(5) // word 1 of packet.
+#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_CTRL_RX_ADDR(6)
+#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_CTRL_RX_ADDR(7)
+#define UE_REG_CTRL_RX_NCHANNELS UE_REG_CTRL_RX_ADDR(8) // 1 in basic case, up to 4 for vector sources
/////////////////////////////////////////////////
// DSP TX Regs
////////////////////////////////////////////////
-#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17)
-#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q}
-#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19)
-#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20)
-#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21)
+#define UE_REG_DSP_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(32) + (4*(n)))
+#define UE_REG_DSP_TX_FREQ UE_REG_DSP_TX_ADDR(0)
+#define UE_REG_DSP_TX_SCALE_IQ UE_REG_DSP_TX_ADDR(1) // {scale_i,scale_q}
+#define UE_REG_DSP_TX_INTERP_RATE UE_REG_DSP_TX_ADDR(2)
+#define UE_REG_DSP_TX_UNUSED UE_REG_DSP_TX_ADDR(3)
+#define UE_REG_DSP_TX_MUX UE_REG_DSP_TX_ADDR(4)
/////////////////////////////////////////////////
// VITA TX CTRL regs
////////////////////////////////////////////////
-#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24)
-#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25)
-#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26)
-#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27)
+#define UE_REG_CTRL_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(24) + (4*(n)))
+#define UE_REG_CTRL_TX_NCHANNELS UE_REG_CTRL_TX_ADDR(0)
+#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_CTRL_TX_ADDR(1)
+#define UE_REG_CTRL_TX_REPORT_SID UE_REG_CTRL_TX_ADDR(2)
+#define UE_REG_CTRL_TX_POLICY UE_REG_CTRL_TX_ADDR(3)
#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0)
#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1)
@@ -189,11 +194,12 @@
*
* </pre>
*/
-#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS
-#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS
-#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above
-#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0)
-#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover)
+#define UE_REG_TIME64_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(40) + (4*(n)))
+#define UE_REG_TIME64_SECS UE_REG_TIME64_ADDR(0) // value to set absolute secs to on next PPS
+#define UE_REG_TIME64_TICKS UE_REG_TIME64_ADDR(1) // value to set absolute ticks to on next PPS
+#define UE_REG_TIME64_FLAGS UE_REG_TIME64_ADDR(2) // flags - see chart above
+#define UE_REG_TIME64_IMM UE_REG_TIME64_ADDR(3) // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+#define UE_REG_TIME64_TPS UE_REG_TIME64_ADDR(4) // clock ticks per second (counter rollover)
//pps flags (see above)
#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
diff --git a/host/usrp_e_utils/CMakeLists.txt b/host/usrp_e_utils/CMakeLists.txt
new file mode 100644
index 000000000..96842a684
--- /dev/null
+++ b/host/usrp_e_utils/CMakeLists.txt
@@ -0,0 +1,51 @@
+#
+# Copyright 2011 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# USRP embedded utilities that get installed into the share path
+########################################################################
+IF(CMAKE_SYSTEM_NAME STREQUAL "Linux")
+ SET(LINUX_TARGET TRUE)
+ENDIF(CMAKE_SYSTEM_NAME STREQUAL "Linux")
+
+LIBUHD_REGISTER_COMPONENT("USRP-E Utils" ENABLE_USRP_E_UTILS OFF "LINUX_TARGET" OFF)
+
+IF(ENABLE_USRP_E_UTILS)
+ ENABLE_LANGUAGE(C)
+ INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100)
+ INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include)
+ INCLUDE_DIRECTORIES(${CMAKE_BINARY_DIR}/lib/ic_reg_maps)
+
+ SET(usrp_e_utils_sources
+ fpga-downloader.cpp
+ clkgen-config.cpp
+ usrp-e-loopback.c
+ usrp-e-wb-test.cpp
+ usrp-e-debug-pins.c
+ usrp-e-i2c.c
+ usrp-e-spi.c
+ )
+
+ #for each source: build an executable and install
+ FOREACH(util_source ${usrp_e_utils_sources})
+ GET_FILENAME_COMPONENT(util_name ${util_source} NAME_WE)
+ ADD_EXECUTABLE(${util_name} ${util_source})
+ TARGET_LINK_LIBRARIES(${util_name} -lpthread)
+ INSTALL(TARGETS ${util_name} RUNTIME DESTINATION ${PKG_DATA_DIR}/usrp_e_utils)
+ ENDFOREACH(util_source)
+
+ENDIF(ENABLE_USRP_E_UTILS)
diff --git a/host/usrp_e_utils/clkgen-config.cpp b/host/usrp_e_utils/clkgen-config.cpp
new file mode 100644
index 000000000..8d29efff1
--- /dev/null
+++ b/host/usrp_e_utils/clkgen-config.cpp
@@ -0,0 +1,305 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of UHD
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+*/
+
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <string>
+#include <cstdlib>
+
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include "ad9522_regs.hpp"
+
+#include <linux/spi/spidev.h>
+
+
+const unsigned int CLKGEN_SELECT = 145;
+
+enum gpio_direction {IN, OUT};
+
+class gpio {
+ public:
+
+ gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action);
+ ~gpio();
+
+ bool get_value();
+ void set_value(bool state);
+
+ private:
+
+ unsigned int gpio_num;
+
+ std::stringstream base_path;
+ std::fstream value_file;
+ std::fstream direction_file;
+ bool close_action; // True set to input and release, false do nothing
+};
+
+class spidev {
+ public:
+
+ spidev(std::string dev_name);
+ ~spidev();
+
+ void send(char *wbuf, char *rbuf, unsigned int nbytes);
+
+ private:
+
+ int fd;
+
+};
+
+gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action)
+{
+ std::fstream export_file;
+
+ gpio_num = _gpio_num;
+
+ export_file.open("/sys/class/gpio/export", std::ios::out);
+ if (!export_file.is_open()) ///\todo Poor error handling
+ std::cout << "Failed to open gpio export file." << std::endl;
+
+ export_file << gpio_num << std::endl;
+
+ base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush;
+
+ std::string direction_file_name;
+
+ direction_file_name = base_path.str() + "/direction";
+
+ direction_file.open(direction_file_name.c_str());
+ if (!direction_file.is_open())
+ std::cout << "Failed to open direction file." << std::endl;
+ if (pin_direction == OUT)
+ direction_file << "out" << std::endl;
+ else
+ direction_file << "in" << std::endl;
+
+ std::string value_file_name;
+
+ value_file_name = base_path.str() + "/value";
+
+ value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out);
+ if (!value_file.is_open())
+ std::cout << "Failed to open value file." << std::endl;
+}
+
+bool gpio::get_value()
+{
+
+ std::string val;
+
+ std::getline(value_file, val);
+ value_file.seekg(0);
+
+ if (val == "0")
+ return false;
+ else if (val == "1")
+ return true;
+ else
+ std::cout << "Data read from value file|" << val << "|" << std::endl;
+
+ return false;
+}
+
+void gpio::set_value(bool state)
+{
+
+ if (state)
+ value_file << "1" << std::endl;
+ else
+ value_file << "0" << std::endl;
+}
+
+gpio::~gpio()
+{
+ if (close_action) {
+ std::fstream unexport_file;
+
+ direction_file << "in" << std::endl;
+
+ unexport_file.open("/sys/class/gpio/unexport", std::ios::out);
+ if (!unexport_file.is_open()) ///\todo Poor error handling
+ std::cout << "Failed to open gpio export file." << std::endl;
+
+ unexport_file << gpio_num << std::endl;
+
+ }
+
+}
+
+spidev::spidev(std::string fname)
+{
+ int ret;
+ int mode = 0;
+ int speed = 12000;
+ int bits = 24;
+
+ fd = open(fname.c_str(), O_RDWR);
+
+ ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
+ ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+ ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+}
+
+
+spidev::~spidev()
+{
+ close(fd);
+}
+
+void spidev::send(char *buf, char *rbuf, unsigned int nbytes)
+{
+ int ret;
+
+ struct spi_ioc_transfer tr;
+ tr.tx_buf = (unsigned long) buf;
+ tr.rx_buf = (unsigned long) rbuf;
+ tr.len = nbytes;
+ tr.delay_usecs = 0;
+ tr.speed_hz = 12000000;
+ tr.bits_per_word = 24;
+
+ ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+
+}
+
+static void spi_write_word(spidev spi, gpio &chip_select, const unsigned int addr, const unsigned char data) {
+ unsigned char out_data[3], in_data[3];
+ unsigned char rw_w1_w0 = 0; //write one byte
+ out_data[0] = (rw_w1_w0 << 5) | (addr >> 8);
+ out_data[1] = addr & 0xff;
+ out_data[2] = data;
+
+ chip_select.set_value(0);
+ spi.send((char *)out_data, (char *)in_data, 4);
+ chip_select.set_value(1);
+}
+
+static void send_config_to_clkgen(gpio &chip_select)
+{
+ spidev spi("/dev/spidev1.0");
+
+ //do a soft reset
+ spi_write_word(spi, chip_select, 0x000, 1 << 5 | 1 << 2);
+ spi_write_word(spi, chip_select, 0x232, 0x1);
+
+ // init some registers;
+ ad9522_regs_t ad9522_regs;
+ ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; //use sdo and sdi
+ ad9522_regs.mirror = 1; //mirror sdo active
+ ad9522_regs.io_update = 1; //latch the registers
+ ad9522_regs.status_pin_control = 0x1; //n divider
+ ad9522_regs.ld_pin_control = 0x32; //show ref2
+ ad9522_regs.refmon_pin_control = 0x12; //show ref2
+ ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin as debug
+
+ ad9522_regs.enable_ref2 = 0x1;
+ ad9522_regs.enable_ref1 = 0x0;
+ ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2;
+
+ ad9522_regs.set_r_counter(1);
+ ad9522_regs.a_counter = 0;
+ ad9522_regs.set_b_counter(20);
+ ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9;
+
+ ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; //normal mode
+ ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA;
+
+ ad9522_regs.vco_calibration_now = 1; //calibrate it!
+ ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5;
+ ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO;
+
+ ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
+ ad9522_regs.divider0_low_cycles = 2; //3 low
+ ad9522_regs.divider0_high_cycles = 1; //2 high
+ ad9522_regs.divider1_low_cycles = 2; //3 low
+ ad9522_regs.divider1_high_cycles = 1; //2 high
+
+ ad9522_regs.enable_eeprom_write = 1;
+
+ //write the registers
+ int reg_list[] = {0, 4, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 240, 241, 242, 243,
+ 244, 245, 246, 247, 248, 249, 250, 251, 252,
+ 253, 400, 401, 402, 403, 404, 405, 406, 407,
+ 408, 409, 410, 411, 480, 481, 560, 562, 2818,
+ 2819};
+
+ for(int i=0; i<49; i++) { //blame std::vector for this (no static initialization bs)
+ spi_write_word(spi, chip_select, reg_list[i], ad9522_regs.get_reg(reg_list[i]));
+ }
+
+ sleep(1);
+
+ if (1){//write settings to eeprom
+
+ //load the register buffs
+ spi_write_word(spi, chip_select, 0xa00, 0x0);
+ spi_write_word(spi, chip_select, 0xa01, 0x0);
+ spi_write_word(spi, chip_select, 0xa02, 0x0);
+ spi_write_word(spi, chip_select, 0xa03, 0x2);
+ spi_write_word(spi, chip_select, 0xa04, 0x0);
+ spi_write_word(spi, chip_select, 0xa05, 0x4);
+ spi_write_word(spi, chip_select, 0xa06, 0xe);
+ spi_write_word(spi, chip_select, 0xa07, 0x0);
+ spi_write_word(spi, chip_select, 0xa08, 0x10);
+ spi_write_word(spi, chip_select, 0xa09, 0xe);
+ spi_write_word(spi, chip_select, 0xa0a, 0x0);
+ spi_write_word(spi, chip_select, 0xa0b, 0xf0);
+ spi_write_word(spi, chip_select, 0xa0c, 0xb);
+ spi_write_word(spi, chip_select, 0xa0d, 0x1);
+ spi_write_word(spi, chip_select, 0xa0e, 0x90);
+ spi_write_word(spi, chip_select, 0xa0f, 0x1);
+ spi_write_word(spi, chip_select, 0xa10, 0x1);
+ spi_write_word(spi, chip_select, 0xa11, 0xe0);
+ spi_write_word(spi, chip_select, 0xa12, 0x1);
+ spi_write_word(spi, chip_select, 0xa13, 0x2);
+ spi_write_word(spi, chip_select, 0xa14, 0x30);
+ spi_write_word(spi, chip_select, 0xa15, 0x80);
+ spi_write_word(spi, chip_select, 0xa16, 0xff);
+
+ spi_write_word(spi, chip_select, 0x232, 0x01); //latch
+ sleep(1);
+ ////////////////////////////////////////////////////////////////
+
+ ad9522_regs.reg2eeprom = 1;
+ //write to eeprom
+ spi_write_word(spi, chip_select, 0xB03, ad9522_regs.get_reg(0xB03));
+ //io update
+ spi_write_word(spi, chip_select, 0x232, ad9522_regs.get_reg(0x232)); //latch
+ sleep(1);
+ }
+
+}
+
+int main(int argc, char *argv[])
+{
+ gpio clkgen_select(CLKGEN_SELECT, OUT, true);
+
+ send_config_to_clkgen(clkgen_select);
+}
+
diff --git a/host/utils/fpga-downloader.cpp b/host/usrp_e_utils/fpga-downloader.cpp
index 80ee71600..80ee71600 100644
--- a/host/utils/fpga-downloader.cpp
+++ b/host/usrp_e_utils/fpga-downloader.cpp
diff --git a/host/utils/usrp-e-debug-pins.c b/host/usrp_e_utils/usrp-e-debug-pins.c
index 94f898b67..94f898b67 100644
--- a/host/utils/usrp-e-debug-pins.c
+++ b/host/usrp_e_utils/usrp-e-debug-pins.c
diff --git a/host/utils/usrp-e-i2c.c b/host/usrp_e_utils/usrp-e-i2c.c
index c6fd4c632..c6fd4c632 100644
--- a/host/utils/usrp-e-i2c.c
+++ b/host/usrp_e_utils/usrp-e-i2c.c
diff --git a/host/utils/usrp-e-loopback.c b/host/usrp_e_utils/usrp-e-loopback.c
index 454d81ba7..454d81ba7 100644
--- a/host/utils/usrp-e-loopback.c
+++ b/host/usrp_e_utils/usrp-e-loopback.c
diff --git a/host/utils/usrp-e-spi.c b/host/usrp_e_utils/usrp-e-spi.c
index 5203f56a8..5203f56a8 100644
--- a/host/utils/usrp-e-spi.c
+++ b/host/usrp_e_utils/usrp-e-spi.c
diff --git a/host/usrp_e_utils/usrp-e-wb-test.cpp b/host/usrp_e_utils/usrp-e-wb-test.cpp
new file mode 100644
index 000000000..3d6a8d101
--- /dev/null
+++ b/host/usrp_e_utils/usrp-e-wb-test.cpp
@@ -0,0 +1,115 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <cstdlib>
+#include <cstdio>
+#include <ctime>
+#include <iostream>
+
+#include <sys/ioctl.h> //ioctl
+#include <fcntl.h> //open, close
+
+#include <linux/usrp_e.h>
+#include "usrp_e100_regs.hpp"
+
+static const size_t num_test_iters = 10000000;
+
+static int fp;
+
+static int peek16(int reg){
+ int ret;
+ struct usrp_e_ctl16 d;
+
+ d.offset = reg;
+ d.count = 1;
+ ret = ioctl(fp, USRP_E_READ_CTL16, &d);
+ return d.buf[0];
+}
+
+static void poke16(int reg, int val){
+ int ret;
+ struct usrp_e_ctl16 d;
+
+ d.offset = reg;
+ d.count = 1;
+ d.buf[0] = val;
+ ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+}
+
+static int peek32(int reg){
+ int ret;
+ struct usrp_e_ctl32 d;
+
+ d.offset = reg;
+ d.count = 1;
+ ret = ioctl(fp, USRP_E_READ_CTL32, &d);
+ return d.buf[0];
+}
+
+static void poke32(int reg, int val){
+ int ret;
+ struct usrp_e_ctl32 d;
+
+ d.offset = reg;
+ d.count = 1;
+ d.buf[0] = val;
+ ret = ioctl(fp, USRP_E_WRITE_CTL32, &d);
+}
+
+int main(int, char *[]){
+
+ srandom(time(NULL)); //seed random()
+
+ if ((fp = ::open("/dev/usrp_e0", O_RDWR)) < 0){
+ std::cerr << "Open failed" << std::endl;
+ return -1;
+ }
+
+ size_t num_pass = 0, num_fail = 0;
+ for (size_t i = 0; i < num_test_iters; i++){
+ if(i%1000000 == 0) {
+ std::cout << "num pass: " << num_pass;
+ std::cout << "\tnum fail: " << num_fail << std::endl;
+ }
+ //make random values
+ int random_test32 = ::random();
+ int random_test16 = ::random() & 0xffff;
+ int random_secs = ::random();
+
+ //set a bunch of registers
+ poke16(UE_REG_MISC_TEST, random_test16);
+ poke32(UE_REG_SR_MISC_TEST32, random_test32);
+ poke32(UE_REG_TIME64_TICKS, 0);
+ poke32(UE_REG_TIME64_IMM, 1); //immediate
+ poke32(UE_REG_TIME64_SECS, random_secs);
+
+ //read a bunch of registers
+ if (
+ (peek16(UE_REG_MISC_TEST) == random_test16) and
+ (peek32(UE_REG_RB_MISC_TEST32) == random_test32) and
+ (peek32(UE_REG_RB_TIME_NOW_SECS) == random_secs) and
+// (peek32(UE_REG_RB_TIME_NOW_TICKS) < 1000000) and
+ true) num_pass++;
+ else num_fail++;
+ }
+
+ std::cout << "num pass: " << num_pass << std::endl;
+ std::cout << "num fail: " << num_fail << std::endl;
+
+ ::close(fp);
+ return 0;
+}
diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt
index 2df1c3529..53527c03d 100644
--- a/host/utils/CMakeLists.txt
+++ b/host/utils/CMakeLists.txt
@@ -1,5 +1,5 @@
#
-# Copyright 2010 Ettus Research LLC
+# Copyright 2010-2011 Ettus Research LLC
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -45,20 +45,6 @@ IF(ENABLE_USRP1)
)
ENDIF(ENABLE_USRP1)
-IF(ENABLE_USRP_E100)
- ENABLE_LANGUAGE(C)
- INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100)
- INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include)
- LIST(APPEND util_share_sources
- fpga-downloader.cpp
- clkgen-config.cpp
- usrp-e-loopback.c
- usrp-e-debug-pins.c
- usrp-e-i2c.c
- usrp-e-spi.c
- )
-ENDIF(ENABLE_USRP_E100)
-
#for each source: build an executable and install
FOREACH(util_source ${util_share_sources})
GET_FILENAME_COMPONENT(util_name ${util_source} NAME_WE)
diff --git a/host/utils/clkgen-config.cpp b/host/utils/clkgen-config.cpp
deleted file mode 100644
index e8279b4ae..000000000
--- a/host/utils/clkgen-config.cpp
+++ /dev/null
@@ -1,296 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
- *
- * This file is part of UHD
- *
- * GNU Radio is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 3, or (at your option)
- * any later version.
- *
- * GNU Radio is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with GNU Radio; see the file COPYING. If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
-*/
-
-#include <iostream>
-#include <sstream>
-#include <fstream>
-#include <string>
-#include <cstdlib>
-
-#include <fcntl.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/ioctl.h>
-
-#include <linux/spi/spidev.h>
-
-
-// Programming data for clock gen chip
-static const unsigned int config_data[] = {
- 0x000024,
- 0x023201,
- 0x000081,
- 0x000400,
- 0x00104c,
- 0x001101,
- 0x001200,
- 0x001300,
- 0x001414,
- 0x001500,
- 0x001604,
- 0x001704,
- 0x001807,
- 0x001900,
- //0x001a00,//for debug
- 0x001a32,
- 0x001b12,
- 0x001c44,
- 0x001d00,
- 0x001e00,
- 0x00f062,
- 0x00f162,
- 0x00f262,
- 0x00f362,
- 0x00f462,
- 0x00f562,
- 0x00f662,
- 0x00f762,
- 0x00f862,
- 0x00f962,
- 0x00fa62,
- 0x00fb62,
- 0x00fc00,
- 0x00fd00,
- 0x019021,
- 0x019100,
- 0x019200,
- 0x019333,
- 0x019400,
- 0x019500,
- 0x019611,
- 0x019700,
- 0x019800,
- 0x019900,
- 0x019a00,
- 0x019b00,
- 0x01e003,
- 0x01e102,
- 0x023000,
- 0x023201,
- 0x0b0201,
- 0x0b0300,
- 0x001fff,
- 0x0a0000,
- 0x0a0100,
- 0x0a0200,
- 0x0a0302,
- 0x0a0400,
- 0x0a0504,
- 0x0a060e,
- 0x0a0700,
- 0x0a0810,
- 0x0a090e,
- 0x0a0a00,
- 0x0a0bf0,
- 0x0a0c0b,
- 0x0a0d01,
- 0x0a0e90,
- 0x0a0f01,
- 0x0a1001,
- 0x0a11e0,
- 0x0a1201,
- 0x0a1302,
- 0x0a1430,
- 0x0a1580,
- 0x0a16ff,
- 0x023201,
- 0x0b0301,
- 0x023201,
-};
-
-
-const unsigned int CLKGEN_SELECT = 145;
-
-
-enum gpio_direction {IN, OUT};
-
-class gpio {
- public:
-
- gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action);
- ~gpio();
-
- bool get_value();
- void set_value(bool state);
-
- private:
-
- unsigned int gpio_num;
-
- std::stringstream base_path;
- std::fstream value_file;
- std::fstream direction_file;
- bool close_action; // True set to input and release, false do nothing
-};
-
-class spidev {
- public:
-
- spidev(std::string dev_name);
- ~spidev();
-
- void send(char *wbuf, char *rbuf, unsigned int nbytes);
-
- private:
-
- int fd;
-
-};
-
-gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action)
-{
- std::fstream export_file;
-
- gpio_num = _gpio_num;
-
- export_file.open("/sys/class/gpio/export", std::ios::out);
- if (!export_file.is_open()) ///\todo Poor error handling
- std::cout << "Failed to open gpio export file." << std::endl;
-
- export_file << gpio_num << std::endl;
-
- base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush;
-
- std::string direction_file_name;
-
- direction_file_name = base_path.str() + "/direction";
-
- direction_file.open(direction_file_name.c_str());
- if (!direction_file.is_open())
- std::cout << "Failed to open direction file." << std::endl;
- if (pin_direction == OUT)
- direction_file << "out" << std::endl;
- else
- direction_file << "in" << std::endl;
-
- std::string value_file_name;
-
- value_file_name = base_path.str() + "/value";
-
- value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out);
- if (!value_file.is_open())
- std::cout << "Failed to open value file." << std::endl;
-}
-
-bool gpio::get_value()
-{
-
- std::string val;
-
- std::getline(value_file, val);
- value_file.seekg(0);
-
- if (val == "0")
- return false;
- else if (val == "1")
- return true;
- else
- std::cout << "Data read from value file|" << val << "|" << std::endl;
-
- return false;
-}
-
-void gpio::set_value(bool state)
-{
-
- if (state)
- value_file << "1" << std::endl;
- else
- value_file << "0" << std::endl;
-}
-
-gpio::~gpio()
-{
- if (close_action) {
- std::fstream unexport_file;
-
- direction_file << "in" << std::endl;
-
- unexport_file.open("/sys/class/gpio/unexport", std::ios::out);
- if (!unexport_file.is_open()) ///\todo Poor error handling
- std::cout << "Failed to open gpio export file." << std::endl;
-
- unexport_file << gpio_num << std::endl;
-
- }
-
-}
-
-spidev::spidev(std::string fname)
-{
- int ret;
- int mode = 0;
- int speed = 12000;
- int bits = 24;
-
- fd = open(fname.c_str(), O_RDWR);
-
- ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
- ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
- ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
-}
-
-
-spidev::~spidev()
-{
- close(fd);
-}
-
-void spidev::send(char *buf, char *rbuf, unsigned int nbytes)
-{
- int ret;
-
- struct spi_ioc_transfer tr;
- tr.tx_buf = (unsigned long) buf;
- tr.rx_buf = (unsigned long) rbuf;
- tr.len = nbytes;
- tr.delay_usecs = 0;
- tr.speed_hz = 12000000;
- tr.bits_per_word = 24;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
-
-}
-
-static void send_config_to_clkgen(gpio &chip_select, const unsigned int data[], unsigned int data_size)
-{
- spidev spi("/dev/spidev1.0");
- unsigned int rbuf;
-
- for (unsigned int i = 0; i < data_size; i++) {
-
- std::cout << "sending " << std::hex << data[i] << std::endl;
- chip_select.set_value(0);
- spi.send((char *)&data[i], (char *)&rbuf, 4);
- chip_select.set_value(1);
-
- };
-}
-
-int main(int argc, char *argv[])
-{
-
- gpio clkgen_select(CLKGEN_SELECT, OUT, true);
-
- send_config_to_clkgen(clkgen_select, config_data, sizeof(config_data)/sizeof(unsigned int));
-}
-
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 21:49:30 +0000