diff options
| -rw-r--r-- | firmware/microblaze/apps/txrx.c | 73 | ||||
| -rw-r--r-- | host/include/uhd/usrp/dboard_interface.hpp | 75 | ||||
| -rw-r--r-- | host/lib/usrp/dboard/db_basic_and_lf.cpp | 4 | ||||
| -rw-r--r-- | host/lib/usrp/dboard_interface.cpp | 13 | ||||
| -rw-r--r-- | host/lib/usrp/dboard_manager.cpp | 11 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/dboard_interface.cpp | 154 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/fw_common.h | 98 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_impl.cpp | 24 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_impl.hpp | 4 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 57 |
10 files changed, 254 insertions, 259 deletions
diff --git a/firmware/microblaze/apps/txrx.c b/firmware/microblaze/apps/txrx.c index 262995885..926260bac 100644 --- a/firmware/microblaze/apps/txrx.c +++ b/firmware/microblaze/apps/txrx.c @@ -291,53 +291,6 @@ void handle_udp_ctrl_packet( break; /******************************************************************* - * GPIO - ******************************************************************/ - case USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO: - if (!DEBUG_MODE) hal_gpio_set_ddr( - OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank), - ctrl_data_in->data.gpio_config.value, - ctrl_data_in->data.gpio_config.mask - ); - ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE; - break; - - case USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO: - if (!DEBUG_MODE) hal_gpio_write( - OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank), - ctrl_data_in->data.gpio_config.value, - ctrl_data_in->data.gpio_config.mask - ); - ctrl_data_out.id = USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE; - break; - - case USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO: - ctrl_data_out.data.gpio_config.value = hal_gpio_read( - OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank) - ); - ctrl_data_out.id = USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE; - break; - - case USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO:{ - //setup the atr registers for this bank - int bank = OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.atr_config.bank); - if (!DEBUG_MODE) set_atr_regs( - bank, - ctrl_data_in->data.atr_config.rx_value, - ctrl_data_in->data.atr_config.tx_value - ); - - //setup the sels based on the atr config mask - int mask = ctrl_data_in->data.atr_config.mask; - for (int i = 0; i < 16; i++){ - // set to either GPIO_SEL_SW or GPIO_SEL_ATR - if (!DEBUG_MODE) hal_gpio_set_sel(bank, i, (mask & (1 << i)) ? 'a' : 's'); - } - ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE; - } - break; - - /******************************************************************* * SPI ******************************************************************/ case USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO:{ @@ -354,8 +307,8 @@ void handle_udp_ctrl_packet( (ctrl_data_in->data.spi_args.readback == 0)? SPI_TXONLY : SPI_TXRX, (ctrl_data_in->data.spi_args.dev == USRP2_DIR_RX)? SPI_SS_RX_DB : SPI_SS_TX_DB, data, num_bytes*8, //length in bits - (ctrl_data_in->data.spi_args.push == USRP2_CLK_EDGE_RISE)? SPIF_PUSH_RISE : SPIF_PUSH_FALL | - (ctrl_data_in->data.spi_args.latch == USRP2_CLK_EDGE_RISE)? SPIF_LATCH_RISE : SPIF_LATCH_FALL + (ctrl_data_in->data.spi_args.edge == USRP2_CLK_EDGE_RISE)? SPIF_PUSH_RISE : SPIF_PUSH_FALL | + (ctrl_data_in->data.spi_args.edge == USRP2_CLK_EDGE_RISE)? SPIF_LATCH_RISE : SPIF_LATCH_FALL ); //load the result into the array of bytes @@ -571,6 +524,24 @@ void handle_udp_ctrl_packet( ctrl_data_out.id = USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE; break; + /******************************************************************* + * Peek and Poke Register + ******************************************************************/ + case USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO: + if (ctrl_data_in->data.poke_args.addr < 0xC000){ + printf("error! tried to poke into 0x%x\n", ctrl_data_in->data.poke_args.addr); + } + else{ + *((uint32_t *) ctrl_data_in->data.poke_args.addr) = ctrl_data_in->data.poke_args.data; + } + ctrl_data_out.id = USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE; + break; + + case USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO: + ctrl_data_in->data.poke_args.data = *((uint32_t *) ctrl_data_in->data.poke_args.addr); + ctrl_data_out.id = USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE; + break; + default: ctrl_data_out.id = USRP2_CTRL_ID_HUH_WHAT; @@ -759,6 +730,10 @@ main(void) hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000); #endif +//set them all to the atr settings by default +hal_gpio_set_sels(GPIO_TX_BANK, "aaaaaaaaaaaaaaaa"); +hal_gpio_set_sels(GPIO_RX_BANK, "aaaaaaaaaaaaaaaa"); + output_regs->debug_mux_ctrl = 1; #if DEBUG_MODE hal_gpio_set_sels(GPIO_TX_BANK, "0000000000000000"); diff --git a/host/include/uhd/usrp/dboard_interface.hpp b/host/include/uhd/usrp/dboard_interface.hpp index c779431ab..8ff0c5d2f 100644 --- a/host/include/uhd/usrp/dboard_interface.hpp +++ b/host/include/uhd/usrp/dboard_interface.hpp @@ -38,32 +38,34 @@ public: //tells the host which unit to use enum unit_type_t{ - UNIT_TYPE_RX, - UNIT_TYPE_TX + UNIT_TYPE_RX = 'r', + UNIT_TYPE_TX = 't' }; //tells the host which device to use enum spi_dev_t{ - SPI_TX_DEV, - SPI_RX_DEV + SPI_DEV_RX = 'r', + SPI_DEV_TX = 't' }; - //args for writing spi data - enum spi_push_t{ - SPI_PUSH_RISE, - SPI_PUSH_FALL - }; - - //args for reading spi data - enum spi_latch_t{ - SPI_LATCH_RISE, - SPI_LATCH_FALL + //args for spi format + enum spi_edge_t{ + SPI_EDGE_RISE = 'r', + SPI_EDGE_FALL = 'f' }; //tell the host which gpio bank enum gpio_bank_t{ - GPIO_TX_BANK, - GPIO_RX_BANK + GPIO_BANK_RX = 'r', + GPIO_BANK_TX = 't' + }; + + //possible atr registers + enum atr_reg_t{ + ATR_REG_IDLE = 'i', + ATR_REG_TXONLY = 't', + ATR_REG_RXONLY = 'r', + ATR_REG_BOTH = 'b' }; //structors @@ -87,17 +89,13 @@ public: virtual int read_aux_adc(unit_type_t unit, int which_adc) = 0; /*! - * Set daughterboard ATR register. - * The ATR register for a particular bank has 2 values: - * one value when transmitting, one when receiving. - * The mask controls which pins are controlled by ATR. + * Set a daughterboard ATR register. * - * \param bank GPIO_TX_BANK or GPIO_RX_BANK - * \param tx_value 16-bits, 0=FPGA output low, 1=FPGA output high - * \param rx_value 16-bits, 0=FPGA output low, 1=FPGA output high - * \param mask 16-bits, 0=software, 1=atr + * \param bank GPIO_TX_BANK or GPIO_RX_BANK + * \param reg which ATR register to set + * \param value 16-bits, 0=FPGA output low, 1=FPGA output high */ - virtual void set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask) = 0; + virtual void set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost::uint16_t value) = 0; /*! * Set daughterboard GPIO data direction register. @@ -108,14 +106,6 @@ public: virtual void set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value) = 0; /*! - * Set daughterboard GPIO pin values. - * - * \param bank GPIO_TX_BANK or GPIO_RX_BANK - * \param value 16 bits, 0=low, 1=high - */ - virtual void write_gpio(gpio_bank_t bank, boost::uint16_t value) = 0; - - /*! * Read daughterboard GPIO pin values * * \param bank GPIO_TX_BANK or GPIO_RX_BANK @@ -142,32 +132,31 @@ public: * \brief Write data to SPI bus peripheral. * * \param dev which spi device - * \param push args for writing + * \param edge args for format * \param buf the data to write */ - void write_spi(spi_dev_t dev, spi_push_t push, const byte_vector_t &buf); + void write_spi(spi_dev_t dev, spi_edge_t edge, const byte_vector_t &buf); /*! * \brief Read data to SPI bus peripheral. * * \param dev which spi device - * \param latch args for reading + * \param edge args for format * \param num_bytes number of bytes to read * \return the data that was read */ - byte_vector_t read_spi(spi_dev_t dev, spi_latch_t latch, size_t num_bytes); + byte_vector_t read_spi(spi_dev_t dev, spi_edge_t edge, size_t num_bytes); /*! * \brief Read and write data to SPI bus peripheral. * The data read back will be the same length as the input buffer. * * \param dev which spi device - * \param latch args for reading - * \param push args for clock + * \param edge args for format * \param buf the data to write * \return the data that was read */ - byte_vector_t read_write_spi(spi_dev_t dev, spi_latch_t latch, spi_push_t push, const byte_vector_t &buf); + byte_vector_t read_write_spi(spi_dev_t dev, spi_edge_t edge, const byte_vector_t &buf); /*! * \brief Get the rate of the rx dboard clock. @@ -186,16 +175,14 @@ private: * \brief Read and write data to SPI bus peripheral. * * \param dev which spi device - * \param latch args for reading - * \param push args for clock + * \param edge args for format * \param buf the data to write * \param readback false for write only * \return the data that was read */ virtual byte_vector_t transact_spi( spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, + spi_edge_t edge, const byte_vector_t &buf, bool readback ) = 0; diff --git a/host/lib/usrp/dboard/db_basic_and_lf.cpp b/host/lib/usrp/dboard/db_basic_and_lf.cpp index 50c868a24..977eb3d49 100644 --- a/host/lib/usrp/dboard/db_basic_and_lf.cpp +++ b/host/lib/usrp/dboard/db_basic_and_lf.cpp @@ -88,7 +88,7 @@ UHD_STATIC_BLOCK(reg_dboards){ basic_rx::basic_rx(ctor_args_t const& args, double max_freq) : rx_dboard_base(args){ _max_freq = max_freq; // set the gpios to safe values (all inputs) - get_interface()->set_gpio_ddr(dboard_interface::GPIO_RX_BANK, 0x0000); + get_interface()->set_gpio_ddr(dboard_interface::GPIO_BANK_RX, 0x0000); } basic_rx::~basic_rx(void){ @@ -199,7 +199,7 @@ void basic_rx::rx_set(const wax::obj &key_, const wax::obj &val){ basic_tx::basic_tx(ctor_args_t const& args, double max_freq) : tx_dboard_base(args){ _max_freq = max_freq; // set the gpios to safe values (all inputs) - get_interface()->set_gpio_ddr(dboard_interface::GPIO_TX_BANK, 0x0000); + get_interface()->set_gpio_ddr(dboard_interface::GPIO_BANK_TX, 0x0000); } basic_tx::~basic_tx(void){ diff --git a/host/lib/usrp/dboard_interface.cpp b/host/lib/usrp/dboard_interface.cpp index f6d6b6456..c40c9b398 100644 --- a/host/lib/usrp/dboard_interface.cpp +++ b/host/lib/usrp/dboard_interface.cpp @@ -29,26 +29,25 @@ dboard_interface::~dboard_interface(void){ void dboard_interface::write_spi( spi_dev_t dev, - spi_push_t push, + spi_edge_t edge, const byte_vector_t &buf ){ - transact_spi(dev, SPI_LATCH_RISE, push, buf, false); //dont readback + transact_spi(dev, edge, buf, false); //dont readback } dboard_interface::byte_vector_t dboard_interface::read_spi( spi_dev_t dev, - spi_latch_t latch, + spi_edge_t edge, size_t num_bytes ){ byte_vector_t buf(num_bytes, 0x00); //dummy data - return transact_spi(dev, latch, SPI_PUSH_RISE, buf, true); //readback + return transact_spi(dev, edge, buf, true); //readback } dboard_interface::byte_vector_t dboard_interface::read_write_spi( spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, + spi_edge_t edge, const byte_vector_t &buf ){ - return transact_spi(dev, latch, push, buf, true); //readback + return transact_spi(dev, edge, buf, true); //readback } diff --git a/host/lib/usrp/dboard_manager.cpp b/host/lib/usrp/dboard_manager.cpp index 15be7eedc..5c063d51d 100644 --- a/host/lib/usrp/dboard_manager.cpp +++ b/host/lib/usrp/dboard_manager.cpp @@ -275,12 +275,9 @@ wax::obj dboard_manager_impl::get_tx_subdev(const std::string &subdev_name){ void dboard_manager_impl::set_nice_gpio_pins(void){ //std::cout << "Set nice GPIO pins" << std::endl; - _interface->set_gpio_ddr(dboard_interface::GPIO_RX_BANK, 0x0000); //all inputs - _interface->set_gpio_ddr(dboard_interface::GPIO_TX_BANK, 0x0000); + _interface->set_gpio_ddr(dboard_interface::GPIO_BANK_RX, 0x0000); //all inputs + _interface->set_atr_reg(dboard_interface::GPIO_BANK_RX, dboard_interface::ATR_REG_IDLE, 0x0000); //all low - _interface->write_gpio(dboard_interface::GPIO_RX_BANK, 0x0000); //all zeros - _interface->write_gpio(dboard_interface::GPIO_TX_BANK, 0x0000); - - _interface->set_atr_reg(dboard_interface::GPIO_RX_BANK, 0x0000, 0x0000, 0x0000); //software controlled - _interface->set_atr_reg(dboard_interface::GPIO_TX_BANK, 0x0000, 0x0000, 0x0000); + _interface->set_gpio_ddr(dboard_interface::GPIO_BANK_TX, 0x0000); //all inputs + _interface->set_atr_reg(dboard_interface::GPIO_BANK_TX, dboard_interface::ATR_REG_IDLE, 0x0000); //all low } diff --git a/host/lib/usrp/usrp2/dboard_interface.cpp b/host/lib/usrp/usrp2/dboard_interface.cpp index 5a7d870b4..0bf4fa2e6 100644 --- a/host/lib/usrp/usrp2/dboard_interface.cpp +++ b/host/lib/usrp/usrp2/dboard_interface.cpp @@ -15,8 +15,12 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // -#include <uhd/utils/assert.hpp> #include "usrp2_impl.hpp" +#include "usrp2_regs.hpp" +#include <uhd/types/dict.hpp> +#include <uhd/utils/assert.hpp> +#include <boost/assign/list_of.hpp> +#include <cstddef> using namespace uhd::usrp; @@ -28,9 +32,8 @@ public: void write_aux_dac(unit_type_t, int, int); int read_aux_adc(unit_type_t, int); - void set_atr_reg(gpio_bank_t, boost::uint16_t, boost::uint16_t, boost::uint16_t); + void set_atr_reg(gpio_bank_t, atr_reg_t, boost::uint16_t); void set_gpio_ddr(gpio_bank_t, boost::uint16_t); - void write_gpio(gpio_bank_t, boost::uint16_t); boost::uint16_t read_gpio(gpio_bank_t); void write_i2c(int, const byte_vector_t &); @@ -41,14 +44,21 @@ public: private: byte_vector_t transact_spi( - spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, - const byte_vector_t &buf, - bool readback + spi_dev_t, spi_edge_t, const byte_vector_t &, bool ); usrp2_impl *_impl; + + //shadows + boost::uint32_t _ddr_shadow; + uhd::dict<atr_reg_t, uint32_t> _atr_reg_shadows; + + //utilities + static int bank_to_shift(gpio_bank_t bank){ + static const uhd::dict<gpio_bank_t, int> _bank_to_shift = \ + boost::assign::map_list_of(GPIO_BANK_RX, 0)(GPIO_BANK_TX, 16); + return _bank_to_shift[bank]; + } }; /*********************************************************************** @@ -63,6 +73,7 @@ dboard_interface::sptr make_usrp2_dboard_interface(usrp2_impl *impl){ **********************************************************************/ usrp2_dboard_interface::usrp2_dboard_interface(usrp2_impl *impl){ _impl = impl; + _ddr_shadow = 0; } usrp2_dboard_interface::~usrp2_dboard_interface(void){ @@ -83,70 +94,43 @@ double usrp2_dboard_interface::get_tx_clock_rate(void){ /*********************************************************************** * GPIO **********************************************************************/ -/*! - * Static function to convert a gpio bank enum - * to an over-the-wire value for the usrp2 control. - * \param bank the dboard interface gpio bank enum - * \return an over the wire representation - */ -static boost::uint8_t gpio_bank_to_otw(dboard_interface::gpio_bank_t bank){ - switch(bank){ - case uhd::usrp::dboard_interface::GPIO_TX_BANK: return USRP2_DIR_TX; - case uhd::usrp::dboard_interface::GPIO_RX_BANK: return USRP2_DIR_RX; - } - throw std::invalid_argument("unknown gpio bank type"); -} - void usrp2_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value){ - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO); - out_data.data.gpio_config.bank = gpio_bank_to_otw(bank); - out_data.data.gpio_config.value = htons(value); - out_data.data.gpio_config.mask = htons(0xffff); - - //send and recv - usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE); -} - -void usrp2_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value){ - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO); - out_data.data.gpio_config.bank = gpio_bank_to_otw(bank); - out_data.data.gpio_config.value = htons(value); - out_data.data.gpio_config.mask = htons(0xffff); - - //send and recv - usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE); + //calculate the new 32 bit ddr value + int shift = bank_to_shift(bank); + boost::uint32_t new_ddr_val = + (_ddr_shadow & ~(boost::uint32_t(0xffff) << shift)) //zero out new bits + | (boost::uint32_t(value) << shift); //or'ed in the new bits + + //poke in the value and shadow + _impl->poke(offsetof(gpio_regs_t, ddr) + 0xC800, new_ddr_val); + _ddr_shadow = new_ddr_val; } boost::uint16_t usrp2_dboard_interface::read_gpio(gpio_bank_t bank){ - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO); - out_data.data.gpio_config.bank = gpio_bank_to_otw(bank); - - //send and recv - usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE); - return ntohs(in_data.data.gpio_config.value); + boost::uint32_t data = _impl->peek(offsetof(gpio_regs_t, io) + 0xC800); + return boost::uint16_t(data >> bank_to_shift(bank)); } -void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask){ - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO); - out_data.data.atr_config.bank = gpio_bank_to_otw(bank); - out_data.data.atr_config.tx_value = htons(tx_value); - out_data.data.atr_config.rx_value = htons(rx_value); - out_data.data.atr_config.mask = htons(mask); - - //send and recv - usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE); +void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost::uint16_t value){ + //map the atr reg to an offset in register space + static const uhd::dict<atr_reg_t, int> reg_to_offset = boost::assign::map_list_of + (ATR_REG_IDLE, ATR_IDLE) (ATR_REG_TXONLY, ATR_TX) + (ATR_REG_RXONLY, ATR_RX) (ATR_REG_BOTH, ATR_FULL) + ; + int offset = reg_to_offset[reg]; + + //ensure a value exists in the shadow + if (not _atr_reg_shadows.has_key(reg)) _atr_reg_shadows[reg] = 0; + + //calculate the new 32 bit atr value + int shift = bank_to_shift(bank); + boost::uint32_t new_atr_val = + (_atr_reg_shadows[reg] & ~(boost::uint32_t(0xffff) << shift)) //zero out new bits + | (boost::uint32_t(value) << shift); //or'ed in the new bits + + //poke in the value and shadow + _impl->poke(offsetof(atr_regs_t, v) + 0xE400 + offset, new_atr_val); + _atr_reg_shadows[reg] = new_atr_val; } /*********************************************************************** @@ -160,44 +144,29 @@ void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_va */ static boost::uint8_t spi_dev_to_otw(dboard_interface::spi_dev_t dev){ switch(dev){ - case uhd::usrp::dboard_interface::SPI_TX_DEV: return USRP2_DIR_TX; - case uhd::usrp::dboard_interface::SPI_RX_DEV: return USRP2_DIR_RX; + case uhd::usrp::dboard_interface::SPI_DEV_TX: return USRP2_DIR_TX; + case uhd::usrp::dboard_interface::SPI_DEV_RX: return USRP2_DIR_RX; } throw std::invalid_argument("unknown spi device type"); } /*! - * Static function to convert a spi latch enum - * to an over-the-wire value for the usrp2 control. - * \param latch the dboard interface spi latch enum - * \return an over the wire representation - */ -static boost::uint8_t spi_latch_to_otw(dboard_interface::spi_latch_t latch){ - switch(latch){ - case uhd::usrp::dboard_interface::SPI_LATCH_RISE: return USRP2_CLK_EDGE_RISE; - case uhd::usrp::dboard_interface::SPI_LATCH_FALL: return USRP2_CLK_EDGE_FALL; - } - throw std::invalid_argument("unknown spi latch type"); -} - -/*! - * Static function to convert a spi push enum + * Static function to convert a spi edge enum * to an over-the-wire value for the usrp2 control. - * \param push the dboard interface spi push enum + * \param edge the dboard interface spi edge enum * \return an over the wire representation */ -static boost::uint8_t spi_push_to_otw(dboard_interface::spi_push_t push){ - switch(push){ - case uhd::usrp::dboard_interface::SPI_PUSH_RISE: return USRP2_CLK_EDGE_RISE; - case uhd::usrp::dboard_interface::SPI_PUSH_FALL: return USRP2_CLK_EDGE_FALL; +static boost::uint8_t spi_edge_to_otw(dboard_interface::spi_edge_t edge){ + switch(edge){ + case uhd::usrp::dboard_interface::SPI_EDGE_RISE: return USRP2_CLK_EDGE_RISE; + case uhd::usrp::dboard_interface::SPI_EDGE_FALL: return USRP2_CLK_EDGE_FALL; } - throw std::invalid_argument("unknown spi push type"); + throw std::invalid_argument("unknown spi edge type"); } dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi( spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, + spi_edge_t edge, const byte_vector_t &buf, bool readback ){ @@ -205,8 +174,7 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi( usrp2_ctrl_data_t out_data; out_data.id = htonl(USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO); out_data.data.spi_args.dev = spi_dev_to_otw(dev); - out_data.data.spi_args.latch = spi_latch_to_otw(latch); - out_data.data.spi_args.push = spi_push_to_otw(push); + out_data.data.spi_args.edge = spi_edge_to_otw(edge); out_data.data.spi_args.readback = (readback)? 1 : 0; out_data.data.spi_args.bytes = buf.size(); diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index 30fee6c32..565154305 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -45,67 +45,61 @@ extern "C" { #define USRP2_UDP_DATA_PORT 49153 typedef enum{ - USRP2_CTRL_ID_HUH_WHAT, + USRP2_CTRL_ID_HUH_WHAT = ' ', //USRP2_CTRL_ID_FOR_SURE, //TODO error condition enums //USRP2_CTRL_ID_SUX_MAN, - USRP2_CTRL_ID_GIVE_ME_YOUR_IP_ADDR_BRO, - USRP2_CTRL_ID_THIS_IS_MY_IP_ADDR_DUDE, - USRP2_CTRL_ID_HERE_IS_A_NEW_IP_ADDR_BRO, + USRP2_CTRL_ID_GIVE_ME_YOUR_IP_ADDR_BRO = 'a', + USRP2_CTRL_ID_THIS_IS_MY_IP_ADDR_DUDE = 'A', + USRP2_CTRL_ID_HERE_IS_A_NEW_IP_ADDR_BRO = 'b', - USRP2_CTRL_ID_GIVE_ME_YOUR_MAC_ADDR_BRO, - USRP2_CTRL_ID_THIS_IS_MY_MAC_ADDR_DUDE, - USRP2_CTRL_ID_HERE_IS_A_NEW_MAC_ADDR_BRO, + USRP2_CTRL_ID_GIVE_ME_YOUR_MAC_ADDR_BRO = 'm', + USRP2_CTRL_ID_THIS_IS_MY_MAC_ADDR_DUDE = 'M', + USRP2_CTRL_ID_HERE_IS_A_NEW_MAC_ADDR_BRO = 'n', - USRP2_CTRL_ID_GIVE_ME_YOUR_DBOARD_IDS_BRO, - USRP2_CTRL_ID_THESE_ARE_MY_DBOARD_IDS_DUDE, + USRP2_CTRL_ID_GIVE_ME_YOUR_DBOARD_IDS_BRO = 'd', + USRP2_CTRL_ID_THESE_ARE_MY_DBOARD_IDS_DUDE = 'D', - USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO, - USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE, + USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO = 'c', + USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE = 'C', - USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO, - USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE, + USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO = 's', + USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE = 'S', - USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO, - USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE, + USRP2_CTRL_ID_DO_AN_I2C_READ_FOR_ME_BRO = 'i', + USRP2_CTRL_ID_HERES_THE_I2C_DATA_DUDE = 'I', - USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO, - USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE, + USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO = 'h', + USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE = 'H', - USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO, - USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE, + USRP2_CTRL_ID_WRITE_THIS_TO_THE_AUX_DAC_BRO = 'x', + USRP2_CTRL_ID_DONE_WITH_THAT_AUX_DAC_DUDE = 'X', - USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO, - USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE, + USRP2_CTRL_ID_READ_FROM_THIS_AUX_ADC_BRO = 'y', + USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE = 'Y', - USRP2_CTRL_ID_DO_AN_I2C_READ_FOR_ME_BRO, - USRP2_CTRL_ID_HERES_THE_I2C_DATA_DUDE, + USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO = '\\', + USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE = '/', - USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO, - USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE, + USRP2_CTRL_ID_SEND_STREAM_COMMAND_FOR_ME_BRO = '{', + USRP2_CTRL_ID_GOT_THAT_STREAM_COMMAND_DUDE = '}', - USRP2_CTRL_ID_WRITE_THIS_TO_THE_AUX_DAC_BRO, - USRP2_CTRL_ID_DONE_WITH_THAT_AUX_DAC_DUDE, + USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO = '\'', + USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE = '"', - USRP2_CTRL_ID_READ_FROM_THIS_AUX_ADC_BRO, - USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE, + USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO = '<', + USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE = '>', - USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO, - USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE, + USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO = '-', + USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE = '_', - USRP2_CTRL_ID_SEND_STREAM_COMMAND_FOR_ME_BRO, - USRP2_CTRL_ID_GOT_THAT_STREAM_COMMAND_DUDE, + USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO = 'p', + USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE = 'P', - USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO, - USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE, + USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO = 'r', + USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE = 'R', - USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO, - USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE, - - USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO, - USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE, - - USRP2_CTRL_ID_PEACE_OUT + USRP2_CTRL_ID_PEACE_OUT = '~' } usrp2_ctrl_id_t; @@ -152,22 +146,8 @@ typedef struct{ _SINS_ uint8_t _pad; } clock_config; struct { - _SINS_ uint8_t bank; - _SINS_ uint8_t _pad[3]; - _SINS_ uint16_t value; - _SINS_ uint16_t mask; - } gpio_config; - struct { - _SINS_ uint8_t bank; - _SINS_ uint8_t _pad[3]; - _SINS_ uint16_t tx_value; - _SINS_ uint16_t rx_value; - _SINS_ uint16_t mask; - } atr_config; - struct { _SINS_ uint8_t dev; - _SINS_ uint8_t latch; - _SINS_ uint8_t push; + _SINS_ uint8_t edge; _SINS_ uint8_t readback; _SINS_ uint8_t bytes; _SINS_ uint8_t data[sizeof(_SINS_ uint32_t)]; @@ -210,6 +190,10 @@ typedef struct{ _SINS_ uint32_t rx_mux; _SINS_ uint32_t tx_mux; } mux_args; + struct { + _SINS_ uint32_t addr; + _SINS_ uint32_t data; + } poke_args; } data; } usrp2_ctrl_data_t; diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index b0ee395fb..e89fe8a63 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -173,6 +173,30 @@ double usrp2_impl::get_master_clock_freq(void){ return 100e6; } +void usrp2_impl::poke(boost::uint32_t addr, boost::uint32_t data){ + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO); + out_data.data.poke_args.addr = htonl(addr); + out_data.data.poke_args.data = htonl(data); + + //send and recv + usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data); + ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE); +} + +boost::uint32_t usrp2_impl::peek(boost::uint32_t addr){ + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO); + out_data.data.poke_args.addr = htonl(addr); + + //send and recv + usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data); + ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE); + return ntohl(out_data.data.poke_args.data); +} + /*********************************************************************** * Control Send/Recv **********************************************************************/ diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 3468a0cf1..1b6175195 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -102,6 +102,10 @@ public: //performs a control transaction usrp2_ctrl_data_t ctrl_send_and_recv(const usrp2_ctrl_data_t &); + //peek and poke registers + void poke(boost::uint32_t addr, boost::uint32_t data); + boost::uint32_t peek(boost::uint32_t addr); + //misc access methods double get_master_clock_freq(void); diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp new file mode 100644 index 000000000..9cf0b1fbc --- /dev/null +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -0,0 +1,57 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_USRP2_REGS_HPP +#define INCLUDED_USRP2_REGS_HPP + +#include <boost/cstdint.hpp> + +//////////////////////////////////////////////// +// GPIO, Slave 4 +// +// These go to the daughterboard i/o pins + +#define GPIO_BASE 0xC800 + +typedef struct { + boost::uint32_t io; // tx data in high 16, rx in low 16 + boost::uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 + boost::uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB + boost::uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB +} gpio_regs_t; + +// each 2-bit sel field is layed out this way +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric + +/////////////////////////////////////////////////// +// ATR Controller, Slave 11 + +#define ATR_BASE 0xE400 + +typedef struct { + boost::uint32_t v[16]; +} atr_regs_t; + +#define ATR_IDLE 0x0 // indicies into v +#define ATR_TX 0x1 +#define ATR_RX 0x2 +#define ATR_FULL 0x3 + +#endif /* INCLUDED_USRP2_REGS_HPP */ |