663 files changed, 1161 insertions, 591 deletions

diff --git a/control_lib/SYSCTRL.sav b/control_lib/SYSCTRL.sav
deleted file mode 100644
index 43bfef10e..000000000
--- a/control_lib/SYSCTRL.sav
+++ /dev/null
@@ -1,24 +0,0 @@
-[size] 1400 971
-[pos] -1 -1
-*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-system_control_tb.aux_clk
-@29
-system_control_tb.clk_fpga
-@28
-system_control_tb.dsp_clk
-system_control_tb.dsp_rst
-system_control_tb.proc_rst
-system_control_tb.rl_done
-system_control_tb.rl_rst
-system_control_tb.wb_clk
-system_control_tb.wb_rst
-system_control_tb.system_control.POR
-@22
-system_control_tb.system_control.POR_ctr[3:0]
-@28
-system_control_tb.clock_ready
-system_control_tb.system_control.half_clk
-system_control_tb.system_control.fin_ret_half
-system_control_tb.system_control.fin_ret_aux
-system_control_tb.system_control.gate_dsp_clk
diff --git a/control_lib/WB_SIM.sav b/control_lib/WB_SIM.sav
deleted file mode 100644
index 467cd35ef..000000000
--- a/control_lib/WB_SIM.sav
+++ /dev/null
@@ -1,47 +0,0 @@
-[size] 1400 971
-[pos] -1 -1
-*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-wb_sim.wb_rst
-wb_sim.wb_clk
-@23
-wb_sim.rom_data[47:0]
-@22
-wb_sim.rom_addr[15:0]
-@28
-wb_sim.start
-wb_sim.wb_ack
-@22
-wb_sim.wb_adr[15:0]
-@28
-wb_sim.wb_cyc
-@22
-wb_sim.wb_dat[31:0]
-wb_sim.wb_sel[3:0]
-@28
-wb_sim.wb_stb
-wb_sim.wb_we
-@22
-wb_sim.port_output[31:0]
-@28
-wb_sim.system_control.POR
-wb_sim.system_control.aux_clk
-wb_sim.system_control.clk_fpga
-@29
-wb_sim.system_control.done
-@28
-wb_sim.system_control.dsp_clk
-wb_sim.system_control.fin_del1
-wb_sim.system_control.fin_del2
-wb_sim.system_control.fin_del3
-wb_sim.system_control.fin_ret_aux
-@29
-wb_sim.system_control.fin_ret_fpga
-@28
-wb_sim.system_control.finished
-wb_sim.system_control.reset_out
-wb_sim.system_control.start
-wb_sim.system_control.started
-wb_sim.system_control.wb_clk_o
-wb_sim.system_control.wb_rst_o
-wb_sim.system_control.wb_rst_o_alt
diff --git a/control_lib/clock_control_tb.sav b/control_lib/clock_control_tb.sav
deleted file mode 100644
index be4001dc5..000000000
--- a/control_lib/clock_control_tb.sav
+++ /dev/null
@@ -1,28 +0,0 @@
-[size] 1400 971
-[pos] -1 -1
-*-7.848898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-clock_control_tb.aux_clk
-clock_control_tb.reset
-clock_control_tb.sclk
-clock_control_tb.sdi
-clock_control_tb.sdo
-clock_control_tb.sen
-@22
-clock_control_tb.clock_control.counter[7:0]
-@28
-clock_control_tb.clock_control.done
-@22
-clock_control_tb.clock_control.entry[5:0]
-@28
-clock_control_tb.clock_control.read
-clock_control_tb.clock_control.reset
-clock_control_tb.clock_control.sclk
-clock_control_tb.clock_control.w[1:0]
-clock_control_tb.sen
-clock_control_tb.sdo
-clock_control_tb.sclk
-clock_control_tb.clock_control.done
-clock_control_tb.clock_control.start
-@22
-clock_control_tb.clock_control.addr_data[20:0]
diff --git a/control_lib/newfifo/ll8_to_fifo19.v b/control_lib/newfifo/ll8_to_fifo19.v
deleted file mode 100644
index c65be5136..000000000
--- a/control_lib/newfifo/ll8_to_fifo19.v
+++ /dev/null
@@ -1,77 +0,0 @@
-
-module ll8_to_fifo19
-  (input clk, input reset, input clear,
-   input [7:0] ll_data,
-   input ll_sof_n,
-   input ll_eof_n,
-   input ll_src_rdy_n,
-   output ll_dst_rdy_n,
-
-   output [18:0] f19_data,
-   output f19_src_rdy_o,
-   input f19_dst_rdy_i );
-
-   // Why anybody would use active low in an FPGA is beyond me...
-   wire  ll_sof      = ~ll_sof_n;
-   wire  ll_eof      = ~ll_eof_n;
-   wire  ll_src_rdy  = ~ll_src_rdy_n;
-   wire  ll_dst_rdy;
-   assign    ll_dst_rdy_n  = ~ll_dst_rdy;
-
-   wire xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   //  wire xfer_in 	   = ll_src_rdy & ll_dst_rdy;   Not needed
-   
-   reg 	 f19_sof, f19_eof, f19_occ;
-   
-   reg [1:0] state;
-   reg [7:0] dat0, dat1;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0)|xfer_out))
-       f19_sof <= ll_sof;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state != 2)|xfer_out))
-       f19_eof <= ll_eof;
-
-   always @(posedge clk)
-     if(ll_eof)
-       f19_occ <= ~state[0];
-     else
-       f19_occ <= 0;
-   
-   always @(posedge clk)
-     if(reset)
-       state   <= 0;
-     else
-       if(ll_src_rdy)
-	 case(state)
-	   0 : 
-	     if(ll_eof)
-	       state <= 2;
-	     else
-	       state <= 1;
-	   1 : 
-	     state <= 2;
-	   2 : 
-	     if(xfer_out)
-	       state 	   <= 1;
-	 endcase // case(state)
-       else
-	 if(xfer_out)
-	   state 	   <= 0;
-
-   always @(posedge clk)
-     if(ll_src_rdy & (state==1))
-       dat1 		   <= ll_data;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0) | xfer_out))
-       dat0 		   <= ll_data;
-   
-   assign    ll_dst_rdy     = xfer_out | (state != 2);
-   assign    f19_data 	    = {f19_occ,f19_eof,f19_sof,dat0,dat1};
-   assign    f19_src_rdy_o  = (state == 2);
-      
-endmodule // ll8_to_fifo19
-
diff --git a/opencores/i2c/sim/i2c_verilog/run/ncverilog.log b/opencores/i2c/sim/i2c_verilog/run/ncverilog.log
deleted file mode 100644
index 420a1b9e5..000000000
--- a/opencores/i2c/sim/i2c_verilog/run/ncverilog.log
+++ /dev/null
@@ -1,118 +0,0 @@
-ncverilog: v03.40.(b001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
-ncverilog: v03.40.(b001): Started on Jun 15, 2002 at 13:36:36
-ncverilog
-	+access+rwc
-	+linedebug
-	+define+"WAVES"
-	+incdir+../../../../bench/verilog
-	+incdir+../../../../rtl/verilog
-	+libext+.v
-	-y
-	/tools/synopsys/dw/sim_ver/
-	../../../../rtl/verilog/i2c_master_bit_ctrl.v
-	../../../../rtl/verilog/i2c_master_byte_ctrl.v
-	../../../../rtl/verilog/i2c_master_top.v
-	../../../../bench/verilog/i2c_slave_model.v
-	../../../../bench/verilog/wb_master_model.v
-	../../../../bench/verilog/tst_bench_top.v
-
-ncverilog: *W,BADPRF: The +linedebug option may have an adverse performance impact.
-file: ../../../../rtl/verilog/i2c_master_bit_ctrl.v
-	module worklib.i2c_master_bit_ctrl:v (up-to-date)
-		errors: 0, warnings: 0
-file: ../../../../rtl/verilog/i2c_master_byte_ctrl.v
-	module worklib.i2c_master_byte_ctrl:v (up-to-date)
-		errors: 0, warnings: 0
-file: ../../../../rtl/verilog/i2c_master_top.v
-	module worklib.i2c_master_top:v (up-to-date)
-		errors: 0, warnings: 0
-file: ../../../../bench/verilog/i2c_slave_model.v
-	module worklib.i2c_slave_model:v (up-to-date)
-		errors: 0, warnings: 0
-file: ../../../../bench/verilog/wb_master_model.v
-	module worklib.wb_master_model:v (up-to-date)
-		errors: 0, warnings: 0
-file: ../../../../bench/verilog/tst_bench_top.v
-	module worklib.tst_bench_top:v
-		errors: 0, warnings: 0
-ncvlog: *W,LIBNOU: Library "/tools/synopsys/dw/sim_ver/" given but not used.
-	Total errors/warnings found outside modules and primitives:
-		errors: 0, warnings: 1
-		Caching library 'worklib' ....... Done
-	Elaborating the design hierarchy:
-	Building instance overlay tables: .................... Done
-	Generating native compiled code:
-		worklib.tst_bench_top:v <0x7fb52c98>
-			streams:  12, words: 59009
-	Loading native compiled code:     .................... Done
-	Building instance specific data structures.
-	Design hierarchy summary:
-		                  Instances  Unique
-		Modules:                  6       6
-		Primitives:               2       1
-		Registers:               68      68
-		Scalar wires:            48       -
-		Expanded wires:          36       2
-		Vectored wires:           6       -
-		Always blocks:           23      23
-		Initial blocks:           3       3
-		Cont. assignments:       28      28
-		Pseudo assignments:      11      14
-		Simulation timescale:  10ps
-	Writing initial simulation snapshot: worklib.tst_bench_top:v
-Loading snapshot worklib.tst_bench_top:v .................... Done
-ncsim> source /cds/tools/inca/files/ncsimrc
-ncsim> run
-INFO: Signal dump enabled ...
-
-
-
-status:                    0 Testbench started
-
-
-
-INFO: WISHBONE MASTER MODEL INSTANTIATED (tst_bench_top.u0)
-
-status:                19500 done reset
-status:                23600 programmed registers
-status:                25600 verified registers
-status:                27600 enabled core
-status:                30600 generate 'start', write cmd a0 (slave address+write)
-status:              2582600 tip==0
-status:              2585600 write slave memory address 01
-status:              4877600 tip==0
-status:              4880600 write data a5
-status:              7172600 tip==0
-status:              7175600 write next data 5a, generate 'stop'
-status:              9467600 tip==0
-status:             19467600 wait 100us
-status:             19470600 generate 'start', write cmd a0 (slave address+write)
-status:             22014600 tip==0
-status:             22017600 write slave address 01
-status:             24309600 tip==0
-status:             24312600 generate 'repeated start', write cmd a1 (slave address+read)
-status:             26858600 tip==0
-status:             26860600 read + ack
-status:             29154600 tip==0
-status:             29158600 read + ack
-status:             31448600 tip==0
-status:             31452600 read + ack
-status:             33744600 tip==0
-status:             33746600 received xx from 3rd read address
-status:             33748600 read + nack
-status:             36038600 tip==0
-status:             36040600 received xx from 4th read address
-status:             36043600 generate 'start', write cmd a0 (slave address+write). Check invalid address
-status:             38589600 tip==0
-status:             38592600 write slave memory address 10
-status:             40884600 tip==0
-status:             40884600 Check for nack
-status:             40886600 generate 'stop'
-status:             40888600 tip==0
-
-
-status:             43388600 Testbench done
-Simulation stopped via $stop(1) at time 433886 NS + 0
-/mnt/pooh/projects/I2C/bench/verilog/tst_bench_top.v:427 			$stop;
-ncsim> exit
-ncverilog: v03.40.(b001): Exiting on Jun 15, 2002 at 13:47:48  (total: 00:11:12)
diff --git a/simple_gemac/ll8_shortfifo.v b/simple_gemac/ll8_shortfifo.v
deleted file mode 100644
index e69de29bb..000000000
--- a/simple_gemac/ll8_shortfifo.v
+++ /dev/null
diff --git a/testbench/BOOTSTRAP.sav b/testbench/BOOTSTRAP.sav
deleted file mode 100644
index 41501945f..000000000
--- a/testbench/BOOTSTRAP.sav
+++ /dev/null
@@ -1,82 +0,0 @@
-[size] 1400 971
-[pos] -1 -1
-*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-u2_sim_top.cpld_clk
-u2_sim_top.cpld_detached
-u2_sim_top.cpld_din
-u2_sim_top.cpld_done
-u2_sim_top.cpld_start
-u2_sim_top.aux_clk
-u2_sim_top.clk_fpga
-u2_sim_top.clk_sel[1:0]
-u2_sim_top.clk_en[1:0]
-u2_sim_top.u2_basic.ram_loader_rst
-u2_sim_top.u2_basic.wb_rst
-u2_sim_top.u2_basic.sysctrl.POR
-u2_sim_top.u2_basic.sysctrl.ram_loader_done_i
-u2_sim_top.cpld_model.sclk
-u2_sim_top.cpld_model.start
-u2_sim_top.u2_basic.ram_loader.rst_i
-u2_sim_top.sen_clk
-u2_sim_top.sen_dac
-u2_sim_top.sclk
-@22
-u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0]
-u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0]
-u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0]
-@28
-u2_sim_top.u2_basic.shared_spi.wb_we_i
-u2_sim_top.u2_basic.shared_spi.wb_stb_i
-u2_sim_top.u2_basic.shared_spi.wb_ack_o
-@22
-u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0]
-u2_sim_top.u2_basic.shared_spi.ctrl[13:0]
-u2_sim_top.u2_basic.shared_spi.divider[15:0]
-u2_sim_top.u2_basic.shared_spi.char_len[6:0]
-u2_sim_top.u2_basic.shared_spi.ss[7:0]
-u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0]
-u2_sim_top.u2_basic.shared_spi.rx[127:0]
-@28
-u2_sim_top.u2_basic.control_lines.wb_stb_i
-u2_sim_top.u2_basic.control_lines.wb_we_i
-@22
-u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0]
-u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0]
-u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0]
-@28
-u2_sim_top.u2_basic.control_lines.wb_cyc_i
-@22
-u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0]
-@28
-u2_sim_top.clock_ready
-u2_sim_top.u2_basic.ram_loader.done_o
-u2_sim_top.u2_basic.dsp_rst
-u2_sim_top.u2_basic.ram_loader_rst
-u2_sim_top.u2_basic.wb_rst
-@22
-u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0]
-@28
-u2_sim_top.u2_basic.aeMB.iwb_ack_i
-u2_sim_top.u2_basic.ram_loader_done
-@22
-u2_sim_top.u2_basic.iram_rd_adr[15:0]
-u2_sim_top.u2_basic.iram_rd_dat[31:0]
-@28
-u2_sim_top.u2_basic.iram_wr_we
-u2_sim_top.u2_basic.iram_wr_stb
-@22
-u2_sim_top.u2_basic.iram_wr_sel[3:0]
-u2_sim_top.u2_basic.iram_wr_dat[31:0]
-u2_sim_top.u2_basic.iram_wr_adr[15:0]
-@28
-u2_sim_top.u2_basic.ram_loader.ram_loader_done_o
-u2_sim_top.u2_basic.ID_ram.dwb_we_i
-u2_sim_top.u2_basic.ID_ram.iwb_we_i
-u2_sim_top.u2_basic.ram_loader.ram_we
-u2_sim_top.u2_basic.ram_loader.ram_we_q
-u2_sim_top.u2_basic.ram_loader.ram_we_s
-u2_sim_top.u2_basic.ram_loader.wb_ack_i
-u2_sim_top.u2_basic.ID_ram.iwb_ack_o
-u2_sim_top.u2_basic.ID_ram.iwb_stb_i
-u2_sim_top.u2_basic.ID_ram.wb_rst_i
diff --git a/testbench/PAUSE.sav b/testbench/PAUSE.sav
deleted file mode 100644
index f5e1ea1ac..000000000
--- a/testbench/PAUSE.sav
+++ /dev/null
@@ -1,62 +0,0 @@
-[size] 1400 967
-[pos] -1 -1
-*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] u2_sim_top.
-[treeopen] u2_sim_top.u2_basic.
-[treeopen] u2_sim_top.u2_basic.MAC_top.
-[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx.
-@22
-u2_sim_top.GMII_TXD[7:0]
-@28
-u2_sim_top.GMII_TX_EN
-@200
--
-@24
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0]
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0]
-@28
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en
-@22
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0]
-@28
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk
-@24
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0]
-@28
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk
-@200
--
-@28
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1
-@200
--
-@28
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1
-@200
--
-@28
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply
-@22
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0]
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
-@28
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en
-u2_sim_top.u2_basic.proc_int
-@22
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0]
-u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
-@25
-u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0]
diff --git a/testbench/SERDES.sav b/testbench/SERDES.sav
deleted file mode 100644
index 3bb6ba929..000000000
--- a/testbench/SERDES.sav
+++ /dev/null
@@ -1,35 +0,0 @@
-[size] 1400 967
-[pos] -1 -1
-*-30.885946 6591910000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] u2_sim_top.
-[treeopen] u2_sim_top.u2_basic.
-[treeopen] u2_sim_top.u2_basic.serdes.
-@22
-u2_sim_top.u2_basic.serdes.ser_t[15:0]
-@28
-u2_sim_top.u2_basic.serdes.ser_tklsb
-u2_sim_top.u2_basic.serdes.ser_tkmsb
-u2_sim_top.u2_basic.ram_loader.ram_loader_done_o
-u2_sim_top.u2_basic.proc_int
-@22
-u2_sim_top.u2_basic.serdes.fifo_space[15:0]
-@28
-u2_sim_top.u2_basic.serdes.inhibit_tx
-u2_sim_top.u2_basic.serdes.send_xoff
-u2_sim_top.u2_basic.serdes.send_xon
-u2_sim_top.u2_basic.serdes.sent
-u2_sim_top.u2_basic.serdes.xoff_rcvd
-u2_sim_top.u2_basic.serdes.xon_rcvd
-u2_sim_top.u2_basic.serdes.serdes_rx.wr_write_o
-u2_sim_top.u2_basic.serdes.serdes_rx.wr_done_o
-u2_sim_top.u2_basic.serdes.serdes_rx.write
-@22
-u2_sim_top.u2_basic.serdes.serdes_rx.line_i[31:0]
-@28
-(0)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0]
-(1)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0]
-@22
-#chosen_data[15:0] (2)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (3)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (4)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (5)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (6)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (7)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (8)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (9)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (10)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (11)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (12)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (13)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (14)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (15)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (16)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (17)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0]
-u2_sim_top.u2_basic.serdes.ser_t[15:0]
-@28
-u2_sim_top.u2_basic.serdes.ser_tklsb
diff --git a/testbench/U2_SIM.sav b/testbench/U2_SIM.sav
deleted file mode 100644
index d320c2b6c..000000000
--- a/testbench/U2_SIM.sav
+++ /dev/null
@@ -1,95 +0,0 @@
-[size] 1400 971
-[pos] -1 -1
-*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-u2_sim_top.adc_oen_a
-u2_sim_top.adc_oen_b
-u2_sim_top.adc_pdn_a
-u2_sim_top.adc_pdn_b
-u2_sim_top.aux_clk
-u2_sim_top.POR
-u2_sim_top.clk_fpga
-u2_sim_top.clk_en[1:0]
-u2_sim_top.clk_sel[1:0]
-u2_sim_top.led1
-u2_sim_top.led2
-u2_sim_top.sclk
-u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0]
-u2_sim_top.sda_pad_o
-u2_sim_top.sda_pad_oen_o
-u2_sim_top.sdi
-u2_sim_top.sdo
-u2_sim_top.sen_clk
-u2_sim_top.sen_dac
-u2_sim_top.ser_enable
-u2_sim_top.ser_loopen
-u2_sim_top.ser_prbsen
-u2_sim_top.ser_rx_en
-u2_sim_top.u2_basic.sysctrl.start
-u2_sim_top.u2_basic.sysctrl.POR
-u2_sim_top.u2_basic.done
-u2_sim_top.u2_basic.sysctrl.POR
-u2_sim_top.u2_basic.sysctrl.aux_clk
-u2_sim_top.u2_basic.sysctrl.clk_fpga
-u2_sim_top.u2_basic.sysctrl.done
-u2_sim_top.u2_basic.bus_writer.start
-u2_sim_top.u2_basic.bus_writer.done
-@22
-u2_sim_top.u2_basic.bus_writer.rom_addr[15:0]
-u2_sim_top.u2_basic.bus_writer.rom_data[47:0]
-u2_sim_top.u2_basic.bus_writer.state[3:0]
-@29
-u2_sim_top.u2_basic.bus_writer.wb_ack_i
-@22
-u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0]
-@28
-u2_sim_top.u2_basic.bus_writer.wb_clk_i
-u2_sim_top.u2_basic.bus_writer.wb_cyc_o
-@22
-u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0]
-u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0]
-@28
-u2_sim_top.u2_basic.bus_writer.wb_stb_o
-u2_sim_top.u2_basic.bus_writer.wb_we_o
-u2_sim_top.u2_basic.bus_writer.wb_rst_i
-u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0]
-u2_sim_top.sda_pad_i
-u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i
-u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o
-@22
-u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0]
-u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0]
-@28
-u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i
-u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i
-u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o
-u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o
-u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o
-u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o
-u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i
-u2_sim_top.u2_basic.control_lines.wb_cyc_i
-u2_sim_top.u2_basic.control_lines.wb_stb_i
-u2_sim_top.u2_basic.control_lines.wb_we_i
-u2_sim_top.u2_basic.control_lines.wb_ack_o
-u2_sim_top.u2_basic.s0_ack
-@22
-u2_sim_top.u2_basic.control_lines.internal_reg[31:0]
-u2_sim_top.u2_basic.control_lines.port_output[31:0]
-@28
-u2_sim_top.u2_basic.led1
-u2_sim_top.u2_basic.led2
-@22
-u2_sim_top.u2_basic.misc_outs[7:0]
-u2_sim_top.u2_basic.clock_outs[7:0]
-u2_sim_top.u2_basic.adc_outs[7:0]
-u2_sim_top.u2_basic.serdes_outs[7:0]
-@28
-u2_sim_top.u2_basic.shared_spi.miso_pad_i
-u2_sim_top.u2_basic.shared_spi.mosi_pad_o
-@22
-u2_sim_top.u2_basic.shared_spi.ss[7:0]
-u2_sim_top.u2_basic.shared_spi.divider[15:0]
-@28
-u2_sim_top.u2_basic.shared_spi.sclk_pad_o
-@22
-u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0]
diff --git a/.gitignore b/usrp2/.gitignore
index a12cca79c..a12cca79c 100644
--- a/.gitignore
+++ b/usrp2/.gitignore
diff --git a/boot_cpld/.gitignore b/usrp2/boot_cpld/.gitignore
index 45cf9a86b..45cf9a86b 100644
--- a/boot_cpld/.gitignore
+++ b/usrp2/boot_cpld/.gitignore
diff --git a/boot_cpld/_impact.cmd b/usrp2/boot_cpld/_impact.cmd
index 4af86cb02..4af86cb02 100755
--- a/boot_cpld/_impact.cmd
+++ b/usrp2/boot_cpld/_impact.cmd
diff --git a/boot_cpld/boot_cpld.ipf b/usrp2/boot_cpld/boot_cpld.ipf
index 8acb6821e..8acb6821e 100755
--- a/boot_cpld/boot_cpld.ipf
+++ b/usrp2/boot_cpld/boot_cpld.ipf
diff --git a/boot_cpld/boot_cpld.ise b/usrp2/boot_cpld/boot_cpld.ise
index 7252d3768..7252d3768 100755
--- a/boot_cpld/boot_cpld.ise
+++ b/usrp2/boot_cpld/boot_cpld.ise
diff --git a/boot_cpld/boot_cpld.lfp b/usrp2/boot_cpld/boot_cpld.lfp
index 0f0c8f2e2..0f0c8f2e2 100755
--- a/boot_cpld/boot_cpld.lfp
+++ b/usrp2/boot_cpld/boot_cpld.lfp
diff --git a/boot_cpld/boot_cpld.ucf b/usrp2/boot_cpld/boot_cpld.ucf
index 789bb1d96..789bb1d96 100755
--- a/boot_cpld/boot_cpld.ucf
+++ b/usrp2/boot_cpld/boot_cpld.ucf
diff --git a/boot_cpld/boot_cpld.v b/usrp2/boot_cpld/boot_cpld.v
index 2ffc6daed..2ffc6daed 100755
--- a/boot_cpld/boot_cpld.v
+++ b/usrp2/boot_cpld/boot_cpld.v
diff --git a/control_lib/.gitignore b/usrp2/control_lib/.gitignore
index 025385cff..025385cff 100644
--- a/control_lib/.gitignore
+++ b/usrp2/control_lib/.gitignore
diff --git a/control_lib/CRC16_D16.v b/usrp2/control_lib/CRC16_D16.v
index 7e2816af1..7e2816af1 100644
--- a/control_lib/CRC16_D16.v
+++ b/usrp2/control_lib/CRC16_D16.v
diff --git a/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v
index fed2791f9..fed2791f9 100644
--- a/control_lib/atr_controller.v
+++ b/usrp2/control_lib/atr_controller.v
diff --git a/control_lib/bin2gray.v b/usrp2/control_lib/bin2gray.v
index 513402163..513402163 100644
--- a/control_lib/bin2gray.v
+++ b/usrp2/control_lib/bin2gray.v
diff --git a/control_lib/bootrom.mem b/usrp2/control_lib/bootrom.mem
index d688b4342..d688b4342 100644
--- a/control_lib/bootrom.mem
+++ b/usrp2/control_lib/bootrom.mem
diff --git a/control_lib/clock_bootstrap_rom.v b/usrp2/control_lib/clock_bootstrap_rom.v
index 46563db65..46563db65 100644
--- a/control_lib/clock_bootstrap_rom.v
+++ b/usrp2/control_lib/clock_bootstrap_rom.v
diff --git a/control_lib/clock_control.v b/usrp2/control_lib/clock_control.v
index 1bbe6bd75..1bbe6bd75 100644
--- a/control_lib/clock_control.v
+++ b/usrp2/control_lib/clock_control.v
diff --git a/control_lib/clock_control_tb.v b/usrp2/control_lib/clock_control_tb.v
index 4e705cf23..4e705cf23 100644
--- a/control_lib/clock_control_tb.v
+++ b/usrp2/control_lib/clock_control_tb.v
diff --git a/control_lib/cmdfile b/usrp2/control_lib/cmdfile
index cb3756cfc..cb3756cfc 100644
--- a/control_lib/cmdfile
+++ b/usrp2/control_lib/cmdfile
diff --git a/control_lib/dcache.v b/usrp2/control_lib/dcache.v
index 9063bf02a..9063bf02a 100644
--- a/control_lib/dcache.v
+++ b/usrp2/control_lib/dcache.v
diff --git a/control_lib/decoder_3_8.v b/usrp2/control_lib/decoder_3_8.v
index 729b45d18..729b45d18 100644
--- a/control_lib/decoder_3_8.v
+++ b/usrp2/control_lib/decoder_3_8.v
diff --git a/control_lib/dpram32.v b/usrp2/control_lib/dpram32.v
index 4da621823..4da621823 100644
--- a/control_lib/dpram32.v
+++ b/usrp2/control_lib/dpram32.v
diff --git a/control_lib/fifo_tb.v b/usrp2/control_lib/fifo_tb.v
index 616fe4ee7..616fe4ee7 100644
--- a/control_lib/fifo_tb.v
+++ b/usrp2/control_lib/fifo_tb.v
diff --git a/control_lib/gray2bin.v b/usrp2/control_lib/gray2bin.v
index 5df40bd52..5df40bd52 100644
--- a/control_lib/gray2bin.v
+++ b/usrp2/control_lib/gray2bin.v
diff --git a/control_lib/gray_send.v b/usrp2/control_lib/gray_send.v
index 7fc07d40c..7fc07d40c 100644
--- a/control_lib/gray_send.v
+++ b/usrp2/control_lib/gray_send.v
diff --git a/control_lib/icache.v b/usrp2/control_lib/icache.v
index bd21f47cc..bd21f47cc 100644
--- a/control_lib/icache.v
+++ b/usrp2/control_lib/icache.v
diff --git a/control_lib/longfifo.v b/usrp2/control_lib/longfifo.v
index bf3338e0b..bf3338e0b 100644
--- a/control_lib/longfifo.v
+++ b/usrp2/control_lib/longfifo.v
diff --git a/control_lib/medfifo.v b/usrp2/control_lib/medfifo.v
index 5a77e8c16..5a77e8c16 100644
--- a/control_lib/medfifo.v
+++ b/usrp2/control_lib/medfifo.v
diff --git a/control_lib/mux4.v b/usrp2/control_lib/mux4.v
index 31c85c832..31c85c832 100644
--- a/control_lib/mux4.v
+++ b/usrp2/control_lib/mux4.v
diff --git a/control_lib/mux8.v b/usrp2/control_lib/mux8.v
index 9db96a60f..9db96a60f 100644
--- a/control_lib/mux8.v
+++ b/usrp2/control_lib/mux8.v
diff --git a/control_lib/mux_32_4.v b/usrp2/control_lib/mux_32_4.v
index fef5812e9..fef5812e9 100644
--- a/control_lib/mux_32_4.v
+++ b/usrp2/control_lib/mux_32_4.v
diff --git a/control_lib/newfifo/.gitignore b/usrp2/control_lib/newfifo/.gitignore
index cba7efc8e..cba7efc8e 100644
--- a/control_lib/newfifo/.gitignore
+++ b/usrp2/control_lib/newfifo/.gitignore
diff --git a/control_lib/newfifo/buffer_int.v b/usrp2/control_lib/newfifo/buffer_int.v
index b45ed3532..b45ed3532 100644
--- a/control_lib/newfifo/buffer_int.v
+++ b/usrp2/control_lib/newfifo/buffer_int.v
diff --git a/control_lib/newfifo/buffer_int_tb.v b/usrp2/control_lib/newfifo/buffer_int_tb.v
index df54dcc0b..df54dcc0b 100644
--- a/control_lib/newfifo/buffer_int_tb.v
+++ b/usrp2/control_lib/newfifo/buffer_int_tb.v
diff --git a/control_lib/newfifo/buffer_pool.v b/usrp2/control_lib/newfifo/buffer_pool.v
index 41ac1deb3..41ac1deb3 100644
--- a/control_lib/newfifo/buffer_pool.v
+++ b/usrp2/control_lib/newfifo/buffer_pool.v
diff --git a/control_lib/newfifo/buffer_pool_tb.v b/usrp2/control_lib/newfifo/buffer_pool_tb.v
index 91a01d268..91a01d268 100644
--- a/control_lib/newfifo/buffer_pool_tb.v
+++ b/usrp2/control_lib/newfifo/buffer_pool_tb.v
diff --git a/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
index e22ca0a49..5f9aeff9b 100644
--- a/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
@@ -7,7 +7,8 @@ module fifo19_to_fifo36
 
    output [35:0] f36_dataout,
    output f36_src_rdy_o,
-   input f36_dst_rdy_i
+   input f36_dst_rdy_i,
+   output [31:0] debug
    );
 
    reg 	 f36_sof, f36_eof, f36_occ;
@@ -50,7 +51,9 @@ module fifo19_to_fifo36
 	     state <= 2;
 	   2 : 
 	     if(xfer_out)
-	       state 	   <= 1;
+	       if(~f19_eof)
+		 state 	   <= 1;
+	   // remain in state 2 if we are at eof
 	 endcase // case(state)
        else
 	 if(xfer_out)
@@ -67,5 +70,7 @@ module fifo19_to_fifo36
    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
    assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
    assign    f36_src_rdy_o  = (state == 2);
-      
+
+   assign    debug = state;
+   
 endmodule // fifo19_to_fifo36
diff --git a/control_lib/newfifo/fifo19_to_ll8.v b/usrp2/control_lib/newfifo/fifo19_to_ll8.v
index 4707f7523..4707f7523 100644
--- a/control_lib/newfifo/fifo19_to_ll8.v
+++ b/usrp2/control_lib/newfifo/fifo19_to_ll8.v
diff --git a/control_lib/newfifo/fifo36_to_fifo18.v b/usrp2/control_lib/newfifo/fifo36_to_fifo18.v
index b636ab9ca..b636ab9ca 100644
--- a/control_lib/newfifo/fifo36_to_fifo18.v
+++ b/usrp2/control_lib/newfifo/fifo36_to_fifo18.v
diff --git a/control_lib/newfifo/fifo36_to_fifo19.v b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
index de249aaeb..de249aaeb 100644
--- a/control_lib/newfifo/fifo36_to_fifo19.v
+++ b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
diff --git a/control_lib/newfifo/fifo36_to_ll8.v b/usrp2/control_lib/newfifo/fifo36_to_ll8.v
index 0dee1dfc6..0dee1dfc6 100644
--- a/control_lib/newfifo/fifo36_to_ll8.v
+++ b/usrp2/control_lib/newfifo/fifo36_to_ll8.v
diff --git a/control_lib/newfifo/fifo_2clock.v b/usrp2/control_lib/newfifo/fifo_2clock.v
index 34c85ccb4..34c85ccb4 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/usrp2/control_lib/newfifo/fifo_2clock.v
diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/usrp2/control_lib/newfifo/fifo_2clock_cascade.v
index 5ce726977..5ce726977 100644
--- a/control_lib/newfifo/fifo_2clock_cascade.v
+++ b/usrp2/control_lib/newfifo/fifo_2clock_cascade.v
diff --git a/control_lib/newfifo/fifo_cascade.v b/usrp2/control_lib/newfifo/fifo_cascade.v
index fdd8449bc..fdd8449bc 100644
--- a/control_lib/newfifo/fifo_cascade.v
+++ b/usrp2/control_lib/newfifo/fifo_cascade.v
diff --git a/control_lib/newfifo/fifo_long.v b/usrp2/control_lib/newfifo/fifo_long.v
index 0426779f6..0426779f6 100644
--- a/control_lib/newfifo/fifo_long.v
+++ b/usrp2/control_lib/newfifo/fifo_long.v
diff --git a/control_lib/newfifo/fifo_new_tb.vcd b/usrp2/control_lib/newfifo/fifo_new_tb.vcd
index 796889e7d..796889e7d 100644
--- a/control_lib/newfifo/fifo_new_tb.vcd
+++ b/usrp2/control_lib/newfifo/fifo_new_tb.vcd
diff --git a/control_lib/newfifo/fifo_short.v b/usrp2/control_lib/newfifo/fifo_short.v
index 53a7603c7..53a7603c7 100644
--- a/control_lib/newfifo/fifo_short.v
+++ b/usrp2/control_lib/newfifo/fifo_short.v
diff --git a/control_lib/newfifo/fifo_spec.txt b/usrp2/control_lib/newfifo/fifo_spec.txt
index 133b9fa8e..133b9fa8e 100644
--- a/control_lib/newfifo/fifo_spec.txt
+++ b/usrp2/control_lib/newfifo/fifo_spec.txt
diff --git a/control_lib/newfifo/fifo_tb.v b/usrp2/control_lib/newfifo/fifo_tb.v
index f561df7fa..f561df7fa 100644
--- a/control_lib/newfifo/fifo_tb.v
+++ b/usrp2/control_lib/newfifo/fifo_tb.v
diff --git a/control_lib/newfifo/ll8_shortfifo.v b/usrp2/control_lib/newfifo/ll8_shortfifo.v
index 39ada9a4f..39ada9a4f 100644
--- a/control_lib/newfifo/ll8_shortfifo.v
+++ b/usrp2/control_lib/newfifo/ll8_shortfifo.v
diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
new file mode 100644
index 000000000..af3b91afb
--- /dev/null
+++ b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
@@ -0,0 +1,73 @@
+
+module ll8_to_fifo19
+  (input clk, input reset, input clear,
+   input [7:0] ll_data,
+   input ll_sof_n,
+   input ll_eof_n,
+   input ll_src_rdy_n,
+   output ll_dst_rdy_n,
+
+   output [18:0] f19_data,
+   output f19_src_rdy_o,
+   input f19_dst_rdy_i );
+   
+   localparam XFER_EMPTY       = 0;
+   localparam XFER_HALF        = 1;
+   localparam XFER_HALF_WRITE  = 3;
+   
+   // Why anybody would use active low in an FPGA is beyond me...
+   wire  ll_sof      = ~ll_sof_n;
+   wire  ll_eof      = ~ll_eof_n;
+   wire  ll_src_rdy  = ~ll_src_rdy_n;
+   wire  ll_dst_rdy;
+   assign    ll_dst_rdy_n  = ~ll_dst_rdy;
+   
+   wire  xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire  xfer_in 	   = ll_src_rdy & ll_dst_rdy; 
+   
+   reg 	 hold_sof;
+   wire  f19_sof, f19_eof, f19_occ;
+   
+   reg [1:0] state;
+   reg [7:0] hold_reg;
+   
+   always @(posedge clk)
+     if(ll_src_rdy & (state==XFER_EMPTY))
+       hold_reg 	      <= ll_data;
+   
+   always @(posedge clk)
+     if(ll_sof & (state==XFER_EMPTY))
+       hold_sof 	      <= 1;
+     else if(xfer_out)
+       hold_sof 	      <= 0;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state 		      <= XFER_EMPTY;
+     else
+       case(state)
+	 XFER_EMPTY :
+	   if(ll_src_rdy)
+	     if(ll_eof)
+	       state 	      <= XFER_HALF_WRITE;
+	     else
+	       state 	      <= XFER_HALF;
+	 XFER_HALF :
+	   if(ll_src_rdy & f19_dst_rdy_i)
+	       state 	      <= XFER_EMPTY;
+         XFER_HALF_WRITE :
+	   if(f19_dst_rdy_i)
+	     state 	<= XFER_EMPTY;
+       endcase // case (state)
+      
+   assign ll_dst_rdy 	 = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
+   assign f19_src_rdy_o  = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+   
+   assign f19_sof 	 = hold_sof | (ll_sof & (state==XFER_HALF));
+   assign f19_eof 	 = (state == XFER_HALF_WRITE) | ll_eof;
+   assign f19_occ 	 = (state == XFER_HALF_WRITE);
+   
+   assign f19_data 	 = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
+      
+endmodule // ll8_to_fifo19
+
diff --git a/control_lib/newfifo/ll8_to_fifo36.v b/usrp2/control_lib/newfifo/ll8_to_fifo36.v
index 108daa903..108daa903 100644
--- a/control_lib/newfifo/ll8_to_fifo36.v
+++ b/usrp2/control_lib/newfifo/ll8_to_fifo36.v
diff --git a/control_lib/nsgpio.v b/usrp2/control_lib/nsgpio.v
index 937ea7020..937ea7020 100644
--- a/control_lib/nsgpio.v
+++ b/usrp2/control_lib/nsgpio.v
diff --git a/control_lib/oneshot_2clk.v b/usrp2/control_lib/oneshot_2clk.v
index 72f16a4b3..72f16a4b3 100644
--- a/control_lib/oneshot_2clk.v
+++ b/usrp2/control_lib/oneshot_2clk.v
diff --git a/control_lib/pic.v b/usrp2/control_lib/pic.v
index 9b9944d4a..9b9944d4a 100644
--- a/control_lib/pic.v
+++ b/usrp2/control_lib/pic.v
diff --git a/control_lib/priority_enc.v b/usrp2/control_lib/priority_enc.v
index 916192445..916192445 100644
--- a/control_lib/priority_enc.v
+++ b/usrp2/control_lib/priority_enc.v
diff --git a/control_lib/ram_2port.v b/usrp2/control_lib/ram_2port.v
index 6c8332b9c..6c8332b9c 100644
--- a/control_lib/ram_2port.v
+++ b/usrp2/control_lib/ram_2port.v
diff --git a/control_lib/ram_harv_cache.v b/usrp2/control_lib/ram_harv_cache.v
index 29fdebf7a..29fdebf7a 100644
--- a/control_lib/ram_harv_cache.v
+++ b/usrp2/control_lib/ram_harv_cache.v
diff --git a/control_lib/ram_loader.v b/usrp2/control_lib/ram_loader.v
index cb67de739..cb67de739 100644
--- a/control_lib/ram_loader.v
+++ b/usrp2/control_lib/ram_loader.v
diff --git a/control_lib/ram_wb_harvard.v b/usrp2/control_lib/ram_wb_harvard.v
index c3efc12e0..c3efc12e0 100644
--- a/control_lib/ram_wb_harvard.v
+++ b/usrp2/control_lib/ram_wb_harvard.v
diff --git a/control_lib/reset_sync.v b/usrp2/control_lib/reset_sync.v
index 94d966840..94d966840 100644
--- a/control_lib/reset_sync.v
+++ b/usrp2/control_lib/reset_sync.v
diff --git a/control_lib/sd_spi.v b/usrp2/control_lib/sd_spi.v
index 3f4d7f46a..3f4d7f46a 100644
--- a/control_lib/sd_spi.v
+++ b/usrp2/control_lib/sd_spi.v
diff --git a/control_lib/sd_spi_tb.v b/usrp2/control_lib/sd_spi_tb.v
index e30a5bdf6..e30a5bdf6 100644
--- a/control_lib/sd_spi_tb.v
+++ b/usrp2/control_lib/sd_spi_tb.v
diff --git a/control_lib/sd_spi_wb.v b/usrp2/control_lib/sd_spi_wb.v
index 7a6258b56..7a6258b56 100644
--- a/control_lib/sd_spi_wb.v
+++ b/usrp2/control_lib/sd_spi_wb.v
diff --git a/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v
index c8aff230f..c8aff230f 100644
--- a/control_lib/setting_reg.v
+++ b/usrp2/control_lib/setting_reg.v
diff --git a/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v
index d01a30ab4..d01a30ab4 100644
--- a/control_lib/settings_bus.v
+++ b/usrp2/control_lib/settings_bus.v
diff --git a/control_lib/shortfifo.v b/usrp2/control_lib/shortfifo.v
index d8ce1428e..d8ce1428e 100644
--- a/control_lib/shortfifo.v
+++ b/usrp2/control_lib/shortfifo.v
diff --git a/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v
index 22f0e70a2..22f0e70a2 100644
--- a/control_lib/simple_uart.v
+++ b/usrp2/control_lib/simple_uart.v
diff --git a/control_lib/simple_uart_rx.v b/usrp2/control_lib/simple_uart_rx.v
index debdd618b..debdd618b 100644
--- a/control_lib/simple_uart_rx.v
+++ b/usrp2/control_lib/simple_uart_rx.v
diff --git a/control_lib/simple_uart_tx.v b/usrp2/control_lib/simple_uart_tx.v
index e11a347ed..e11a347ed 100644
--- a/control_lib/simple_uart_tx.v
+++ b/usrp2/control_lib/simple_uart_tx.v
diff --git a/control_lib/spi.v b/usrp2/control_lib/spi.v
index a80c488e9..a80c488e9 100644
--- a/control_lib/spi.v
+++ b/usrp2/control_lib/spi.v
diff --git a/control_lib/srl.v b/usrp2/control_lib/srl.v
index fa28c7669..fa28c7669 100644
--- a/control_lib/srl.v
+++ b/usrp2/control_lib/srl.v
diff --git a/control_lib/ss_rcvr.v b/usrp2/control_lib/ss_rcvr.v
index 8e650d21b..8e650d21b 100644
--- a/control_lib/ss_rcvr.v
+++ b/usrp2/control_lib/ss_rcvr.v
diff --git a/control_lib/system_control.v b/usrp2/control_lib/system_control.v
index 5d89f13db..5d89f13db 100644
--- a/control_lib/system_control.v
+++ b/usrp2/control_lib/system_control.v
diff --git a/control_lib/system_control_tb.v b/usrp2/control_lib/system_control_tb.v
index a8eff4811..a8eff4811 100644
--- a/control_lib/system_control_tb.v
+++ b/usrp2/control_lib/system_control_tb.v
diff --git a/control_lib/traffic_cop.v b/usrp2/control_lib/traffic_cop.v
index e7579656a..e7579656a 100644
--- a/control_lib/traffic_cop.v
+++ b/usrp2/control_lib/traffic_cop.v
diff --git a/control_lib/wb_1master.v b/usrp2/control_lib/wb_1master.v
index fb313efae..fb313efae 100644
--- a/control_lib/wb_1master.v
+++ b/usrp2/control_lib/wb_1master.v
diff --git a/control_lib/wb_bridge_16_32.v b/usrp2/control_lib/wb_bridge_16_32.v
index 405e25c3c..405e25c3c 100644
--- a/control_lib/wb_bridge_16_32.v
+++ b/usrp2/control_lib/wb_bridge_16_32.v
diff --git a/control_lib/wb_bus_writer.v b/usrp2/control_lib/wb_bus_writer.v
index fc148a0ff..fc148a0ff 100644
--- a/control_lib/wb_bus_writer.v
+++ b/usrp2/control_lib/wb_bus_writer.v
diff --git a/control_lib/wb_output_pins32.v b/usrp2/control_lib/wb_output_pins32.v
index 1517f2066..1517f2066 100644
--- a/control_lib/wb_output_pins32.v
+++ b/usrp2/control_lib/wb_output_pins32.v
diff --git a/control_lib/wb_ram_block.v b/usrp2/control_lib/wb_ram_block.v
index 044d34ca4..044d34ca4 100644
--- a/control_lib/wb_ram_block.v
+++ b/usrp2/control_lib/wb_ram_block.v
diff --git a/control_lib/wb_ram_dist.v b/usrp2/control_lib/wb_ram_dist.v
index cffc2f423..cffc2f423 100644
--- a/control_lib/wb_ram_dist.v
+++ b/usrp2/control_lib/wb_ram_dist.v
diff --git a/control_lib/wb_readback_mux.v b/usrp2/control_lib/wb_readback_mux.v
index 3922b03e3..3922b03e3 100644
--- a/control_lib/wb_readback_mux.v
+++ b/usrp2/control_lib/wb_readback_mux.v
diff --git a/control_lib/wb_regfile_2clock.v b/usrp2/control_lib/wb_regfile_2clock.v
index e248e5161..e248e5161 100644
--- a/control_lib/wb_regfile_2clock.v
+++ b/usrp2/control_lib/wb_regfile_2clock.v
diff --git a/control_lib/wb_semaphore.v b/usrp2/control_lib/wb_semaphore.v
index a9208e6a1..a9208e6a1 100644
--- a/control_lib/wb_semaphore.v
+++ b/usrp2/control_lib/wb_semaphore.v
diff --git a/control_lib/wb_sim.v b/usrp2/control_lib/wb_sim.v
index b324e1457..b324e1457 100644
--- a/control_lib/wb_sim.v
+++ b/usrp2/control_lib/wb_sim.v
diff --git a/coregen/.gitignore b/usrp2/coregen/.gitignore
index 956cab52b..956cab52b 100644
--- a/coregen/.gitignore
+++ b/usrp2/coregen/.gitignore
diff --git a/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp
index 810d64dac..810d64dac 100644
--- a/coregen/coregen.cgp
+++ b/usrp2/coregen/coregen.cgp
diff --git a/coregen/fifo_generator_release_notes.txt b/usrp2/coregen/fifo_generator_release_notes.txt
index 554ec87f4..554ec87f4 100644
--- a/coregen/fifo_generator_release_notes.txt
+++ b/usrp2/coregen/fifo_generator_release_notes.txt
diff --git a/coregen/fifo_generator_ug175.pdf b/usrp2/coregen/fifo_generator_ug175.pdf
index 2c3e3c200..2c3e3c200 100644
--- a/coregen/fifo_generator_ug175.pdf
+++ b/usrp2/coregen/fifo_generator_ug175.pdf
diff --git a/coregen/fifo_xlnx_16x19_2clk.ngc b/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc
index b12d34d7c..b12d34d7c 100644
--- a/coregen/fifo_xlnx_16x19_2clk.ngc
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc
diff --git a/coregen/fifo_xlnx_16x19_2clk.v b/usrp2/coregen/fifo_xlnx_16x19_2clk.v
index 1d633384b..1d633384b 100644
--- a/coregen/fifo_xlnx_16x19_2clk.v
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.v
diff --git a/coregen/fifo_xlnx_16x19_2clk.veo b/usrp2/coregen/fifo_xlnx_16x19_2clk.veo
index 2e9af1efa..2e9af1efa 100644
--- a/coregen/fifo_xlnx_16x19_2clk.veo
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.veo
diff --git a/coregen/fifo_xlnx_16x19_2clk.xco b/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
index d0f638026..d0f638026 100644
--- a/coregen/fifo_xlnx_16x19_2clk.xco
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
index f1a6f7899..f1a6f7899 100644
--- a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
diff --git a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
index ef33fff67..ef33fff67 100644
--- a/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
diff --git a/coregen/fifo_xlnx_16x19_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt
index 5e1a6ed35..5e1a6ed35 100644
--- a/coregen/fifo_xlnx_16x19_2clk_flist.txt
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt
diff --git a/coregen/fifo_xlnx_16x19_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt
index 1b5976555..1b5976555 100644
--- a/coregen/fifo_xlnx_16x19_2clk_readme.txt
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt
diff --git a/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
index 8d633e9c2..8d633e9c2 100644
--- a/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
+++ b/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.asy b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy
index a87aa2f84..a87aa2f84 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.asy
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.ngc b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc
index 684eb74f4..684eb74f4 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.ngc
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.sym b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym
index 5d56b5c98..5d56b5c98 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.sym
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.v b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
index 0762b3ae9..0762b3ae9 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.v
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.veo b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo
index af9191555..af9191555 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.veo
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.vhd b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd
index 53033dc97..53033dc97 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.vhd
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.vho b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho
index 5165b0bc4..5165b0bc4 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.vho
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.xco b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
index e25ad38da..e25ad38da 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk.xco
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
diff --git a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
index f1a6f7899..f1a6f7899 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
diff --git a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
index 5108be2c5..5108be2c5 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
diff --git a/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
index 670d84713..670d84713 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
diff --git a/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
index 1879503a9..1879503a9 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
diff --git a/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
index cac25efd2..cac25efd2 100644
--- a/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
+++ b/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
diff --git a/coregen/fifo_xlnx_512x36_2clk.asy b/usrp2/coregen/fifo_xlnx_512x36_2clk.asy
index ecc80b648..ecc80b648 100644
--- a/coregen/fifo_xlnx_512x36_2clk.asy
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.asy
diff --git a/coregen/fifo_xlnx_512x36_2clk.ngc b/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc
index 55486485a..55486485a 100644
--- a/coregen/fifo_xlnx_512x36_2clk.ngc
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc
diff --git a/coregen/fifo_xlnx_512x36_2clk.sym b/usrp2/coregen/fifo_xlnx_512x36_2clk.sym
index 13e8af33d..13e8af33d 100644
--- a/coregen/fifo_xlnx_512x36_2clk.sym
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.sym
diff --git a/coregen/fifo_xlnx_512x36_2clk.v b/usrp2/coregen/fifo_xlnx_512x36_2clk.v
index 905069743..905069743 100644
--- a/coregen/fifo_xlnx_512x36_2clk.v
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.v
diff --git a/coregen/fifo_xlnx_512x36_2clk.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk.veo
index 6699ee73b..6699ee73b 100644
--- a/coregen/fifo_xlnx_512x36_2clk.veo
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.veo
diff --git a/coregen/fifo_xlnx_512x36_2clk.vhd b/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd
index d9c2dd307..d9c2dd307 100644
--- a/coregen/fifo_xlnx_512x36_2clk.vhd
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd
diff --git a/coregen/fifo_xlnx_512x36_2clk.vho b/usrp2/coregen/fifo_xlnx_512x36_2clk.vho
index 70eac27a5..70eac27a5 100644
--- a/coregen/fifo_xlnx_512x36_2clk.vho
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.vho
diff --git a/coregen/fifo_xlnx_512x36_2clk.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
index 5934ef285..5934ef285 100644
--- a/coregen/fifo_xlnx_512x36_2clk.xco
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
diff --git a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
index f1a6f7899..f1a6f7899 100644
--- a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
diff --git a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
index d110a0158..d110a0158 100644
--- a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
diff --git a/coregen/fifo_xlnx_512x36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt
index b0975be2d..b0975be2d 100644
--- a/coregen/fifo_xlnx_512x36_2clk_flist.txt
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt
diff --git a/coregen/fifo_xlnx_512x36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt
index a250a74f5..a250a74f5 100644
--- a/coregen/fifo_xlnx_512x36_2clk_readme.txt
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt
diff --git a/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
index 8a0c0e3ff..8a0c0e3ff 100644
--- a/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
diff --git a/coregen/fifo_xlnx_64x36_2clk.ngc b/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc
index e8c55a1af..e8c55a1af 100644
--- a/coregen/fifo_xlnx_64x36_2clk.ngc
+++ b/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc
diff --git a/coregen/fifo_xlnx_64x36_2clk.v b/usrp2/coregen/fifo_xlnx_64x36_2clk.v
index e84237689..e84237689 100644
--- a/coregen/fifo_xlnx_64x36_2clk.v
+++ b/usrp2/coregen/fifo_xlnx_64x36_2clk.v
diff --git a/coregen/fifo_xlnx_64x36_2clk.veo b/usrp2/coregen/fifo_xlnx_64x36_2clk.veo
index 9c761370c..9c761370c 100644
--- a/coregen/fifo_xlnx_64x36_2clk.veo
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diff --git a/coregen/fifo_xlnx_64x36_2clk.xco b/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
index c6e9aae27..c6e9aae27 100644
--- a/coregen/fifo_xlnx_64x36_2clk.xco
+++ b/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
diff --git a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
index f1a6f7899..f1a6f7899 100644
--- a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
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diff --git a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
index a23402f56..a23402f56 100644
--- a/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ b/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
diff --git a/coregen/fifo_xlnx_64x36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt
index 44e31eb6c..44e31eb6c 100644
--- a/coregen/fifo_xlnx_64x36_2clk_flist.txt
+++ b/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt
diff --git a/coregen/fifo_xlnx_64x36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt
index 7734c0087..7734c0087 100644
--- a/coregen/fifo_xlnx_64x36_2clk_readme.txt
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diff --git a/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
index ff5dfd3c2..ff5dfd3c2 100644
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+++ b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Entries
diff --git a/opencores/i2c/sim/i2c_verilog/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository
index b97ee33c8..b97ee33c8 100644
--- a/opencores/i2c/sim/i2c_verilog/CVS/Repository
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository
diff --git a/opencores/i2c/sim/i2c_verilog/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/sim/i2c_verilog/CVS/Root
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root
diff --git a/opencores/i2c/sim/i2c_verilog/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/sim/i2c_verilog/CVS/Template
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Template
diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Entries b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
index ddea0baae..ddea0baae 100644
--- a/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository
index bdd990e7c..bdd990e7c 100644
--- a/opencores/i2c/sim/i2c_verilog/run/CVS/Repository
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository
diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/sim/i2c_verilog/run/CVS/Root
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root
diff --git a/opencores/i2c/sim/i2c_verilog/run/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/sim/i2c_verilog/run/CVS/Template
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Template
diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
index 178481050..178481050 100644
--- a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
index 6b760e397..6b760e397 100644
--- a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
diff --git a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template
diff --git a/opencores/i2c/sim/i2c_verilog/run/bench.vcd b/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd
index 9a364415f..9a364415f 100644
--- a/opencores/i2c/sim/i2c_verilog/run/bench.vcd
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd
diff --git a/opencores/i2c/sim/i2c_verilog/run/ncverilog.key b/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key
index a3abe5090..a3abe5090 100644
--- a/opencores/i2c/sim/i2c_verilog/run/ncverilog.key
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key
diff --git a/opencores/i2c/sim/i2c_verilog/run/run b/usrp2/opencores/i2c/sim/i2c_verilog/run/run
index 41bcaab30..41bcaab30 100755
--- a/opencores/i2c/sim/i2c_verilog/run/run
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/run
diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries
index 178481050..178481050 100644
--- a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries
diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository
index 94d106eb0..94d106eb0 100644
--- a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository
diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root
diff --git a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template
+++ b/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template
diff --git a/opencores/i2c/software/CVS/Entries b/usrp2/opencores/i2c/software/CVS/Entries
index 934613477..934613477 100644
--- a/opencores/i2c/software/CVS/Entries
+++ b/usrp2/opencores/i2c/software/CVS/Entries
diff --git a/opencores/i2c/software/CVS/Repository b/usrp2/opencores/i2c/software/CVS/Repository
index 1b4c9f0bb..1b4c9f0bb 100644
--- a/opencores/i2c/software/CVS/Repository
+++ b/usrp2/opencores/i2c/software/CVS/Repository
diff --git a/opencores/i2c/software/CVS/Root b/usrp2/opencores/i2c/software/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/software/CVS/Root
+++ b/usrp2/opencores/i2c/software/CVS/Root
diff --git a/opencores/i2c/software/CVS/Template b/usrp2/opencores/i2c/software/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/software/CVS/Template
+++ b/usrp2/opencores/i2c/software/CVS/Template
diff --git a/opencores/i2c/software/drivers/CVS/Entries b/usrp2/opencores/i2c/software/drivers/CVS/Entries
index 178481050..178481050 100644
--- a/opencores/i2c/software/drivers/CVS/Entries
+++ b/usrp2/opencores/i2c/software/drivers/CVS/Entries
diff --git a/opencores/i2c/software/drivers/CVS/Repository b/usrp2/opencores/i2c/software/drivers/CVS/Repository
index 260d7873c..260d7873c 100644
--- a/opencores/i2c/software/drivers/CVS/Repository
+++ b/usrp2/opencores/i2c/software/drivers/CVS/Repository
diff --git a/opencores/i2c/software/drivers/CVS/Root b/usrp2/opencores/i2c/software/drivers/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/software/drivers/CVS/Root
+++ b/usrp2/opencores/i2c/software/drivers/CVS/Root
diff --git a/opencores/i2c/software/drivers/CVS/Template b/usrp2/opencores/i2c/software/drivers/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/software/drivers/CVS/Template
+++ b/usrp2/opencores/i2c/software/drivers/CVS/Template
diff --git a/opencores/i2c/software/include/CVS/Entries b/usrp2/opencores/i2c/software/include/CVS/Entries
index ef11b0c73..ef11b0c73 100644
--- a/opencores/i2c/software/include/CVS/Entries
+++ b/usrp2/opencores/i2c/software/include/CVS/Entries
diff --git a/opencores/i2c/software/include/CVS/Repository b/usrp2/opencores/i2c/software/include/CVS/Repository
index 2ea08eeec..2ea08eeec 100644
--- a/opencores/i2c/software/include/CVS/Repository
+++ b/usrp2/opencores/i2c/software/include/CVS/Repository
diff --git a/opencores/i2c/software/include/CVS/Root b/usrp2/opencores/i2c/software/include/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/software/include/CVS/Root
+++ b/usrp2/opencores/i2c/software/include/CVS/Root
diff --git a/opencores/i2c/software/include/CVS/Template b/usrp2/opencores/i2c/software/include/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/software/include/CVS/Template
+++ b/usrp2/opencores/i2c/software/include/CVS/Template
diff --git a/opencores/i2c/software/include/oc_i2c_master.h b/usrp2/opencores/i2c/software/include/oc_i2c_master.h
index 7f7cfc417..7f7cfc417 100644
--- a/opencores/i2c/software/include/oc_i2c_master.h
+++ b/usrp2/opencores/i2c/software/include/oc_i2c_master.h
diff --git a/opencores/i2c/verilog/CVS/Entries b/usrp2/opencores/i2c/verilog/CVS/Entries
index 178481050..178481050 100644
--- a/opencores/i2c/verilog/CVS/Entries
+++ b/usrp2/opencores/i2c/verilog/CVS/Entries
diff --git a/opencores/i2c/verilog/CVS/Repository b/usrp2/opencores/i2c/verilog/CVS/Repository
index acc23265f..acc23265f 100644
--- a/opencores/i2c/verilog/CVS/Repository
+++ b/usrp2/opencores/i2c/verilog/CVS/Repository
diff --git a/opencores/i2c/verilog/CVS/Root b/usrp2/opencores/i2c/verilog/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/verilog/CVS/Root
+++ b/usrp2/opencores/i2c/verilog/CVS/Root
diff --git a/opencores/i2c/verilog/CVS/Template b/usrp2/opencores/i2c/verilog/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/verilog/CVS/Template
+++ b/usrp2/opencores/i2c/verilog/CVS/Template
diff --git a/opencores/i2c/vhdl/CVS/Entries b/usrp2/opencores/i2c/vhdl/CVS/Entries
index 178481050..178481050 100644
--- a/opencores/i2c/vhdl/CVS/Entries
+++ b/usrp2/opencores/i2c/vhdl/CVS/Entries
diff --git a/opencores/i2c/vhdl/CVS/Repository b/usrp2/opencores/i2c/vhdl/CVS/Repository
index 8ee00a788..8ee00a788 100644
--- a/opencores/i2c/vhdl/CVS/Repository
+++ b/usrp2/opencores/i2c/vhdl/CVS/Repository
diff --git a/opencores/i2c/vhdl/CVS/Root b/usrp2/opencores/i2c/vhdl/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/i2c/vhdl/CVS/Root
+++ b/usrp2/opencores/i2c/vhdl/CVS/Root
diff --git a/opencores/i2c/vhdl/CVS/Template b/usrp2/opencores/i2c/vhdl/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/i2c/vhdl/CVS/Template
+++ b/usrp2/opencores/i2c/vhdl/CVS/Template
diff --git a/opencores/simple_gpio/CVS/Entries b/usrp2/opencores/simple_gpio/CVS/Entries
index df1462bb9..df1462bb9 100644
--- a/opencores/simple_gpio/CVS/Entries
+++ b/usrp2/opencores/simple_gpio/CVS/Entries
diff --git a/opencores/simple_gpio/CVS/Repository b/usrp2/opencores/simple_gpio/CVS/Repository
index b869a0de8..b869a0de8 100644
--- a/opencores/simple_gpio/CVS/Repository
+++ b/usrp2/opencores/simple_gpio/CVS/Repository
diff --git a/opencores/simple_gpio/CVS/Root b/usrp2/opencores/simple_gpio/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/simple_gpio/CVS/Root
+++ b/usrp2/opencores/simple_gpio/CVS/Root
diff --git a/opencores/simple_gpio/CVS/Template b/usrp2/opencores/simple_gpio/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/simple_gpio/CVS/Template
+++ b/usrp2/opencores/simple_gpio/CVS/Template
diff --git a/opencores/simple_gpio/rtl/CVS/Entries b/usrp2/opencores/simple_gpio/rtl/CVS/Entries
index 8c6258130..8c6258130 100644
--- a/opencores/simple_gpio/rtl/CVS/Entries
+++ b/usrp2/opencores/simple_gpio/rtl/CVS/Entries
diff --git a/opencores/simple_gpio/rtl/CVS/Repository b/usrp2/opencores/simple_gpio/rtl/CVS/Repository
index 955303d8a..955303d8a 100644
--- a/opencores/simple_gpio/rtl/CVS/Repository
+++ b/usrp2/opencores/simple_gpio/rtl/CVS/Repository
diff --git a/opencores/simple_gpio/rtl/CVS/Root b/usrp2/opencores/simple_gpio/rtl/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/simple_gpio/rtl/CVS/Root
+++ b/usrp2/opencores/simple_gpio/rtl/CVS/Root
diff --git a/opencores/simple_gpio/rtl/CVS/Template b/usrp2/opencores/simple_gpio/rtl/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/simple_gpio/rtl/CVS/Template
+++ b/usrp2/opencores/simple_gpio/rtl/CVS/Template
diff --git a/opencores/simple_gpio/rtl/simple_gpio.v b/usrp2/opencores/simple_gpio/rtl/simple_gpio.v
index 0b78f9921..0b78f9921 100644
--- a/opencores/simple_gpio/rtl/simple_gpio.v
+++ b/usrp2/opencores/simple_gpio/rtl/simple_gpio.v
diff --git a/opencores/simple_pic/CVS/Entries b/usrp2/opencores/simple_pic/CVS/Entries
index df1462bb9..df1462bb9 100644
--- a/opencores/simple_pic/CVS/Entries
+++ b/usrp2/opencores/simple_pic/CVS/Entries
diff --git a/opencores/simple_pic/CVS/Repository b/usrp2/opencores/simple_pic/CVS/Repository
index 73de5bf2b..73de5bf2b 100644
--- a/opencores/simple_pic/CVS/Repository
+++ b/usrp2/opencores/simple_pic/CVS/Repository
diff --git a/opencores/simple_pic/CVS/Root b/usrp2/opencores/simple_pic/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/simple_pic/CVS/Root
+++ b/usrp2/opencores/simple_pic/CVS/Root
diff --git a/opencores/simple_pic/CVS/Template b/usrp2/opencores/simple_pic/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/simple_pic/CVS/Template
+++ b/usrp2/opencores/simple_pic/CVS/Template
diff --git a/opencores/simple_pic/rtl/CVS/Entries b/usrp2/opencores/simple_pic/rtl/CVS/Entries
index e5e641097..e5e641097 100644
--- a/opencores/simple_pic/rtl/CVS/Entries
+++ b/usrp2/opencores/simple_pic/rtl/CVS/Entries
diff --git a/opencores/simple_pic/rtl/CVS/Repository b/usrp2/opencores/simple_pic/rtl/CVS/Repository
index 2639a29e2..2639a29e2 100644
--- a/opencores/simple_pic/rtl/CVS/Repository
+++ b/usrp2/opencores/simple_pic/rtl/CVS/Repository
diff --git a/opencores/simple_pic/rtl/CVS/Root b/usrp2/opencores/simple_pic/rtl/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/simple_pic/rtl/CVS/Root
+++ b/usrp2/opencores/simple_pic/rtl/CVS/Root
diff --git a/opencores/simple_pic/rtl/CVS/Template b/usrp2/opencores/simple_pic/rtl/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/simple_pic/rtl/CVS/Template
+++ b/usrp2/opencores/simple_pic/rtl/CVS/Template
diff --git a/opencores/simple_pic/rtl/simple_pic.v b/usrp2/opencores/simple_pic/rtl/simple_pic.v
index 28184cbe2..28184cbe2 100644
--- a/opencores/simple_pic/rtl/simple_pic.v
+++ b/usrp2/opencores/simple_pic/rtl/simple_pic.v
diff --git a/opencores/spi/CVS/Entries b/usrp2/opencores/spi/CVS/Entries
index 62011c465..62011c465 100644
--- a/opencores/spi/CVS/Entries
+++ b/usrp2/opencores/spi/CVS/Entries
diff --git a/opencores/spi/CVS/Repository b/usrp2/opencores/spi/CVS/Repository
index c928c4b77..c928c4b77 100644
--- a/opencores/spi/CVS/Repository
+++ b/usrp2/opencores/spi/CVS/Repository
diff --git a/opencores/spi/CVS/Root b/usrp2/opencores/spi/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/CVS/Root
+++ b/usrp2/opencores/spi/CVS/Root
diff --git a/opencores/spi/CVS/Template b/usrp2/opencores/spi/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/CVS/Template
+++ b/usrp2/opencores/spi/CVS/Template
diff --git a/opencores/spi/bench/CVS/Entries b/usrp2/opencores/spi/bench/CVS/Entries
index 428c5622d..428c5622d 100644
--- a/opencores/spi/bench/CVS/Entries
+++ b/usrp2/opencores/spi/bench/CVS/Entries
diff --git a/opencores/spi/bench/CVS/Repository b/usrp2/opencores/spi/bench/CVS/Repository
index f45728d0f..f45728d0f 100644
--- a/opencores/spi/bench/CVS/Repository
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diff --git a/opencores/spi/bench/CVS/Root b/usrp2/opencores/spi/bench/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/bench/CVS/Root
+++ b/usrp2/opencores/spi/bench/CVS/Root
diff --git a/opencores/spi/bench/CVS/Template b/usrp2/opencores/spi/bench/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/bench/CVS/Template
+++ b/usrp2/opencores/spi/bench/CVS/Template
diff --git a/opencores/spi/bench/verilog/CVS/Entries b/usrp2/opencores/spi/bench/verilog/CVS/Entries
index 68404f871..68404f871 100644
--- a/opencores/spi/bench/verilog/CVS/Entries
+++ b/usrp2/opencores/spi/bench/verilog/CVS/Entries
diff --git a/opencores/spi/bench/verilog/CVS/Repository b/usrp2/opencores/spi/bench/verilog/CVS/Repository
index 78a3c4a9f..78a3c4a9f 100644
--- a/opencores/spi/bench/verilog/CVS/Repository
+++ b/usrp2/opencores/spi/bench/verilog/CVS/Repository
diff --git a/opencores/spi/bench/verilog/CVS/Root b/usrp2/opencores/spi/bench/verilog/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/bench/verilog/CVS/Root
+++ b/usrp2/opencores/spi/bench/verilog/CVS/Root
diff --git a/opencores/spi/bench/verilog/CVS/Template b/usrp2/opencores/spi/bench/verilog/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/bench/verilog/CVS/Template
+++ b/usrp2/opencores/spi/bench/verilog/CVS/Template
diff --git a/opencores/spi/bench/verilog/spi_slave_model.v b/usrp2/opencores/spi/bench/verilog/spi_slave_model.v
index dfdaed929..dfdaed929 100644
--- a/opencores/spi/bench/verilog/spi_slave_model.v
+++ b/usrp2/opencores/spi/bench/verilog/spi_slave_model.v
diff --git a/opencores/spi/bench/verilog/tb_spi_top.v b/usrp2/opencores/spi/bench/verilog/tb_spi_top.v
index 529c0aca1..529c0aca1 100644
--- a/opencores/spi/bench/verilog/tb_spi_top.v
+++ b/usrp2/opencores/spi/bench/verilog/tb_spi_top.v
diff --git a/opencores/spi/bench/verilog/wb_master_model.v b/usrp2/opencores/spi/bench/verilog/wb_master_model.v
index 3f8b7ee6a..3f8b7ee6a 100644
--- a/opencores/spi/bench/verilog/wb_master_model.v
+++ b/usrp2/opencores/spi/bench/verilog/wb_master_model.v
diff --git a/opencores/spi/doc/CVS/Entries b/usrp2/opencores/spi/doc/CVS/Entries
index ff33fa590..ff33fa590 100644
--- a/opencores/spi/doc/CVS/Entries
+++ b/usrp2/opencores/spi/doc/CVS/Entries
diff --git a/opencores/spi/doc/CVS/Repository b/usrp2/opencores/spi/doc/CVS/Repository
index 772adcef5..772adcef5 100644
--- a/opencores/spi/doc/CVS/Repository
+++ b/usrp2/opencores/spi/doc/CVS/Repository
diff --git a/opencores/spi/doc/CVS/Root b/usrp2/opencores/spi/doc/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/doc/CVS/Root
+++ b/usrp2/opencores/spi/doc/CVS/Root
diff --git a/opencores/spi/doc/CVS/Template b/usrp2/opencores/spi/doc/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/doc/CVS/Template
+++ b/usrp2/opencores/spi/doc/CVS/Template
diff --git a/opencores/spi/doc/spi.pdf b/usrp2/opencores/spi/doc/spi.pdf
index d88ee2807..d88ee2807 100644
--- a/opencores/spi/doc/spi.pdf
+++ b/usrp2/opencores/spi/doc/spi.pdf
diff --git a/opencores/spi/doc/src/CVS/Entries b/usrp2/opencores/spi/doc/src/CVS/Entries
index adcbf083d..adcbf083d 100644
--- a/opencores/spi/doc/src/CVS/Entries
+++ b/usrp2/opencores/spi/doc/src/CVS/Entries
diff --git a/opencores/spi/doc/src/CVS/Repository b/usrp2/opencores/spi/doc/src/CVS/Repository
index 09b1f4a98..09b1f4a98 100644
--- a/opencores/spi/doc/src/CVS/Repository
+++ b/usrp2/opencores/spi/doc/src/CVS/Repository
diff --git a/opencores/spi/doc/src/CVS/Root b/usrp2/opencores/spi/doc/src/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/doc/src/CVS/Root
+++ b/usrp2/opencores/spi/doc/src/CVS/Root
diff --git a/opencores/spi/doc/src/CVS/Template b/usrp2/opencores/spi/doc/src/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/doc/src/CVS/Template
+++ b/usrp2/opencores/spi/doc/src/CVS/Template
diff --git a/opencores/spi/doc/src/spi.doc b/usrp2/opencores/spi/doc/src/spi.doc
index b04700177..b04700177 100755
--- a/opencores/spi/doc/src/spi.doc
+++ b/usrp2/opencores/spi/doc/src/spi.doc
diff --git a/opencores/spi/rtl/CVS/Entries b/usrp2/opencores/spi/rtl/CVS/Entries
index 428c5622d..428c5622d 100644
--- a/opencores/spi/rtl/CVS/Entries
+++ b/usrp2/opencores/spi/rtl/CVS/Entries
diff --git a/opencores/spi/rtl/CVS/Repository b/usrp2/opencores/spi/rtl/CVS/Repository
index 5fd79b19b..5fd79b19b 100644
--- a/opencores/spi/rtl/CVS/Repository
+++ b/usrp2/opencores/spi/rtl/CVS/Repository
diff --git a/opencores/spi/rtl/CVS/Root b/usrp2/opencores/spi/rtl/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/rtl/CVS/Root
+++ b/usrp2/opencores/spi/rtl/CVS/Root
diff --git a/opencores/spi/rtl/CVS/Template b/usrp2/opencores/spi/rtl/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/rtl/CVS/Template
+++ b/usrp2/opencores/spi/rtl/CVS/Template
diff --git a/opencores/spi/rtl/verilog/CVS/Entries b/usrp2/opencores/spi/rtl/verilog/CVS/Entries
index d125a1657..d125a1657 100644
--- a/opencores/spi/rtl/verilog/CVS/Entries
+++ b/usrp2/opencores/spi/rtl/verilog/CVS/Entries
diff --git a/opencores/spi/rtl/verilog/CVS/Repository b/usrp2/opencores/spi/rtl/verilog/CVS/Repository
index 361b93bf8..361b93bf8 100644
--- a/opencores/spi/rtl/verilog/CVS/Repository
+++ b/usrp2/opencores/spi/rtl/verilog/CVS/Repository
diff --git a/opencores/spi/rtl/verilog/CVS/Root b/usrp2/opencores/spi/rtl/verilog/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/rtl/verilog/CVS/Root
+++ b/usrp2/opencores/spi/rtl/verilog/CVS/Root
diff --git a/opencores/spi/rtl/verilog/CVS/Template b/usrp2/opencores/spi/rtl/verilog/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/rtl/verilog/CVS/Template
+++ b/usrp2/opencores/spi/rtl/verilog/CVS/Template
diff --git a/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
index 7bc4f6e5e..7bc4f6e5e 100644
--- a/opencores/spi/rtl/verilog/spi_clgen.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
diff --git a/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index a6925918e..a6925918e 100644
--- a/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
diff --git a/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
index b17ac8b1f..b17ac8b1f 100644
--- a/opencores/spi/rtl/verilog/spi_shift.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
diff --git a/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v
index 09b2e50e1..09b2e50e1 100644
--- a/opencores/spi/rtl/verilog/spi_top.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v
diff --git a/opencores/spi/rtl/verilog/timescale.v b/usrp2/opencores/spi/rtl/verilog/timescale.v
index 60d4ecbd1..60d4ecbd1 100644
--- a/opencores/spi/rtl/verilog/timescale.v
+++ b/usrp2/opencores/spi/rtl/verilog/timescale.v
diff --git a/opencores/spi/sim/CVS/Entries b/usrp2/opencores/spi/sim/CVS/Entries
index 545533337..545533337 100644
--- a/opencores/spi/sim/CVS/Entries
+++ b/usrp2/opencores/spi/sim/CVS/Entries
diff --git a/opencores/spi/sim/CVS/Repository b/usrp2/opencores/spi/sim/CVS/Repository
index 9ec769309..9ec769309 100644
--- a/opencores/spi/sim/CVS/Repository
+++ b/usrp2/opencores/spi/sim/CVS/Repository
diff --git a/opencores/spi/sim/CVS/Root b/usrp2/opencores/spi/sim/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/sim/CVS/Root
+++ b/usrp2/opencores/spi/sim/CVS/Root
diff --git a/opencores/spi/sim/CVS/Template b/usrp2/opencores/spi/sim/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/sim/CVS/Template
+++ b/usrp2/opencores/spi/sim/CVS/Template
diff --git a/opencores/spi/sim/rtl_sim/CVS/Entries b/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries
index 8ab9f73a7..8ab9f73a7 100644
--- a/opencores/spi/sim/rtl_sim/CVS/Entries
+++ b/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries
diff --git a/opencores/spi/sim/rtl_sim/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository
index c8c6a94c6..c8c6a94c6 100644
--- a/opencores/spi/sim/rtl_sim/CVS/Repository
+++ b/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository
diff --git a/opencores/spi/sim/rtl_sim/CVS/Root b/usrp2/opencores/spi/sim/rtl_sim/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/sim/rtl_sim/CVS/Root
+++ b/usrp2/opencores/spi/sim/rtl_sim/CVS/Root
diff --git a/opencores/spi/sim/rtl_sim/CVS/Template b/usrp2/opencores/spi/sim/rtl_sim/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/sim/rtl_sim/CVS/Template
+++ b/usrp2/opencores/spi/sim/rtl_sim/CVS/Template
diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Entries b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries
index 8947f64a0..8947f64a0 100644
--- a/opencores/spi/sim/rtl_sim/run/CVS/Entries
+++ b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries
diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Repository b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository
index 5200bb196..5200bb196 100644
--- a/opencores/spi/sim/rtl_sim/run/CVS/Repository
+++ b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository
diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Root b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/sim/rtl_sim/run/CVS/Root
+++ b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root
diff --git a/opencores/spi/sim/rtl_sim/run/CVS/Template b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/sim/rtl_sim/run/CVS/Template
+++ b/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template
diff --git a/opencores/spi/sim/rtl_sim/run/rtl.fl b/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl
index d84a0840d..d84a0840d 100644
--- a/opencores/spi/sim/rtl_sim/run/rtl.fl
+++ b/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl
diff --git a/opencores/spi/sim/rtl_sim/run/run_sim b/usrp2/opencores/spi/sim/rtl_sim/run/run_sim
index 1b13a35b9..1b13a35b9 100755
--- a/opencores/spi/sim/rtl_sim/run/run_sim
+++ b/usrp2/opencores/spi/sim/rtl_sim/run/run_sim
diff --git a/opencores/spi/sim/rtl_sim/run/sim.fl b/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl
index 283aad1f8..283aad1f8 100644
--- a/opencores/spi/sim/rtl_sim/run/sim.fl
+++ b/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl
diff --git a/opencores/spi/sim/run/CVS/Entries b/usrp2/opencores/spi/sim/run/CVS/Entries
index 178481050..178481050 100644
--- a/opencores/spi/sim/run/CVS/Entries
+++ b/usrp2/opencores/spi/sim/run/CVS/Entries
diff --git a/opencores/spi/sim/run/CVS/Repository b/usrp2/opencores/spi/sim/run/CVS/Repository
index e8646e70d..e8646e70d 100644
--- a/opencores/spi/sim/run/CVS/Repository
+++ b/usrp2/opencores/spi/sim/run/CVS/Repository
diff --git a/opencores/spi/sim/run/CVS/Root b/usrp2/opencores/spi/sim/run/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi/sim/run/CVS/Root
+++ b/usrp2/opencores/spi/sim/run/CVS/Root
diff --git a/opencores/spi/sim/run/CVS/Template b/usrp2/opencores/spi/sim/run/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi/sim/run/CVS/Template
+++ b/usrp2/opencores/spi/sim/run/CVS/Template
diff --git a/opencores/spi_boot/COMPILE_LIST b/usrp2/opencores/spi_boot/COMPILE_LIST
index fc8f7d418..fc8f7d418 100644
--- a/opencores/spi_boot/COMPILE_LIST
+++ b/usrp2/opencores/spi_boot/COMPILE_LIST
diff --git a/opencores/spi_boot/COPYING b/usrp2/opencores/spi_boot/COPYING
index 60549be51..60549be51 100644
--- a/opencores/spi_boot/COPYING
+++ b/usrp2/opencores/spi_boot/COPYING
diff --git a/opencores/spi_boot/CVS/Entries b/usrp2/opencores/spi_boot/CVS/Entries
index d339433f3..d339433f3 100644
--- a/opencores/spi_boot/CVS/Entries
+++ b/usrp2/opencores/spi_boot/CVS/Entries
diff --git a/opencores/spi_boot/CVS/Repository b/usrp2/opencores/spi_boot/CVS/Repository
index 6aa579d49..6aa579d49 100644
--- a/opencores/spi_boot/CVS/Repository
+++ b/usrp2/opencores/spi_boot/CVS/Repository
diff --git a/opencores/spi_boot/CVS/Root b/usrp2/opencores/spi_boot/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/CVS/Root
+++ b/usrp2/opencores/spi_boot/CVS/Root
diff --git a/opencores/spi_boot/CVS/Template b/usrp2/opencores/spi_boot/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/CVS/Template
+++ b/usrp2/opencores/spi_boot/CVS/Template
diff --git a/opencores/spi_boot/KNOWN_BUGS b/usrp2/opencores/spi_boot/KNOWN_BUGS
index 298e4ba2e..298e4ba2e 100644
--- a/opencores/spi_boot/KNOWN_BUGS
+++ b/usrp2/opencores/spi_boot/KNOWN_BUGS
diff --git a/opencores/spi_boot/README b/usrp2/opencores/spi_boot/README
index 926b35bff..926b35bff 100644
--- a/opencores/spi_boot/README
+++ b/usrp2/opencores/spi_boot/README
diff --git a/opencores/spi_boot/bench/CVS/Entries b/usrp2/opencores/spi_boot/bench/CVS/Entries
index a4756ee6f..a4756ee6f 100644
--- a/opencores/spi_boot/bench/CVS/Entries
+++ b/usrp2/opencores/spi_boot/bench/CVS/Entries
diff --git a/opencores/spi_boot/bench/CVS/Repository b/usrp2/opencores/spi_boot/bench/CVS/Repository
index ac45542a6..ac45542a6 100644
--- a/opencores/spi_boot/bench/CVS/Repository
+++ b/usrp2/opencores/spi_boot/bench/CVS/Repository
diff --git a/opencores/spi_boot/bench/CVS/Root b/usrp2/opencores/spi_boot/bench/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/bench/CVS/Root
+++ b/usrp2/opencores/spi_boot/bench/CVS/Root
diff --git a/opencores/spi_boot/bench/CVS/Template b/usrp2/opencores/spi_boot/bench/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/bench/CVS/Template
+++ b/usrp2/opencores/spi_boot/bench/CVS/Template
diff --git a/opencores/spi_boot/bench/vhdl/CVS/Entries b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries
index 8649c9f90..8649c9f90 100644
--- a/opencores/spi_boot/bench/vhdl/CVS/Entries
+++ b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries
diff --git a/opencores/spi_boot/bench/vhdl/CVS/Repository b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository
index ce62c2b8e..ce62c2b8e 100644
--- a/opencores/spi_boot/bench/vhdl/CVS/Repository
+++ b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository
diff --git a/opencores/spi_boot/bench/vhdl/CVS/Root b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/bench/vhdl/CVS/Root
+++ b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root
diff --git a/opencores/spi_boot/bench/vhdl/CVS/Template b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/bench/vhdl/CVS/Template
+++ b/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template
diff --git a/opencores/spi_boot/bench/vhdl/card-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd
index 797eb1c90..797eb1c90 100644
--- a/opencores/spi_boot/bench/vhdl/card-c.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd
diff --git a/opencores/spi_boot/bench/vhdl/card.vhd b/usrp2/opencores/spi_boot/bench/vhdl/card.vhd
index dcd676095..dcd676095 100644
--- a/opencores/spi_boot/bench/vhdl/card.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/card.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd
index caa171362..caa171362 100644
--- a/opencores/spi_boot/bench/vhdl/tb-c.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd
index b359fa7c5..b359fa7c5 100644
--- a/opencores/spi_boot/bench/vhdl/tb.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
index 3c0fb902f..3c0fb902f 100644
--- a/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
index 1c33ac3d0..1c33ac3d0 100644
--- a/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
index b5baf604e..b5baf604e 100644
--- a/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
index 9cdf3eaa1..9cdf3eaa1 100644
--- a/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_elem.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd
index 689cec037..689cec037 100644
--- a/opencores/spi_boot/bench/vhdl/tb_elem.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
index 7534aafdc..7534aafdc 100644
--- a/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
index 84273abc5..84273abc5 100644
--- a/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
diff --git a/opencores/spi_boot/bench/vhdl/tb_rl.vhd b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd
index 9f28e62b4..9f28e62b4 100644
--- a/opencores/spi_boot/bench/vhdl/tb_rl.vhd
+++ b/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd
diff --git a/opencores/spi_boot/doc/CVS/Entries b/usrp2/opencores/spi_boot/doc/CVS/Entries
index 630615f41..630615f41 100644
--- a/opencores/spi_boot/doc/CVS/Entries
+++ b/usrp2/opencores/spi_boot/doc/CVS/Entries
diff --git a/opencores/spi_boot/doc/CVS/Repository b/usrp2/opencores/spi_boot/doc/CVS/Repository
index 07fb78846..07fb78846 100644
--- a/opencores/spi_boot/doc/CVS/Repository
+++ b/usrp2/opencores/spi_boot/doc/CVS/Repository
diff --git a/opencores/spi_boot/doc/CVS/Root b/usrp2/opencores/spi_boot/doc/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/doc/CVS/Root
+++ b/usrp2/opencores/spi_boot/doc/CVS/Root
diff --git a/opencores/spi_boot/doc/CVS/Template b/usrp2/opencores/spi_boot/doc/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/doc/CVS/Template
+++ b/usrp2/opencores/spi_boot/doc/CVS/Template
diff --git a/opencores/spi_boot/doc/spi_boot.pdf b/usrp2/opencores/spi_boot/doc/spi_boot.pdf
index a889c3f22..a889c3f22 100644
--- a/opencores/spi_boot/doc/spi_boot.pdf
+++ b/usrp2/opencores/spi_boot/doc/spi_boot.pdf
diff --git a/opencores/spi_boot/doc/spi_boot_schematic.pdf b/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
index 92755d5f3..92755d5f3 100644
--- a/opencores/spi_boot/doc/spi_boot_schematic.pdf
+++ b/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
diff --git a/opencores/spi_boot/doc/src/CVS/Entries b/usrp2/opencores/spi_boot/doc/src/CVS/Entries
index b2d32af23..b2d32af23 100644
--- a/opencores/spi_boot/doc/src/CVS/Entries
+++ b/usrp2/opencores/spi_boot/doc/src/CVS/Entries
diff --git a/opencores/spi_boot/doc/src/CVS/Repository b/usrp2/opencores/spi_boot/doc/src/CVS/Repository
index 5f8aafef8..5f8aafef8 100644
--- a/opencores/spi_boot/doc/src/CVS/Repository
+++ b/usrp2/opencores/spi_boot/doc/src/CVS/Repository
diff --git a/opencores/spi_boot/doc/src/CVS/Root b/usrp2/opencores/spi_boot/doc/src/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/doc/src/CVS/Root
+++ b/usrp2/opencores/spi_boot/doc/src/CVS/Root
diff --git a/opencores/spi_boot/doc/src/CVS/Template b/usrp2/opencores/spi_boot/doc/src/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/doc/src/CVS/Template
+++ b/usrp2/opencores/spi_boot/doc/src/CVS/Template
diff --git a/opencores/spi_boot/doc/src/architecture.eps b/usrp2/opencores/spi_boot/doc/src/architecture.eps
index 3e70efdb1..3e70efdb1 100644
--- a/opencores/spi_boot/doc/src/architecture.eps
+++ b/usrp2/opencores/spi_boot/doc/src/architecture.eps
diff --git a/opencores/spi_boot/doc/src/architecture.fig b/usrp2/opencores/spi_boot/doc/src/architecture.fig
index 708e166a8..708e166a8 100644
--- a/opencores/spi_boot/doc/src/architecture.fig
+++ b/usrp2/opencores/spi_boot/doc/src/architecture.fig
diff --git a/opencores/spi_boot/doc/src/initialization.eps b/usrp2/opencores/spi_boot/doc/src/initialization.eps
index ff4ec89e9..ff4ec89e9 100644
--- a/opencores/spi_boot/doc/src/initialization.eps
+++ b/usrp2/opencores/spi_boot/doc/src/initialization.eps
diff --git a/opencores/spi_boot/doc/src/initialization.fig b/usrp2/opencores/spi_boot/doc/src/initialization.fig
index 96ec5f506..96ec5f506 100644
--- a/opencores/spi_boot/doc/src/initialization.fig
+++ b/usrp2/opencores/spi_boot/doc/src/initialization.fig
diff --git a/opencores/spi_boot/doc/src/memory_organization.eps b/usrp2/opencores/spi_boot/doc/src/memory_organization.eps
index 7f48f591d..7f48f591d 100644
--- a/opencores/spi_boot/doc/src/memory_organization.eps
+++ b/usrp2/opencores/spi_boot/doc/src/memory_organization.eps
diff --git a/opencores/spi_boot/doc/src/memory_organization.fig b/usrp2/opencores/spi_boot/doc/src/memory_organization.fig
index e9413110e..e9413110e 100644
--- a/opencores/spi_boot/doc/src/memory_organization.fig
+++ b/usrp2/opencores/spi_boot/doc/src/memory_organization.fig
diff --git a/opencores/spi_boot/doc/src/spi_boot.sxw b/usrp2/opencores/spi_boot/doc/src/spi_boot.sxw
index 634cda5c8..634cda5c8 100644
--- a/opencores/spi_boot/doc/src/spi_boot.sxw
+++ b/usrp2/opencores/spi_boot/doc/src/spi_boot.sxw
diff --git a/opencores/spi_boot/doc/src/transfer.eps b/usrp2/opencores/spi_boot/doc/src/transfer.eps
index b28abc024..b28abc024 100644
--- a/opencores/spi_boot/doc/src/transfer.eps
+++ b/usrp2/opencores/spi_boot/doc/src/transfer.eps
diff --git a/opencores/spi_boot/doc/src/transfer.fig b/usrp2/opencores/spi_boot/doc/src/transfer.fig
index 3d1724050..3d1724050 100644
--- a/opencores/spi_boot/doc/src/transfer.fig
+++ b/usrp2/opencores/spi_boot/doc/src/transfer.fig
diff --git a/opencores/spi_boot/rtl/CVS/Entries b/usrp2/opencores/spi_boot/rtl/CVS/Entries
index a4756ee6f..a4756ee6f 100644
--- a/opencores/spi_boot/rtl/CVS/Entries
+++ b/usrp2/opencores/spi_boot/rtl/CVS/Entries
diff --git a/opencores/spi_boot/rtl/CVS/Repository b/usrp2/opencores/spi_boot/rtl/CVS/Repository
index dcb0a69bc..dcb0a69bc 100644
--- a/opencores/spi_boot/rtl/CVS/Repository
+++ b/usrp2/opencores/spi_boot/rtl/CVS/Repository
diff --git a/opencores/spi_boot/rtl/CVS/Root b/usrp2/opencores/spi_boot/rtl/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/rtl/CVS/Root
+++ b/usrp2/opencores/spi_boot/rtl/CVS/Root
diff --git a/opencores/spi_boot/rtl/CVS/Template b/usrp2/opencores/spi_boot/rtl/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/rtl/CVS/Template
+++ b/usrp2/opencores/spi_boot/rtl/CVS/Template
diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Entries b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries
index 880f353ca..880f353ca 100644
--- a/opencores/spi_boot/rtl/vhdl/CVS/Entries
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries
diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Repository b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository
index a09f391ea..a09f391ea 100644
--- a/opencores/spi_boot/rtl/vhdl/CVS/Repository
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository
diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Root b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/rtl/vhdl/CVS/Root
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root
diff --git a/opencores/spi_boot/rtl/vhdl/CVS/Template b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/rtl/vhdl/CVS/Template
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template
diff --git a/opencores/spi_boot/rtl/vhdl/chip-e.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd
index 0bdd05aff..0bdd05aff 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-e.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
index e43ecb3c4..e43ecb3c4 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
index da88552c4..da88552c4 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
index 090d0b79c..090d0b79c 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
index 5547747b2..5547747b2 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
index cef42d268..cef42d268 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
index 6131013e4..6131013e4 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
index c955a5f3a..c955a5f3a 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
index 91e41ddfb..91e41ddfb 100644
--- a/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries
index 552a7baad..552a7baad 100644
--- a/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries
diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository
index 026a73983..026a73983 100644
--- a/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository
diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Root b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/rtl/vhdl/sample/CVS/Root
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root
diff --git a/opencores/spi_boot/rtl/vhdl/sample/CVS/Template b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/rtl/vhdl/sample/CVS/Template
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template
diff --git a/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
index 8b26c4d57..8b26c4d57 100644
--- a/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
index c604876d7..c604876d7 100644
--- a/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
index 6f11ed34b..6f11ed34b 100644
--- a/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/spi_boot.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
index 3d2b81da7..3d2b81da7 100644
--- a/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
index ac8b544f9..ac8b544f9 100644
--- a/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
index d81e20db6..d81e20db6 100644
--- a/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
diff --git a/opencores/spi_boot/rtl/vhdl/spi_counter.vhd b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
index 8ec7357ea..8ec7357ea 100644
--- a/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
+++ b/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
diff --git a/opencores/spi_boot/sim/CVS/Entries b/usrp2/opencores/spi_boot/sim/CVS/Entries
index 9487498ad..9487498ad 100644
--- a/opencores/spi_boot/sim/CVS/Entries
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diff --git a/opencores/spi_boot/sim/CVS/Repository b/usrp2/opencores/spi_boot/sim/CVS/Repository
index 4e2e09740..4e2e09740 100644
--- a/opencores/spi_boot/sim/CVS/Repository
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diff --git a/opencores/spi_boot/sim/CVS/Root b/usrp2/opencores/spi_boot/sim/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/sim/CVS/Root
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diff --git a/opencores/spi_boot/sim/CVS/Template b/usrp2/opencores/spi_boot/sim/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/sim/CVS/Template
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diff --git a/opencores/spi_boot/sim/rtl_sim/CVS/Entries b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries
index e3d0dc145..e3d0dc145 100644
--- a/opencores/spi_boot/sim/rtl_sim/CVS/Entries
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index 114ab862f..114ab862f 100644
--- a/opencores/spi_boot/sim/rtl_sim/CVS/Repository
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diff --git a/opencores/spi_boot/sim/rtl_sim/CVS/Root b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/sim/rtl_sim/CVS/Root
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diff --git a/opencores/spi_boot/sim/rtl_sim/CVS/Template b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/sim/rtl_sim/CVS/Template
+++ b/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template
diff --git a/opencores/spi_boot/sim/rtl_sim/Makefile b/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile
index 46fb3c635..46fb3c635 100644
--- a/opencores/spi_boot/sim/rtl_sim/Makefile
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diff --git a/opencores/spi_boot/sw/CVS/Entries b/usrp2/opencores/spi_boot/sw/CVS/Entries
index 0f2bd88d4..0f2bd88d4 100644
--- a/opencores/spi_boot/sw/CVS/Entries
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index 98d181ecb..98d181ecb 100644
--- a/opencores/spi_boot/sw/CVS/Repository
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diff --git a/opencores/spi_boot/sw/CVS/Root b/usrp2/opencores/spi_boot/sw/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/sw/CVS/Root
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diff --git a/opencores/spi_boot/sw/CVS/Template b/usrp2/opencores/spi_boot/sw/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/sw/CVS/Template
+++ b/usrp2/opencores/spi_boot/sw/CVS/Template
diff --git a/opencores/spi_boot/sw/misc/CVS/Entries b/usrp2/opencores/spi_boot/sw/misc/CVS/Entries
index e46425fde..e46425fde 100644
--- a/opencores/spi_boot/sw/misc/CVS/Entries
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diff --git a/opencores/spi_boot/sw/misc/CVS/Repository b/usrp2/opencores/spi_boot/sw/misc/CVS/Repository
index 0519f4b59..0519f4b59 100644
--- a/opencores/spi_boot/sw/misc/CVS/Repository
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diff --git a/opencores/spi_boot/sw/misc/CVS/Root b/usrp2/opencores/spi_boot/sw/misc/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/spi_boot/sw/misc/CVS/Root
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diff --git a/opencores/spi_boot/sw/misc/CVS/Template b/usrp2/opencores/spi_boot/sw/misc/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/spi_boot/sw/misc/CVS/Template
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diff --git a/opencores/spi_boot/sw/misc/bit_reverse.c b/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c
index 9defb106a..9defb106a 100644
--- a/opencores/spi_boot/sw/misc/bit_reverse.c
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diff --git a/opencores/wb_zbt/CVS/Entries b/usrp2/opencores/wb_zbt/CVS/Entries
index ef78b4f27..ef78b4f27 100644
--- a/opencores/wb_zbt/CVS/Entries
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index ca9c641d0..ca9c641d0 100644
--- a/opencores/wb_zbt/CVS/Repository
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diff --git a/opencores/wb_zbt/CVS/Root b/usrp2/opencores/wb_zbt/CVS/Root
index 44b2aa23b..44b2aa23b 100644
--- a/opencores/wb_zbt/CVS/Root
+++ b/usrp2/opencores/wb_zbt/CVS/Root
diff --git a/opencores/wb_zbt/CVS/Template b/usrp2/opencores/wb_zbt/CVS/Template
index e69de29bb..e69de29bb 100644
--- a/opencores/wb_zbt/CVS/Template
+++ b/usrp2/opencores/wb_zbt/CVS/Template
diff --git a/opencores/wb_zbt/wb_zbt.v b/usrp2/opencores/wb_zbt/wb_zbt.v
index 8f9232752..8f9232752 100644
--- a/opencores/wb_zbt/wb_zbt.v
+++ b/usrp2/opencores/wb_zbt/wb_zbt.v
diff --git a/sdr_lib/.gitignore b/usrp2/sdr_lib/.gitignore
index 3c782d589..3c782d589 100644
--- a/sdr_lib/.gitignore
+++ b/usrp2/sdr_lib/.gitignore
diff --git a/sdr_lib/HB.sav b/usrp2/sdr_lib/HB.sav
index c5087e8a6..c5087e8a6 100644
--- a/sdr_lib/HB.sav
+++ b/usrp2/sdr_lib/HB.sav
diff --git a/sdr_lib/SMALL_HB.sav b/usrp2/sdr_lib/SMALL_HB.sav
index 96ba00636..96ba00636 100644
--- a/sdr_lib/SMALL_HB.sav
+++ b/usrp2/sdr_lib/SMALL_HB.sav
diff --git a/sdr_lib/acc.v b/usrp2/sdr_lib/acc.v
index a2da9c86d..a2da9c86d 100644
--- a/sdr_lib/acc.v
+++ b/usrp2/sdr_lib/acc.v
diff --git a/sdr_lib/add2.v b/usrp2/sdr_lib/add2.v
index 13fff803e..13fff803e 100644
--- a/sdr_lib/add2.v
+++ b/usrp2/sdr_lib/add2.v
diff --git a/sdr_lib/add2_and_round.v b/usrp2/sdr_lib/add2_and_round.v
index 146af28da..146af28da 100644
--- a/sdr_lib/add2_and_round.v
+++ b/usrp2/sdr_lib/add2_and_round.v
diff --git a/sdr_lib/add2_and_round_reg.v b/usrp2/sdr_lib/add2_and_round_reg.v
index e7fcbf1a1..e7fcbf1a1 100644
--- a/sdr_lib/add2_and_round_reg.v
+++ b/usrp2/sdr_lib/add2_and_round_reg.v
diff --git a/sdr_lib/add2_reg.v b/usrp2/sdr_lib/add2_reg.v
index 456cf315b..456cf315b 100644
--- a/sdr_lib/add2_reg.v
+++ b/usrp2/sdr_lib/add2_reg.v
diff --git a/sdr_lib/cic_dec_shifter.v b/usrp2/sdr_lib/cic_dec_shifter.v
index aa5ac895b..aa5ac895b 100644
--- a/sdr_lib/cic_dec_shifter.v
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index 9a03081b0..9a03081b0 100755
--- a/sdr_lib/cic_decim.v
+++ b/usrp2/sdr_lib/cic_decim.v
diff --git a/sdr_lib/cic_int_shifter.v b/usrp2/sdr_lib/cic_int_shifter.v
index 18587fa8b..18587fa8b 100644
--- a/sdr_lib/cic_int_shifter.v
+++ b/usrp2/sdr_lib/cic_int_shifter.v
diff --git a/sdr_lib/cic_interp.v b/usrp2/sdr_lib/cic_interp.v
index 9b6928aa1..9b6928aa1 100755
--- a/sdr_lib/cic_interp.v
+++ b/usrp2/sdr_lib/cic_interp.v
diff --git a/sdr_lib/cic_strober.v b/usrp2/sdr_lib/cic_strober.v
index 40d76bdd9..40d76bdd9 100644
--- a/sdr_lib/cic_strober.v
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diff --git a/sdr_lib/clip.v b/usrp2/sdr_lib/clip.v
index 3e6b3a2e2..3e6b3a2e2 100644
--- a/sdr_lib/clip.v
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diff --git a/sdr_lib/clip_and_round.v b/usrp2/sdr_lib/clip_and_round.v
index 4546283a3..4546283a3 100644
--- a/sdr_lib/clip_and_round.v
+++ b/usrp2/sdr_lib/clip_and_round.v
diff --git a/sdr_lib/clip_and_round_reg.v b/usrp2/sdr_lib/clip_and_round_reg.v
index 66fb155fb..66fb155fb 100644
--- a/sdr_lib/clip_and_round_reg.v
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diff --git a/sdr_lib/clip_reg.v b/usrp2/sdr_lib/clip_reg.v
index d5e98d982..d5e98d982 100644
--- a/sdr_lib/clip_reg.v
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diff --git a/sdr_lib/cordic.v b/usrp2/sdr_lib/cordic.v
index b73e7acf1..b73e7acf1 100755
--- a/sdr_lib/cordic.v
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diff --git a/sdr_lib/cordic_stage.v b/usrp2/sdr_lib/cordic_stage.v
index 641ff9108..641ff9108 100755
--- a/sdr_lib/cordic_stage.v
+++ b/usrp2/sdr_lib/cordic_stage.v
diff --git a/sdr_lib/cordic_z24.v b/usrp2/sdr_lib/cordic_z24.v
index cf668d5ec..cf668d5ec 100644
--- a/sdr_lib/cordic_z24.v
+++ b/usrp2/sdr_lib/cordic_z24.v
diff --git a/sdr_lib/ddc.v b/usrp2/sdr_lib/ddc.v
index 0d4da9bbc..0d4da9bbc 100755
--- a/sdr_lib/ddc.v
+++ b/usrp2/sdr_lib/ddc.v
diff --git a/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 2ac429630..2ac429630 100644
--- a/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
diff --git a/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v
index 22d3d44a3..22d3d44a3 100644
--- a/sdr_lib/dsp_core_tx.v
+++ b/usrp2/sdr_lib/dsp_core_tx.v
diff --git a/sdr_lib/duc.v b/usrp2/sdr_lib/duc.v
index 6dac95b49..6dac95b49 100755
--- a/sdr_lib/duc.v
+++ b/usrp2/sdr_lib/duc.v
diff --git a/sdr_lib/dummy_rx.v b/usrp2/sdr_lib/dummy_rx.v
index 99290ecec..99290ecec 100644
--- a/sdr_lib/dummy_rx.v
+++ b/usrp2/sdr_lib/dummy_rx.v
diff --git a/sdr_lib/gen_cordic_consts.py b/usrp2/sdr_lib/gen_cordic_consts.py
index 261e8c223..261e8c223 100755
--- a/sdr_lib/gen_cordic_consts.py
+++ b/usrp2/sdr_lib/gen_cordic_consts.py
diff --git a/sdr_lib/halfband_ideal.v b/usrp2/sdr_lib/halfband_ideal.v
index 484cfff2a..484cfff2a 100644
--- a/sdr_lib/halfband_ideal.v
+++ b/usrp2/sdr_lib/halfband_ideal.v
diff --git a/sdr_lib/halfband_tb.v b/usrp2/sdr_lib/halfband_tb.v
index 231dd00d7..231dd00d7 100644
--- a/sdr_lib/halfband_tb.v
+++ b/usrp2/sdr_lib/halfband_tb.v
diff --git a/sdr_lib/hb/acc.v b/usrp2/sdr_lib/hb/acc.v
index 195d5ea94..195d5ea94 100644
--- a/sdr_lib/hb/acc.v
+++ b/usrp2/sdr_lib/hb/acc.v
diff --git a/sdr_lib/hb/coeff_ram.v b/usrp2/sdr_lib/hb/coeff_ram.v
index 65460822f..65460822f 100644
--- a/sdr_lib/hb/coeff_ram.v
+++ b/usrp2/sdr_lib/hb/coeff_ram.v
diff --git a/sdr_lib/hb/coeff_rom.v b/usrp2/sdr_lib/hb/coeff_rom.v
index 7f8886b4e..7f8886b4e 100644
--- a/sdr_lib/hb/coeff_rom.v
+++ b/usrp2/sdr_lib/hb/coeff_rom.v
diff --git a/sdr_lib/hb/halfband_decim.v b/usrp2/sdr_lib/hb/halfband_decim.v
index dff4d902c..dff4d902c 100644
--- a/sdr_lib/hb/halfband_decim.v
+++ b/usrp2/sdr_lib/hb/halfband_decim.v
diff --git a/sdr_lib/hb/halfband_interp.v b/usrp2/sdr_lib/hb/halfband_interp.v
index cdb11c1f6..cdb11c1f6 100644
--- a/sdr_lib/hb/halfband_interp.v
+++ b/usrp2/sdr_lib/hb/halfband_interp.v
diff --git a/sdr_lib/hb/hbd_tb/HBD b/usrp2/sdr_lib/hb/hbd_tb/HBD
index 574fbba91..574fbba91 100644
--- a/sdr_lib/hb/hbd_tb/HBD
+++ b/usrp2/sdr_lib/hb/hbd_tb/HBD
diff --git a/sdr_lib/hb/hbd_tb/really_golden b/usrp2/sdr_lib/hb/hbd_tb/really_golden
index 2d24a9e14..2d24a9e14 100644
--- a/sdr_lib/hb/hbd_tb/really_golden
+++ b/usrp2/sdr_lib/hb/hbd_tb/really_golden
diff --git a/sdr_lib/hb/hbd_tb/regression b/usrp2/sdr_lib/hb/hbd_tb/regression
index fc279c2f2..fc279c2f2 100644
--- a/sdr_lib/hb/hbd_tb/regression
+++ b/usrp2/sdr_lib/hb/hbd_tb/regression
diff --git a/sdr_lib/hb/hbd_tb/run_hbd b/usrp2/sdr_lib/hb/hbd_tb/run_hbd
index b8aec7574..b8aec7574 100755
--- a/sdr_lib/hb/hbd_tb/run_hbd
+++ b/usrp2/sdr_lib/hb/hbd_tb/run_hbd
diff --git a/sdr_lib/hb/hbd_tb/test_hbd.v b/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v
index 01ab5e7e0..01ab5e7e0 100644
--- a/sdr_lib/hb/hbd_tb/test_hbd.v
+++ b/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v
diff --git a/sdr_lib/hb/mac.v b/usrp2/sdr_lib/hb/mac.v
index 5a270bc73..5a270bc73 100644
--- a/sdr_lib/hb/mac.v
+++ b/usrp2/sdr_lib/hb/mac.v
diff --git a/sdr_lib/hb/mult.v b/usrp2/sdr_lib/hb/mult.v
index a8d4cb1b7..a8d4cb1b7 100644
--- a/sdr_lib/hb/mult.v
+++ b/usrp2/sdr_lib/hb/mult.v
diff --git a/sdr_lib/hb/ram16_2port.v b/usrp2/sdr_lib/hb/ram16_2port.v
index e1761a926..e1761a926 100644
--- a/sdr_lib/hb/ram16_2port.v
+++ b/usrp2/sdr_lib/hb/ram16_2port.v
diff --git a/sdr_lib/hb/ram16_2sum.v b/usrp2/sdr_lib/hb/ram16_2sum.v
index 559b06fd5..559b06fd5 100644
--- a/sdr_lib/hb/ram16_2sum.v
+++ b/usrp2/sdr_lib/hb/ram16_2sum.v
diff --git a/sdr_lib/hb/ram32_2sum.v b/usrp2/sdr_lib/hb/ram32_2sum.v
index d1f55b7d0..d1f55b7d0 100644
--- a/sdr_lib/hb/ram32_2sum.v
+++ b/usrp2/sdr_lib/hb/ram32_2sum.v
diff --git a/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v
index 8fb5ba222..8fb5ba222 100644
--- a/sdr_lib/hb_dec.v
+++ b/usrp2/sdr_lib/hb_dec.v
diff --git a/sdr_lib/hb_dec_tb.v b/usrp2/sdr_lib/hb_dec_tb.v
index 3e5faa80a..3e5faa80a 100644
--- a/sdr_lib/hb_dec_tb.v
+++ b/usrp2/sdr_lib/hb_dec_tb.v
diff --git a/sdr_lib/hb_interp.v b/usrp2/sdr_lib/hb_interp.v
index d16807e15..d16807e15 100644
--- a/sdr_lib/hb_interp.v
+++ b/usrp2/sdr_lib/hb_interp.v
diff --git a/sdr_lib/hb_interp_tb.v b/usrp2/sdr_lib/hb_interp_tb.v
index 52f137f28..52f137f28 100644
--- a/sdr_lib/hb_interp_tb.v
+++ b/usrp2/sdr_lib/hb_interp_tb.v
diff --git a/sdr_lib/hb_tb.v b/usrp2/sdr_lib/hb_tb.v
index 7e960fd13..7e960fd13 100644
--- a/sdr_lib/hb_tb.v
+++ b/usrp2/sdr_lib/hb_tb.v
diff --git a/sdr_lib/input.dat b/usrp2/sdr_lib/input.dat
index 1e649ac2e..1e649ac2e 100644
--- a/sdr_lib/input.dat
+++ b/usrp2/sdr_lib/input.dat
diff --git a/sdr_lib/integrate.v b/usrp2/sdr_lib/integrate.v
index db33de979..db33de979 100644
--- a/sdr_lib/integrate.v
+++ b/usrp2/sdr_lib/integrate.v
diff --git a/sdr_lib/med_hb_int.v b/usrp2/sdr_lib/med_hb_int.v
index bc8066509..bc8066509 100644
--- a/sdr_lib/med_hb_int.v
+++ b/usrp2/sdr_lib/med_hb_int.v
diff --git a/sdr_lib/output.dat b/usrp2/sdr_lib/output.dat
index 15db3ced4..15db3ced4 100644
--- a/sdr_lib/output.dat
+++ b/usrp2/sdr_lib/output.dat
diff --git a/sdr_lib/round.v b/usrp2/sdr_lib/round.v
index c4f9ec9cd..c4f9ec9cd 100644
--- a/sdr_lib/round.v
+++ b/usrp2/sdr_lib/round.v
diff --git a/sdr_lib/round_reg.v b/usrp2/sdr_lib/round_reg.v
index aa0972dab..aa0972dab 100644
--- a/sdr_lib/round_reg.v
+++ b/usrp2/sdr_lib/round_reg.v
diff --git a/sdr_lib/rssi.v b/usrp2/sdr_lib/rssi.v
index e45e2148c..e45e2148c 100644
--- a/sdr_lib/rssi.v
+++ b/usrp2/sdr_lib/rssi.v
diff --git a/sdr_lib/rx_control.v b/usrp2/sdr_lib/rx_control.v
index 0adeb0794..0adeb0794 100644
--- a/sdr_lib/rx_control.v
+++ b/usrp2/sdr_lib/rx_control.v
diff --git a/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index bedbd40e6..bedbd40e6 100644
--- a/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
diff --git a/sdr_lib/rx_dcoffset_tb.v b/usrp2/sdr_lib/rx_dcoffset_tb.v
index a8b4ec20f..a8b4ec20f 100644
--- a/sdr_lib/rx_dcoffset_tb.v
+++ b/usrp2/sdr_lib/rx_dcoffset_tb.v
diff --git a/sdr_lib/sign_extend.v b/usrp2/sdr_lib/sign_extend.v
index eae67faf2..eae67faf2 100644
--- a/sdr_lib/sign_extend.v
+++ b/usrp2/sdr_lib/sign_extend.v
diff --git a/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v
index 8519b628a..8519b628a 100644
--- a/sdr_lib/small_hb_dec.v
+++ b/usrp2/sdr_lib/small_hb_dec.v
diff --git a/sdr_lib/small_hb_dec_tb.v b/usrp2/sdr_lib/small_hb_dec_tb.v
index 0d6a0689e..0d6a0689e 100644
--- a/sdr_lib/small_hb_dec_tb.v
+++ b/usrp2/sdr_lib/small_hb_dec_tb.v
diff --git a/sdr_lib/small_hb_int.v b/usrp2/sdr_lib/small_hb_int.v
index f80d3cac3..f80d3cac3 100644
--- a/sdr_lib/small_hb_int.v
+++ b/usrp2/sdr_lib/small_hb_int.v
diff --git a/sdr_lib/small_hb_int_tb.v b/usrp2/sdr_lib/small_hb_int_tb.v
index 71d77f0a8..71d77f0a8 100644
--- a/sdr_lib/small_hb_int_tb.v
+++ b/usrp2/sdr_lib/small_hb_int_tb.v
diff --git a/sdr_lib/tx_control.v b/usrp2/sdr_lib/tx_control.v
index e5fed0b93..e5fed0b93 100644
--- a/sdr_lib/tx_control.v
+++ b/usrp2/sdr_lib/tx_control.v
diff --git a/serdes/serdes.v b/usrp2/serdes/serdes.v
index 17049bfe6..17049bfe6 100644
--- a/serdes/serdes.v
+++ b/usrp2/serdes/serdes.v
diff --git a/serdes/serdes_fc_rx.v b/usrp2/serdes/serdes_fc_rx.v
index 4dd46e27f..4dd46e27f 100644
--- a/serdes/serdes_fc_rx.v
+++ b/usrp2/serdes/serdes_fc_rx.v
diff --git a/serdes/serdes_fc_tx.v b/usrp2/serdes/serdes_fc_tx.v
index 2fe967c8d..2fe967c8d 100644
--- a/serdes/serdes_fc_tx.v
+++ b/usrp2/serdes/serdes_fc_tx.v
diff --git a/serdes/serdes_rx.v b/usrp2/serdes/serdes_rx.v
index afefccaa1..afefccaa1 100644
--- a/serdes/serdes_rx.v
+++ b/usrp2/serdes/serdes_rx.v
diff --git a/serdes/serdes_tb.v b/usrp2/serdes/serdes_tb.v
index eb8e019fc..eb8e019fc 100644
--- a/serdes/serdes_tb.v
+++ b/usrp2/serdes/serdes_tb.v
diff --git a/serdes/serdes_tx.v b/usrp2/serdes/serdes_tx.v
index 2e5e3bd80..2e5e3bd80 100644
--- a/serdes/serdes_tx.v
+++ b/usrp2/serdes/serdes_tx.v
diff --git a/simple_gemac/.gitignore b/usrp2/simple_gemac/.gitignore
index 17f35e962..17f35e962 100644
--- a/simple_gemac/.gitignore
+++ b/usrp2/simple_gemac/.gitignore
diff --git a/simple_gemac/address_filter.v b/usrp2/simple_gemac/address_filter.v
index 50a52b954..50a52b954 100644
--- a/simple_gemac/address_filter.v
+++ b/usrp2/simple_gemac/address_filter.v
diff --git a/simple_gemac/crc.v b/usrp2/simple_gemac/crc.v
index ac019083a..ac019083a 100644
--- a/simple_gemac/crc.v
+++ b/usrp2/simple_gemac/crc.v
diff --git a/simple_gemac/delay_line.v b/usrp2/simple_gemac/delay_line.v
index d371bb9c5..d371bb9c5 100644
--- a/simple_gemac/delay_line.v
+++ b/usrp2/simple_gemac/delay_line.v
diff --git a/simple_gemac/eth_tasks.v b/usrp2/simple_gemac/eth_tasks.v
index d49f30e24..d49f30e24 100644
--- a/simple_gemac/eth_tasks.v
+++ b/usrp2/simple_gemac/eth_tasks.v
diff --git a/usrp2/simple_gemac/eth_tasks_f19.v b/usrp2/simple_gemac/eth_tasks_f19.v
new file mode 100644
index 000000000..ff3ae5407
--- /dev/null
+++ b/usrp2/simple_gemac/eth_tasks_f19.v
@@ -0,0 +1,92 @@
+
+
+task SendFlowCtrl;
+   input [15:0] fc_len;
+   begin
+      $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+      pause_time <= fc_len;
+      @(posedge eth_clk);
+      pause_req <= 1;
+      @(posedge eth_clk);
+      pause_req <= 0;
+      $display("Sent Flow Control");
+   end
+endtask // SendFlowCtrl
+
+task SendPacket_to_fifo19;
+   input [31:0] data_start;
+   input [15:0] data_len;
+   reg [15:0] 	count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count   <= 2;
+      tx_f19_data <= {2'b0, 1'b0, 1'b1, data_start};
+      tx_f19_src_rdy  <= 1;
+      #1;
+      while(count < data_len)
+	begin
+	   while(~tx_f19_dst_rdy)
+	     @(posedge sys_clk);
+	   @(posedge sys_clk);
+	   //tx_f19_data[31:0] = tx_f19_data[31:0] + 32'h0101_0101;
+	   count 	   = count + 4;
+	   //tx_f19_data[32] <= 0;
+	end
+      //tx_f19_data[33] 	  <= 1;
+      while(~tx_f19_dst_rdy)
+	@(posedge sys_clk);
+      @(posedge sys_clk);
+      tx_f19_src_rdy <= 0;
+   end
+endtask // SendPacket_to_fifo19
+
+/*
+task Waiter;
+   input [31:0] wait_length;
+   begin
+      tx_ll_src_rdy2 <= 0;
+      repeat(wait_length)
+	@(posedge clk);
+      tx_ll_src_rdy2 <= 1;
+   end
+endtask // Waiter
+*/
+
+/*
+task SendPacketFromFile_f19;
+   input [31:0] data_len;
+   input [31:0] wait_length;
+   input [31:0] wait_time;
+   
+   integer count;
+   begin
+      $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+
+      while(~tx_f19_dst_rdy)
+	@(posedge clk);
+      tx_f19_data <= pkt_rom[0];
+      tx_f19_src_rdy <= 1;
+      tx_f19_eof     <= 0;
+      @(posedge clk);
+      
+      for(i=1;i<data_len-1;i=i+1)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   tx_ll_data2 <= pkt_rom[i];
+	   tx_ll_sof2  <= 0;
+	   @(posedge clk);
+//	   if(i==wait_time)
+//	     Waiter(wait_length);
+	end
+      
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_eof2 <= 1;
+      tx_ll_data2 <= pkt_rom[data_len-1];
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask
+*/
diff --git a/simple_gemac/eth_tasks_f36.v b/usrp2/simple_gemac/eth_tasks_f36.v
index efd72778b..efd72778b 100644
--- a/simple_gemac/eth_tasks_f36.v
+++ b/usrp2/simple_gemac/eth_tasks_f36.v
diff --git a/simple_gemac/flow_ctrl_rx.v b/usrp2/simple_gemac/flow_ctrl_rx.v
index d09bf377f..d09bf377f 100644
--- a/simple_gemac/flow_ctrl_rx.v
+++ b/usrp2/simple_gemac/flow_ctrl_rx.v
diff --git a/simple_gemac/flow_ctrl_tx.v b/usrp2/simple_gemac/flow_ctrl_tx.v
index f80f5a76d..f80f5a76d 100644
--- a/simple_gemac/flow_ctrl_tx.v
+++ b/usrp2/simple_gemac/flow_ctrl_tx.v
diff --git a/simple_gemac/ll8_to_txmac.v b/usrp2/simple_gemac/ll8_to_txmac.v
index 3530a0c59..3530a0c59 100644
--- a/simple_gemac/ll8_to_txmac.v
+++ b/usrp2/simple_gemac/ll8_to_txmac.v
diff --git a/simple_gemac/miim/eth_clockgen.v b/usrp2/simple_gemac/miim/eth_clockgen.v
index 9da732f7f..9da732f7f 100644
--- a/simple_gemac/miim/eth_clockgen.v
+++ b/usrp2/simple_gemac/miim/eth_clockgen.v
diff --git a/simple_gemac/miim/eth_miim.v b/usrp2/simple_gemac/miim/eth_miim.v
index a15c94205..a15c94205 100644
--- a/simple_gemac/miim/eth_miim.v
+++ b/usrp2/simple_gemac/miim/eth_miim.v
diff --git a/simple_gemac/miim/eth_outputcontrol.v b/usrp2/simple_gemac/miim/eth_outputcontrol.v
index 3df6c560a..3df6c560a 100644
--- a/simple_gemac/miim/eth_outputcontrol.v
+++ b/usrp2/simple_gemac/miim/eth_outputcontrol.v
diff --git a/simple_gemac/miim/eth_shiftreg.v b/usrp2/simple_gemac/miim/eth_shiftreg.v
index 0b97bb7bc..0b97bb7bc 100644
--- a/simple_gemac/miim/eth_shiftreg.v
+++ b/usrp2/simple_gemac/miim/eth_shiftreg.v
diff --git a/simple_gemac/rxmac_to_ll8.v b/usrp2/simple_gemac/rxmac_to_ll8.v
index 5ec233d95..5ec233d95 100644
--- a/simple_gemac/rxmac_to_ll8.v
+++ b/usrp2/simple_gemac/rxmac_to_ll8.v
diff --git a/simple_gemac/simple_gemac.v b/usrp2/simple_gemac/simple_gemac.v
index e7f327358..2dd8deb99 100644
--- a/simple_gemac/simple_gemac.v
+++ b/usrp2/simple_gemac/simple_gemac.v
@@ -16,7 +16,9 @@ module simple_gemac
    output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack,
 
    // TX Client Interface
-   output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack
+   output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack,
+
+   output [31:0] debug
    );
 
    localparam SGE_IFG 		     = 8'd12;  // 12 should be the absolute minimum
@@ -46,7 +48,8 @@ module simple_gemac
       .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
       .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
       .pass_pause(pass_pause), .pass_all(pass_all),
-      .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd) 
+      .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd),
+      .debug(debug)
       );
 
    flow_ctrl_tx flow_ctrl_tx
diff --git a/simple_gemac/simple_gemac_rx.v b/usrp2/simple_gemac/simple_gemac_rx.v
index 45ddd6dfa..b02bb0758 100644
--- a/simple_gemac/simple_gemac_rx.v
+++ b/usrp2/simple_gemac/simple_gemac_rx.v
@@ -6,7 +6,8 @@ module simple_gemac_rx
    output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
    input [47:0] ucast_addr, input [47:0] mcast_addr, 
    input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
-   output reg [15:0] pause_quanta_rcvd, output pause_rcvd );
+   output reg [15:0] pause_quanta_rcvd, output pause_rcvd,
+   output [31:0] debug );
 
    localparam RX_IDLE 		  = 0;
    localparam RX_PREAMBLE 	  = 1;
@@ -170,5 +171,7 @@ module simple_gemac_rx
        pause_quanta_rcvd[7:0] <= rxd_d1;
    
    assign rx_clk 	  = GMII_RX_CLK;
+
+   assign debug = rx_state;
    
 endmodule // simple_gemac_rx
diff --git a/simple_gemac/simple_gemac_tb.v b/usrp2/simple_gemac/simple_gemac_tb.v
index 6091751a7..6091751a7 100644
--- a/simple_gemac/simple_gemac_tb.v
+++ b/usrp2/simple_gemac/simple_gemac_tb.v
diff --git a/simple_gemac/simple_gemac_tx.v b/usrp2/simple_gemac/simple_gemac_tx.v
index dd870d04d..dd870d04d 100644
--- a/simple_gemac/simple_gemac_tx.v
+++ b/usrp2/simple_gemac/simple_gemac_tx.v
diff --git a/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v
index 6df277e3e..6df277e3e 100644
--- a/simple_gemac/simple_gemac_wb.v
+++ b/usrp2/simple_gemac/simple_gemac_wb.v
diff --git a/simple_gemac/simple_gemac_wrapper.build b/usrp2/simple_gemac/simple_gemac_wrapper.build
index 30f65ab17..30f65ab17 100755
--- a/simple_gemac/simple_gemac_wrapper.build
+++ b/usrp2/simple_gemac/simple_gemac_wrapper.build
diff --git a/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v
index efcf89276..efcf89276 100644
--- a/simple_gemac/simple_gemac_wrapper.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper.v
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.build b/usrp2/simple_gemac/simple_gemac_wrapper19.build
new file mode 100755
index 000000000..4be0aac1f
--- /dev/null
+++ b/usrp2/simple_gemac/simple_gemac_wrapper19.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.v b/usrp2/simple_gemac/simple_gemac_wrapper19.v
new file mode 100644
index 000000000..6cdbd1a59
--- /dev/null
+++ b/usrp2/simple_gemac/simple_gemac_wrapper19.v
@@ -0,0 +1,170 @@
+
+module simple_gemac_wrapper19
+  #(parameter RXFIFOSIZE=9,
+    parameter TXFIFOSIZE=6)
+   (input clk125, input reset,
+    // GMII
+    output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+    input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+    
+    // Client FIFO Interfaces
+    input sys_clk,
+    output [18:0] rx_f19_data, output rx_f19_src_rdy, input rx_f19_dst_rdy,
+    input [18:0] tx_f19_data, input tx_f19_src_rdy, output tx_f19_dst_rdy,
+    
+    // Wishbone Interface
+    input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
+    input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
+    
+    // MIIM
+    inout mdio, output mdc,
+    output [31:0] debug);
+
+   wire 	  clear = 0;
+   wire [7:0] 	  rx_data, tx_data;
+   wire 	  tx_clk, tx_valid, tx_error, tx_ack;
+   wire 	  rx_clk, rx_valid, rx_error, rx_ack;
+   
+   wire [47:0] 	  ucast_addr, mcast_addr;
+   wire 	  pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
+   wire 	  pause_req;
+   wire 	  pause_request_en, pause_respect_en;
+   wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
+
+   wire [31:0] 	  debug_state;
+      
+   wire 	  tx_reset, rx_reset;
+   reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
+   reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
+   
+   simple_gemac simple_gemac
+     (.clk125(clk125),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time_req(pause_time_req), 
+      .pause_respect_en(pause_respect_en),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .rx_clk(rx_clk), .rx_data(rx_data),
+      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .tx_clk(tx_clk), .tx_data(tx_data), 
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .debug(debug_state)
+      );
+   
+   simple_gemac_wb simple_gemac_wb
+     (.wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+      .mdio(mdio), .mdc(mdc),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all), 
+      .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
+      .pause_time(pause_time), .pause_thresh(pause_thresh) );
+
+   // RX FIFO Chain
+   wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   
+   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
+   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
+   
+   wire [7:0] 	  rx_ll_data, rx_ll_data2;
+   
+   wire [18:0] 	  rx_f19_data_int1;
+   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1;
+   
+   rxmac_to_ll8 rx_adapt
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+   ll8_shortfifo rx_sfifo
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
+   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
+   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
+   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
+   
+   ll8_to_fifo19 ll8_to_fifo19
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
+      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
+
+   //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+     (.wclk(rx_clk), .datain(rx_f19_data_int1), 
+      .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .space(rx_fifo_space),
+      .rclk(sys_clk), .dataout(rx_f19_data), 
+      .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), .arst(reset));
+   
+   // TX FIFO Chain
+   wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
+   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
+   wire [7:0] 	  tx_ll_data, tx_ll_data2;
+   wire [18:0] 	  tx_f19_data_int1;
+   wire 	  tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1;
+
+   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) tx_2clk_fifo
+     (.wclk(sys_clk), .datain(tx_f19_data), 
+      .src_rdy_i(tx_f19_src_rdy), .dst_rdy_o(tx_f19_dst_rdy), .space(),
+      .rclk(tx_clk), .dataout(tx_f19_data_int1), 
+      .src_rdy_o(tx_f19_src_rdy_int1), .dst_rdy_i(tx_f19_dst_rdy_int1), .occupied(), .arst(rx_reset));
+   
+   fifo19_to_ll8 fifo19_to_ll8
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .f19_data(tx_f19_data_int1), .f19_src_rdy_i(tx_f19_src_rdy_int1), .f19_dst_rdy_o(tx_f19_dst_rdy_int1),
+      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
+      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+
+   assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
+   assign tx_ll_eof2 	    = ~tx_ll_eof2_n;
+   assign tx_ll_src_rdy2    = ~tx_ll_src_rdy2_n;
+   assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
+   
+   ll8_shortfifo tx_sfifo
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+   
+   ll8_to_txmac ll8_to_txmac
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+
+   // Flow Control
+   flow_ctrl_rx flow_ctrl_rx
+     (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
+      .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
+      .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
+   
+   wire [31:0] 	  debug_tx, debug_rx;
+
+   assign debug_tx  = { { tx_ll_data },
+			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
+			  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
+			{ tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]},
+			{ tx_data} };
+   assign debug_rx  = { { rx_f19_src_rdy, rx_f19_dst_rdy, debug_state[5:0] },
+			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
+			  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
+			{ rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]},
+			{ rx_data} };
+
+   assign debug  = debug_rx;
+   
+endmodule // simple_gemac_wrapper19
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
new file mode 100644
index 000000000..7d57542dc
--- /dev/null
+++ b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
@@ -0,0 +1,209 @@
+
+
+module simple_gemac_wrapper19_tb;
+`include "eth_tasks_f19.v"
+     
+   reg reset   = 1;
+   initial #1000 reset = 0;
+   wire wb_rst 	= reset;
+
+   reg eth_clk     = 0;
+   always #50 eth_clk = ~eth_clk;
+
+   reg wb_clk 	= 0;
+   always #173 wb_clk = ~wb_clk;
+
+   reg sys_clk 	= 0;
+   always #77 sys_clk = ~ sys_clk;
+   
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+   wire [31:0] wb_dat_o;
+   reg [31:0]  wb_dat_i;
+   reg [7:0]   wb_adr;
+   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
+   wire        wb_ack;
+
+   reg [18:0]  tx_f19_data=0;
+   reg 	       tx_f19_src_rdy = 0;
+   wire        tx_f19_dst_rdy;
+   wire [35:0] rx_f36_data;
+   wire        rx_f36_src_rdy;
+   wire        rx_f36_dst_rdy = 1;
+   
+   simple_gemac_wrapper19 simple_gemac_wrapper19
+     (.clk125(eth_clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      //.pause_req(pause_req), .pause_time(pause_time),
+
+      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+
+      .mdio(), .mdc(),
+      .debug() );
+   
+   initial $dumpfile("simple_gemac_wrapper19_tb.vcd");
+   initial $dumpvars(0,simple_gemac_wrapper19_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge wb_clk);
+	WishboneWR(0,6'b111101); 
+	WishboneWR(4,16'hA0B0);
+	WishboneWR(8,32'hC0D0_A1B1);
+	WishboneWR(12,16'h0000);
+	WishboneWR(16,32'h0000_0000);
+	
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge eth_clk);
+	#30000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
+	#10000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge eth_clk); 
+
+	repeat (1000)
+	  @(posedge sys_clk);
+	SendPacket_to_fifo19(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
+	repeat (1000)
+	  @(posedge sys_clk);
+
+	SendPacket_to_fifo19(32'hAABBCCDD,100);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge sys_clk);
+/*
+ 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_f36(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,30);
+ */
+	#100000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge eth_clk);
+	FORCE_ERR <= 1;
+	@(posedge eth_clk);
+	FORCE_ERR <= 0;
+     end
+/*
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+  */
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+   task WishboneWR;
+      input [7:0] adr;
+      input [31:0] value;
+      begin
+	 wb_adr   <= adr;
+	 wb_dat_i <= value;
+	 wb_stb   <= 1;
+	 wb_cyc   <= 1;
+	 wb_we 	  <= 1;
+	 while (~wb_ack)
+	   @(posedge wb_clk);
+	 @(posedge wb_clk);
+	 wb_stb <= 0;
+	 wb_cyc <= 0;
+	 wb_we 	<= 0;
+      end
+   endtask // WishboneWR
+   /*
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   */
+endmodule // simple_gemac_wrapper19_tb
diff --git a/simple_gemac/simple_gemac_wrapper_f36_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v
index 804fa8748..804fa8748 100644
--- a/simple_gemac/simple_gemac_wrapper_f36_tb.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v
diff --git a/simple_gemac/simple_gemac_wrapper_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
index 26a471a49..26a471a49 100644
--- a/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
diff --git a/simple_gemac/test_packet.mem b/usrp2/simple_gemac/test_packet.mem
index 7f41d3e42..7f41d3e42 100644
--- a/simple_gemac/test_packet.mem
+++ b/usrp2/simple_gemac/test_packet.mem
diff --git a/testbench/.gitignore b/usrp2/testbench/.gitignore
index eedcf9652..eedcf9652 100644
--- a/testbench/.gitignore
+++ b/usrp2/testbench/.gitignore
diff --git a/testbench/Makefile b/usrp2/testbench/Makefile
index 6032a0123..6032a0123 100644
--- a/testbench/Makefile
+++ b/usrp2/testbench/Makefile
diff --git a/testbench/README b/usrp2/testbench/README
index 14bbb68bb..14bbb68bb 100644
--- a/testbench/README
+++ b/usrp2/testbench/README
diff --git a/testbench/cmdfile b/usrp2/testbench/cmdfile
index 8083eb92a..8083eb92a 100644
--- a/testbench/cmdfile
+++ b/usrp2/testbench/cmdfile
diff --git a/timing/.gitignore b/usrp2/timing/.gitignore
index 515552fdb..515552fdb 100644
--- a/timing/.gitignore
+++ b/usrp2/timing/.gitignore
diff --git a/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 8ccde3f54..8ccde3f54 100644
--- a/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
diff --git a/timing/time_compare.v b/usrp2/timing/time_compare.v
index a21c9f8e0..a21c9f8e0 100644
--- a/timing/time_compare.v
+++ b/usrp2/timing/time_compare.v
diff --git a/timing/time_receiver.v b/usrp2/timing/time_receiver.v
index 8e7d3f1ea..8e7d3f1ea 100644
--- a/timing/time_receiver.v
+++ b/usrp2/timing/time_receiver.v
diff --git a/timing/time_sender.v b/usrp2/timing/time_sender.v
index aa2fcbbdb..aa2fcbbdb 100644
--- a/timing/time_sender.v
+++ b/usrp2/timing/time_sender.v
diff --git a/timing/time_sync.v b/usrp2/timing/time_sync.v
index c0c8e195f..c0c8e195f 100644
--- a/timing/time_sync.v
+++ b/usrp2/timing/time_sync.v
diff --git a/timing/time_transfer_tb.v b/usrp2/timing/time_transfer_tb.v
index 2b75c60bd..2b75c60bd 100644
--- a/timing/time_transfer_tb.v
+++ b/usrp2/timing/time_transfer_tb.v
diff --git a/timing/timer.v b/usrp2/timing/timer.v
index 70c9746be..70c9746be 100644
--- a/timing/timer.v
+++ b/usrp2/timing/timer.v
diff --git a/top/.gitignore b/usrp2/top/.gitignore
index bf1b77066..bf1b77066 100644
--- a/top/.gitignore
+++ b/usrp2/top/.gitignore
diff --git a/top/eth_test/.gitignore b/usrp2/top/eth_test/.gitignore
index b30397081..b30397081 100644
--- a/top/eth_test/.gitignore
+++ b/usrp2/top/eth_test/.gitignore
diff --git a/top/eth_test/eth_sim_top.v b/usrp2/top/eth_test/eth_sim_top.v
index 640a4e60f..640a4e60f 100644
--- a/top/eth_test/eth_sim_top.v
+++ b/usrp2/top/eth_test/eth_sim_top.v
diff --git a/top/eth_test/eth_tb.v b/usrp2/top/eth_test/eth_tb.v
index 451ce1e7e..451ce1e7e 100644
--- a/top/eth_test/eth_tb.v
+++ b/usrp2/top/eth_test/eth_tb.v
diff --git a/top/single_u2_sim/single_u2_sim.v b/usrp2/top/single_u2_sim/single_u2_sim.v
index 2a7b24849..2a7b24849 100644
--- a/top/single_u2_sim/single_u2_sim.v
+++ b/usrp2/top/single_u2_sim/single_u2_sim.v
diff --git a/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl
index fe9db87af..fe9db87af 100644
--- a/top/tcl/ise_helper.tcl
+++ b/usrp2/top/tcl/ise_helper.tcl
diff --git a/top/u2_core/.gitignore b/usrp2/top/u2_core/.gitignore
index 9728395c1..9728395c1 100644
--- a/top/u2_core/.gitignore
+++ b/usrp2/top/u2_core/.gitignore
diff --git a/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v
index 591c10232..a9c97c869 100644
--- a/top/u2_core/u2_core.v
+++ b/usrp2/top/u2_core/u2_core.v
@@ -136,12 +136,14 @@ module u2_core
    input [3:0] clock_divider
    );
 
-   localparam SR_RX_DSP = 160;
-   localparam SR_RX_CTRL = 176;
-   localparam SR_TX_DSP = 208;
-   localparam SR_TX_CTRL = 224;
-   localparam SR_TIME64 = 192;
-   localparam SR_SIMTIMER = 198;
+   localparam SR_BUF_POOL = 64;   // Uses 1 reg
+   localparam SR_UDP_SM   = 96;   // 64 regs
+   localparam SR_RX_DSP   = 160;  // 16
+   localparam SR_RX_CTRL  = 176;  // 16
+   localparam SR_TIME64   = 192;  //  3
+   localparam SR_SIMTIMER = 198;  //  2
+   localparam SR_TX_DSP   = 208;  // 16
+   localparam SR_TX_CTRL  = 224;  // 16
    
    wire [7:0] 	set_addr;
    wire [31:0] 	set_data;
@@ -157,8 +159,8 @@ module u2_core
    wire [31:0] 	debug_gpio_0, debug_gpio_1;
    wire [31:0] 	atr_lines;
 
-   wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, 
-		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
+   wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
 
    wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
    wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
@@ -342,7 +344,7 @@ module u2_core
    wire [3:0] 	 wr0_flags, wr1_flags, wr2_flags, wr3_flags;
    wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
    
-   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool
+   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
       .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
@@ -421,19 +423,31 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
 
-   simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper
+   wire [18:0] 	 rx_f19_data, tx_f19_data;
+   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+   
+   simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
      (.clk125(clk_to_mac),  .reset(wb_rst),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       .sys_clk(dsp_clk),
-      .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
-      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
       .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
       .mdio(MDIO), .mdc(MDC),
       .debug(debug_mac));
+
+   udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
+      .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy_o(wr2_ready_i), .rx_f36_dst_rdy_i(wr2_ready_o),
+      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), .tx_f36_dst_rdy_o(rd2_ready_i),
+      .debug(debug_udp) );
    
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #7
@@ -707,7 +721,7 @@ module u2_core
      eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
 			{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
    
-   assign  debug_clk[0]  = 0; // wb_clk;
+   assign  debug_clk[0]  = GMII_RX_CLK; // wb_clk;
    assign  debug_clk[1]  = dsp_clk;
 
 /*
@@ -729,9 +743,13 @@ module u2_core
 			     { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
  */
 
-   assign debug = debug_vt;
-   assign debug_gpio_0 = sample_tx;
-   assign debug_gpio_1 = 32'hDEAD_BEEF;
+   assign debug = debug_udp;
+   assign debug_gpio_0 = debug_mac;
+   assign debug_gpio_1 = { { tx_f19_data[15:8] },
+			   { tx_f19_data[7:0] },
+			   { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] },
+			   { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } };
+   
    
 endmodule // u2_core
 
diff --git a/top/u2_rev1/.gitignore b/usrp2/top/u2_rev1/.gitignore
index de5b50277..de5b50277 100644
--- a/top/u2_rev1/.gitignore
+++ b/usrp2/top/u2_rev1/.gitignore
diff --git a/top/u2_rev1/Makefile b/usrp2/top/u2_rev1/Makefile
index b3245d883..b3245d883 100644
--- a/top/u2_rev1/Makefile
+++ b/usrp2/top/u2_rev1/Makefile
diff --git a/top/u2_rev1/u2_fpga.ise b/usrp2/top/u2_rev1/u2_fpga.ise
index f90caf024..f90caf024 100644
--- a/top/u2_rev1/u2_fpga.ise
+++ b/usrp2/top/u2_rev1/u2_fpga.ise
diff --git a/top/u2_rev1/u2_fpga.ucf b/usrp2/top/u2_rev1/u2_fpga.ucf
index 5d2124819..5d2124819 100755
--- a/top/u2_rev1/u2_fpga.ucf
+++ b/usrp2/top/u2_rev1/u2_fpga.ucf
diff --git a/top/u2_rev1/u2_fpga_top.prj b/usrp2/top/u2_rev1/u2_fpga_top.prj
index 544415f4d..544415f4d 100644
--- a/top/u2_rev1/u2_fpga_top.prj
+++ b/usrp2/top/u2_rev1/u2_fpga_top.prj
diff --git a/top/u2_rev1/u2_fpga_top.v b/usrp2/top/u2_rev1/u2_fpga_top.v
index 63798a0c8..63798a0c8 100644
--- a/top/u2_rev1/u2_fpga_top.v
+++ b/usrp2/top/u2_rev1/u2_fpga_top.v
diff --git a/top/u2_rev2/.gitignore b/usrp2/top/u2_rev2/.gitignore
index 432f8fd58..432f8fd58 100644
--- a/top/u2_rev2/.gitignore
+++ b/usrp2/top/u2_rev2/.gitignore
diff --git a/top/u2_rev2/Makefile b/usrp2/top/u2_rev2/Makefile
index 275c24b02..275c24b02 100644
--- a/top/u2_rev2/Makefile
+++ b/usrp2/top/u2_rev2/Makefile
diff --git a/top/u2_rev2/u2_rev2.ucf b/usrp2/top/u2_rev2/u2_rev2.ucf
index e18dc6f17..e18dc6f17 100644
--- a/top/u2_rev2/u2_rev2.ucf
+++ b/usrp2/top/u2_rev2/u2_rev2.ucf
diff --git a/top/u2_rev2/u2_rev2.v b/usrp2/top/u2_rev2/u2_rev2.v
index 517285e52..517285e52 100644
--- a/top/u2_rev2/u2_rev2.v
+++ b/usrp2/top/u2_rev2/u2_rev2.v
diff --git a/top/u2_rev3/.gitignore b/usrp2/top/u2_rev3/.gitignore
index 432f8fd58..432f8fd58 100644
--- a/top/u2_rev3/.gitignore
+++ b/usrp2/top/u2_rev3/.gitignore
diff --git a/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index 57d55106f..1fd8638d9 100644
--- a/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -88,7 +88,12 @@ vrt/vita_rx_control.v \
 vrt/vita_rx_framer.v \
 vrt/vita_tx_control.v \
 vrt/vita_tx_deframer.v \
+udp/udp_wrapper.v \
+udp/fifo19_rxrealign.v \
+udp/prot_eng_tx.v \
+udp/add_onescomp.v \
 simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac_wrapper19.v \
 simple_gemac/simple_gemac.v \
 simple_gemac/simple_gemac_wb.v \
 simple_gemac/simple_gemac_tx.v \
@@ -109,11 +114,15 @@ control_lib/newfifo/buffer_pool.v \
 control_lib/newfifo/fifo_2clock.v \
 control_lib/newfifo/fifo_2clock_cascade.v \
 control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/ll8_to_fifo36.v \
 control_lib/newfifo/fifo_short.v \
 control_lib/newfifo/fifo_long.v \
 control_lib/newfifo/fifo_cascade.v \
 control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo19_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo19.v \
+control_lib/newfifo/fifo36_to_fifo19.v \
+control_lib/newfifo/fifo19_to_fifo36.v \
 control_lib/longfifo.v \
 control_lib/shortfifo.v \
 control_lib/medfifo.v \
@@ -123,6 +132,8 @@ coregen/fifo_xlnx_512x36_2clk.v \
 coregen/fifo_xlnx_512x36_2clk.xco \
 coregen/fifo_xlnx_64x36_2clk.v \
 coregen/fifo_xlnx_64x36_2clk.xco \
+coregen/fifo_xlnx_16x19_2clk.v \
+coregen/fifo_xlnx_16x19_2clk.xco \
 extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
diff --git a/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index 255a298ac..255a298ac 100644
--- a/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
diff --git a/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 23a825007..23a825007 100644
--- a/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
diff --git a/top/u2_rev3_2rx_iad/Makefile b/usrp2/top/u2_rev3_2rx_iad/Makefile
index 5b7ed5a8e..5b7ed5a8e 100644
--- a/top/u2_rev3_2rx_iad/Makefile
+++ b/usrp2/top/u2_rev3_2rx_iad/Makefile
diff --git a/top/u2_rev3_2rx_iad/README b/usrp2/top/u2_rev3_2rx_iad/README
index 3efc5305b..3efc5305b 100644
--- a/top/u2_rev3_2rx_iad/README
+++ b/usrp2/top/u2_rev3_2rx_iad/README
diff --git a/top/u2_rev3_2rx_iad/cmdfile b/usrp2/top/u2_rev3_2rx_iad/cmdfile
index 34373a676..34373a676 100644
--- a/top/u2_rev3_2rx_iad/cmdfile
+++ b/usrp2/top/u2_rev3_2rx_iad/cmdfile
diff --git a/top/u2_rev3_2rx_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v
index 4a945bd1a..4a945bd1a 100644
--- a/top/u2_rev3_2rx_iad/dsp_core_rx.v
+++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v
diff --git a/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav
index 12f746860..12f746860 100644
--- a/top/u2_rev3_2rx_iad/dsp_core_tb.sav
+++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav
diff --git a/top/u2_rev3_2rx_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v
index d947df40a..d947df40a 100644
--- a/top/u2_rev3_2rx_iad/dsp_core_tb.v
+++ b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v
diff --git a/top/u2_rev3_2rx_iad/impulse.v b/usrp2/top/u2_rev3_2rx_iad/impulse.v
index fc5e3c1ed..fc5e3c1ed 100644
--- a/top/u2_rev3_2rx_iad/impulse.v
+++ b/usrp2/top/u2_rev3_2rx_iad/impulse.v
diff --git a/top/u2_rev3_2rx_iad/u2_core.v b/usrp2/top/u2_rev3_2rx_iad/u2_core.v
index 3d96a4e0e..3d96a4e0e 100755
--- a/top/u2_rev3_2rx_iad/u2_core.v
+++ b/usrp2/top/u2_rev3_2rx_iad/u2_core.v
diff --git a/top/u2_rev3_2rx_iad/wave.sh b/usrp2/top/u2_rev3_2rx_iad/wave.sh
index 626f224e5..626f224e5 100755
--- a/top/u2_rev3_2rx_iad/wave.sh
+++ b/usrp2/top/u2_rev3_2rx_iad/wave.sh
diff --git a/top/u2_rev3_iad/.gitignore b/usrp2/top/u2_rev3_iad/.gitignore
index e4daaf1ea..e4daaf1ea 100644
--- a/top/u2_rev3_iad/.gitignore
+++ b/usrp2/top/u2_rev3_iad/.gitignore
diff --git a/top/u2_rev3_iad/Makefile b/usrp2/top/u2_rev3_iad/Makefile
index 5ae8846dd..5ae8846dd 100644
--- a/top/u2_rev3_iad/Makefile
+++ b/usrp2/top/u2_rev3_iad/Makefile
diff --git a/top/u2_rev3_iad/cmdfile b/usrp2/top/u2_rev3_iad/cmdfile
index 34373a676..34373a676 100644
--- a/top/u2_rev3_iad/cmdfile
+++ b/usrp2/top/u2_rev3_iad/cmdfile
diff --git a/top/u2_rev3_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_iad/dsp_core_rx.v
index 2882464ba..2882464ba 100644
--- a/top/u2_rev3_iad/dsp_core_rx.v
+++ b/usrp2/top/u2_rev3_iad/dsp_core_rx.v
diff --git a/top/u2_rev3_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_iad/dsp_core_tb.sav
index 17c90cdd7..17c90cdd7 100644
--- a/top/u2_rev3_iad/dsp_core_tb.sav
+++ b/usrp2/top/u2_rev3_iad/dsp_core_tb.sav
diff --git a/top/u2_rev3_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_iad/dsp_core_tb.v
index 4d5a5b537..4d5a5b537 100644
--- a/top/u2_rev3_iad/dsp_core_tb.v
+++ b/usrp2/top/u2_rev3_iad/dsp_core_tb.v
diff --git a/top/u2_rev3_iad/impulse.v b/usrp2/top/u2_rev3_iad/impulse.v
index 7f0cdc9be..7f0cdc9be 100644
--- a/top/u2_rev3_iad/impulse.v
+++ b/usrp2/top/u2_rev3_iad/impulse.v
diff --git a/top/u2_rev3_iad/wave.sh b/usrp2/top/u2_rev3_iad/wave.sh
index 626f224e5..626f224e5 100755
--- a/top/u2_rev3_iad/wave.sh
+++ b/usrp2/top/u2_rev3_iad/wave.sh
diff --git a/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index 091eb2005..091eb2005 100755
--- a/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
diff --git a/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index e95445867..e95445867 100644
--- a/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
diff --git a/usrp2/udp/add_onescomp.v b/usrp2/udp/add_onescomp.v
new file mode 100644
index 000000000..048842a86
--- /dev/null
+++ b/usrp2/udp/add_onescomp.v
@@ -0,0 +1,12 @@
+
+
+module add_onescomp
+  #(parameter WIDTH = 16)
+   (input [WIDTH-1:0] A,
+    input [WIDTH-1:0] B,
+    output [WIDTH-1:0] SUM);
+
+   wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
+   assign SUM  = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
+   
+endmodule // add_onescomp
diff --git a/usrp2/udp/fifo19_rxrealign.v b/usrp2/udp/fifo19_rxrealign.v
new file mode 100644
index 000000000..35ad90951
--- /dev/null
+++ b/usrp2/udp/fifo19_rxrealign.v
@@ -0,0 +1,42 @@
+
+
+//  Adds a junk line at the beginning of every packet, which the
+//   following stages should ignore.  This gives us proper alignment due
+//   to the 14 byte ethernet header
+
+// Bit 18 -- odd length
+// Bit 17 -- eof
+// Bit 16 -- sof
+// Bit 15:0 -- data
+
+module fifo19_rxrealign
+  (input clk, input reset, input clear,
+   input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+   output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+   
+   reg 	rxre_state;
+   localparam RXRE_DUMMY  = 0;
+   localparam RXRE_PKT 	  = 1;
+   
+   assign dataout[18] 	  = datain[18];
+   assign dataout[17] 	  = datain[17];
+   assign dataout[16] 	  = (rxre_state==RXRE_DUMMY) | (datain[17] & datain[16]);  // allows for passing error signal
+   assign dataout[15:0] = datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       rxre_state <= RXRE_DUMMY;
+     else if(src_rdy_i & dst_rdy_i)
+       case(rxre_state)
+	 RXRE_DUMMY :
+	   rxre_state <= RXRE_PKT;
+	 RXRE_PKT :
+	   if(datain[17])   // if eof or error
+	     rxre_state <= RXRE_DUMMY;
+       endcase // case (rxre_state)
+
+   assign src_rdy_o 	 = src_rdy_i & dst_rdy_i;   // Send anytime both sides are ready
+   assign dst_rdy_o = src_rdy_i & dst_rdy_i & (rxre_state == RXRE_PKT);  // Only consume after the dummy
+   
+endmodule // fifo19_rxrealign
+
diff --git a/usrp2/udp/prot_eng_rx.v b/usrp2/udp/prot_eng_rx.v
new file mode 100644
index 000000000..5df158b2b
--- /dev/null
+++ b/usrp2/udp/prot_eng_rx.v
@@ -0,0 +1,121 @@
+
+
+
+// Protocol Engine Receiver
+//  Checks each line (16 bits) against values in setting regs
+//  3 options for each line -- 
+//      Error if mismatch, Slowpath if mismatch, or ignore line
+//  The engine increases the length of each packet by 32 or 48 bits,
+//   bringing the total length to a multiple of 32 bits.  The last line
+//   is entirely new, and contains the results of the matching operation:
+//      16 bits of flags, 16 bits of data.  Flags indicate error or slowpath
+//      Data indicates line that caused mismatch if any.
+
+
+//   Flags[2:0] is {occ, eop, sop}
+//   Protocol word format is:
+//             22   Last Header Line
+//             21   SLOWPATH if mismatch
+//             20   ERROR if mismatch
+//             19   This is the IP checksum
+//             18   This is the UDP checksum
+//             17   Compute IP checksum on this word
+//             16   Compute UDP checksum on this word
+//           15:0   data word to be matched
+
+module prot_eng_rx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   localparam HDR_WIDTH  = 16 + 7;  // 16 bits plus flags
+   localparam HDR_LEN 	 = 32;      // Up to 64 bytes of protocol
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
+   wire [HDR_WIDTH-1:0] header_word;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hE0) == BASE))
+       header_ram[set_addr[4:0]] <= set_data;
+
+   assign header_word 	= header_ram[state];
+
+   wire consume_input 	= src_rdy_i & dst_rdy_o;
+   wire produce_output 	= src_rdy_o & dst_rdy_i;
+   
+   // Main State Machine
+   reg [15:0] pkt_length, fail_word, dataout_int;
+   
+   reg slowpath, error, sof_o, eof_o, occ_o, odd;
+
+   assign dataout    = {occ_o, eof_o, sof_o, dataout_int};
+
+   wire [15:0] calc_ip_checksum, calc_udp_checksum;
+   reg [15:0] rx_ip_checksum, rx_udp_checksum;
+
+   always @(posedge clk) 
+     if(header_word[19]) 
+       rx_ip_checksum  <= datain[15:0];
+   always @(posedge clk) 
+     if(header_word[18]) 
+       rx_udp_checksum <= datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  slowpath     <= 0;
+	  error        <= 0;
+	  state        <= 0;
+	  fail_word    <= 0;
+	  eof_o        <= 0;
+	  occ_o        <= 0;
+       end
+     else if(src_rdy_i & dst_rdy_i)
+       case (state)
+	 0 :
+	   begin
+	      slowpath 	   <= 0;
+	      error 	   <= 0;
+	      eof_o 	   <= 0;
+	      occ_o 	   <= 0;
+	      state 	   <= 1;
+	   end
+
+	 ST_SLOWPATH :
+	   ;
+	 ST_ERROR :
+	   ;
+	 ST_PAYLOAD :
+	   ;
+	 ST_FILLER :
+	   ;
+	 ST_END1 :
+	   ;
+	 ST_END2 :
+	   ;
+	 default :
+	   if(header_word[21] && mismatch)
+	     state <= ST_SLOWPATH;
+	   else if(header_word[20] && mismatch)
+	     state <= ST_ERROR;
+	   else if(header_word[22])
+	     state <= ST_PAYLOAD;
+	   else
+	     state <= state + 1;
+       endcase // case (state)
+   
+
+
+   // IP + UDP checksum state machines
+   checksum_sm ip_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum));
+   
+   checksum_sm udp_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum));
+   
+endmodule // prot_eng_rx
diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v
new file mode 100644
index 000000000..9031011f7
--- /dev/null
+++ b/usrp2/udp/prot_eng_tx.v
@@ -0,0 +1,119 @@
+
+// The input FIFO contents should be 16 bits wide
+//   The first word is 1 for fast path (accelerated protocol)
+//                     0 for software implemented protocol
+//   The second word is the number of bytes in the packet, 
+//         and must be valid even if we are in slow path mode
+//            Odd means the last word is half full
+//   Flags[1:0] is {eop, sop}
+//   Protocol word format is:
+//             19   Last Header Line
+//             18   IP Header Checksum XOR
+//             17   IP Length Here
+//             16   UDP Length Here
+//           15:0   data word to be sent
+
+module prot_eng_tx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   wire [2:0] flags_i = datain[18:16];
+   reg [15:0] dataout_int;
+   reg fast_path, sof_o;
+   
+   wire [2:0] flags_o 	 = {flags_i[2], flags_i[1], sof_o};  // OCC, EOF, SOF
+
+   assign dataout 	 = {flags_o[2:0], dataout_int[15:0]};
+
+   reg [4:0] state;
+   wire do_payload 	 = (state == 31);
+   
+   assign dst_rdy_o 	 = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30));
+   assign src_rdy_o 	 = src_rdy_i & ~((state==0) | (state==1) | (state==30));
+   
+   localparam HDR_WIDTH  = 16 + 4;  // 16 bits plus flags
+   localparam HDR_LEN 	 = 32;      // Up to 64 bytes of protocol
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
+   wire [HDR_WIDTH-1:0] header_word;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hE0) == BASE))
+       header_ram[set_addr[4:0]] <= set_data;
+
+   assign header_word = header_ram[state];
+
+   wire last_hdr_line  = header_word[19];
+   wire ip_chk 	       = header_word[18];
+   wire ip_len 	       = header_word[17];
+   wire udp_len        = header_word[16];
+   
+   // Protocol State Machine
+   reg [15:0] length;
+   wire [15:0] ip_length = length + 28;  // IP HDR + UDP HDR
+   wire [15:0] udp_length = length + 8;  //  UDP HDR
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  state     <= 0;
+	  fast_path <= 0;
+	  sof_o   <= 0;
+       end
+     else
+       if(src_rdy_i & dst_rdy_i)
+	 case(state)
+	   0 :
+	     begin
+		fast_path <= datain[0];
+		state <= 1;
+	     end
+	   1 :
+	     begin
+		length 	<= datain[15:0];
+		sof_o <= 1;
+		if(fast_path)
+		  state <= 2;
+		else
+		  state <= 30;  // Skip 1 word for alignment
+	     end
+	   30 :
+	     state <= 31;
+	   31 :
+	     begin
+		sof_o <= 0;
+		if(flags_i[1]) // eop
+		  state <= 0;
+	     end
+	   default :
+	     begin
+		sof_o 	<= 0;
+		if(~last_hdr_line)
+		  state <= state + 1;
+		else
+		  state <= 31;
+	     end
+	 endcase // case (state)
+
+   wire [15:0] checksum;
+   add_onescomp #(.WIDTH(16)) add_onescomp 
+     (.A(header_word[15:0]),.B(ip_length),.SUM(checksum));
+
+   always @*
+     if(ip_chk)
+       //dataout_int 	<= header_word[15:0] ^ ip_length;
+       dataout_int 	<= 16'hFFFF ^ checksum;
+     else if(ip_len)
+       dataout_int 	<= ip_length;
+     else if(udp_len)
+       dataout_int 	<= udp_length;
+     else if(do_payload)
+       dataout_int 	<= datain[15:0];
+     else
+       dataout_int 	<= header_word[15:0];
+   
+endmodule // prot_eng_tx
diff --git a/usrp2/udp/prot_eng_tx_tb.v b/usrp2/udp/prot_eng_tx_tb.v
new file mode 100644
index 000000000..e7ffeb5e1
--- /dev/null
+++ b/usrp2/udp/prot_eng_tx_tb.v
@@ -0,0 +1,167 @@
+module prot_eng_tx_tb();
+
+   localparam BASE = 128;
+   reg clk    = 0;
+   reg rst    = 1;
+   reg clear  = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data;
+   reg [1:0] f36_occ;
+   reg f36_sof, f36_eof;
+   
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg src_rdy_f36i  = 0;
+   reg [15:0] count;
+
+   wire [35:0] casc_do;
+   wire [18:0] final_out, prot_out;
+
+   wire src_rdy_final, dst_rdy_final, src_rdy_prot;
+   reg dst_rdy_prot =0;
+   
+   wire dst_rdy_f36o ;
+   fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o));
+
+   fifo36_to_fifo19 fifo_converter
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f36_datain(casc_do),.f36_src_rdy_i(src_rdy_f36o),.f36_dst_rdy_o(dst_rdy_f36o),
+      .f19_dataout(final_out),.f19_src_rdy_o(src_rdy_final),.f19_dst_rdy_i(dst_rdy_final));
+
+   reg set_stb;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+	
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .datain(final_out[18:0]),.src_rdy_i(src_rdy_final),.dst_rdy_o(dst_rdy_final),
+      .dataout(prot_out[18:0]),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot));
+   
+   reg [35:0] printer;
+
+   task WriteSREG;
+      input [7:0] addr;
+      input [31:0] data;
+
+      begin
+	 @(posedge clk);
+	 set_addr <= addr;
+	 set_data <= data;
+	 set_stb  <= 1;
+	 @(posedge clk);
+	 set_stb <= 0;
+      end
+   endtask // WriteSREG
+   	
+   task ReadFromFIFO36;
+      begin
+	 $display("Read from FIFO36");
+	 #1 dst_rdy_prot <= 1;
+	 while(~src_rdy_prot)
+	   @(posedge clk);
+	 while(1)
+	   begin
+	      while(~src_rdy_prot)
+		@(posedge clk);
+	      $display("Read: %h",prot_out);
+	      @(posedge clk);
+	   end
+      end
+   endtask // ReadFromFIFO36
+   
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+	 count 	      <= 4;
+	 src_rdy_f36i <= 1;
+	 f36_data     <= 32'h0001_000c;
+	 f36_sof      <= 1;
+	 f36_eof      <= 0;
+	 f36_occ      <= 0;
+	
+	 $display("Put Packet in FIFO36");
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 $display("PPI_FIFO36: Entered First Line");
+	 f36_sof  <= 0;
+	 f36_data <= data_start;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 while(count+4 < data_len)
+	   begin
+	      f36_data <= f36_data + 32'h01010101;
+	      count    <= count + 4;
+	      while(~dst_rdy_f36i)
+		@(posedge clk);
+	      @(posedge clk);
+	      $display("PPI_FIFO36: Entered New Line");
+	   end
+	 f36_data  <= f36_data + 32'h01010101;
+	 f36_eof   <= 1;
+	 if(count + 4 == data_len)
+	   f36_occ <= 0;
+	 else if(count + 3 == data_len)
+	   f36_occ <= 3;
+	 else if(count + 2 == data_len)
+	   f36_occ <= 2;
+	 else
+	   f36_occ <= 1;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 f36_occ      <= 0;
+	 f36_eof      <= 0;
+	 f36_data     <= 0;
+	 src_rdy_f36i <= 0;
+	 $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("prot_eng_tx_tb.vcd");
+   initial $dumpvars(0,prot_eng_tx_tb);
+
+   initial
+     begin
+	#10000;
+	@(posedge clk);
+	ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	WriteSREG(BASE, {12'b0, 4'h0, 16'h0000});
+	WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000});
+	WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234});
+	WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678});
+	WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD});
+	@(posedge clk);
+	PutPacketInFIFO36(32'hA0B0C0D0,16);
+	@(posedge clk);
+	@(posedge clk);
+	#10000;
+	@(posedge clk);
+	PutPacketInFIFO36(32'hE0F0A0B0,36);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // prot_eng_tx_tb
diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v
new file mode 100644
index 000000000..390abd0d5
--- /dev/null
+++ b/usrp2/udp/udp_wrapper.v
@@ -0,0 +1,92 @@
+
+module udp_wrapper
+  #(parameter BASE=0,
+    parameter RXFIFOSIZE=11)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o,
+    output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i,
+    
+    output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i,
+    input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o,
+    output [31:0] debug
+    );
+
+   wire 	 tx_int1_src_rdy, tx_int1_dst_rdy;
+   wire [18:0] 	 tx_int1_data;
+   
+   wire 	 tx_int2_src_rdy, tx_int2_dst_rdy;
+   wire [18:0] 	 tx_int2_data;
+   wire [31:0] 	 debug_state;
+   
+   // TX side
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o),
+      .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) );
+
+   fifo_short #(.WIDTH(19)) shortfifo19_a
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy),
+      .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy),
+      .space(), .occupied() );
+     
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy),
+      .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) );
+
+   // RX side
+   wire rx_int1_src_rdy, rx_int1_dst_rdy;
+   wire [18:0] rx_int1_data;
+      
+   wire rx_int2_src_rdy, rx_int2_dst_rdy;
+   wire [18:0] rx_int2_data;
+      
+   wire rx_int3_src_rdy, rx_int3_dst_rdy;
+   wire [35:0] rx_int3_data;
+   
+`ifdef USE_PROT_ENG
+   prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`else
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`endif // !`ifdef USE_PROT_ENG
+   
+   fifo_short #(.WIDTH(19)) shortfifo19_b
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy),
+      .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy),
+      .space(), .occupied() );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy),
+      .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy),
+      .debug(debug_state));
+   
+   fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
+      .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i),
+      .space(), .occupied() );
+
+   /*
+   assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i },
+		    { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy},
+		    { rx_int3_data[35:32], rx_f36_data[35:32] },
+		    { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } };
+    */
+
+   assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] },
+		    { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] },
+		    { tx_int2_data[15:8] },
+		    { tx_int2_data[7:0] } };
+   
+endmodule // udp_wrapper
diff --git a/vrt/.gitignore b/usrp2/vrt/.gitignore
index 446b2daae..446b2daae 100644
--- a/vrt/.gitignore
+++ b/usrp2/vrt/.gitignore
diff --git a/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build
index f6d2d75a3..f6d2d75a3 100755
--- a/vrt/vita_rx.build
+++ b/usrp2/vrt/vita_rx.build
diff --git a/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v
index 2e96e6d42..2e96e6d42 100644
--- a/vrt/vita_rx_control.v
+++ b/usrp2/vrt/vita_rx_control.v
diff --git a/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index d3ff98df7..d3ff98df7 100644
--- a/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
diff --git a/vrt/vita_rx_tb.v b/usrp2/vrt/vita_rx_tb.v
index b4fda9622..b4fda9622 100644
--- a/vrt/vita_rx_tb.v
+++ b/usrp2/vrt/vita_rx_tb.v
diff --git a/vrt/vita_tx.build b/usrp2/vrt/vita_tx.build
index 902929c08..902929c08 100755
--- a/vrt/vita_tx.build
+++ b/usrp2/vrt/vita_tx.build
diff --git a/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index bffc64e52..bffc64e52 100644
--- a/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
diff --git a/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 49428ead5..49428ead5 100644
--- a/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
diff --git a/vrt/vita_tx_tb.v b/usrp2/vrt/vita_tx_tb.v
index 90986a35f..90986a35f 100644
--- a/vrt/vita_tx_tb.v
+++ b/usrp2/vrt/vita_tx_tb.v