diff options
| -rw-r--r-- | usrp2/control_lib/Makefile.srcs | 3 | ||||
| -rw-r--r-- | usrp2/control_lib/user_settings.v | 63 | ||||
| -rw-r--r-- | usrp2/sdr_lib/ddc_chain.v | 2 | ||||
| -rw-r--r-- | usrp2/sdr_lib/duc_chain.v | 2 | ||||
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 52 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 50 | ||||
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v | 72 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 53 | ||||
| -rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 10 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 2 |
10 files changed, 203 insertions, 106 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs index 567feacde..6ee7ea262 100644 --- a/usrp2/control_lib/Makefile.srcs +++ b/usrp2/control_lib/Makefile.srcs @@ -1,5 +1,5 @@ # -# Copyright 2010 Ettus Research LLC +# Copyright 2010-2012 Ettus Research LLC # ################################################## @@ -54,4 +54,5 @@ settings_bus_16LE.v \ atr_controller16.v \ fifo_to_wb.v \ gpio_atr.v \ +user_settings.v \ )) diff --git a/usrp2/control_lib/user_settings.v b/usrp2/control_lib/user_settings.v new file mode 100644 index 000000000..96ee22427 --- /dev/null +++ b/usrp2/control_lib/user_settings.v @@ -0,0 +1,63 @@ +// +// Copyright 2011 Corgan Enterprises LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +// User settings bus +// +// Provides 8-bit address, 32-bit data write only bus for user settings, consumes to addresses in +// normal settings bus. +// +// Write user address to BASE +// Write user data to BASE+1 +// +// The user_set_stb will strobe after data write, must write new address even if same as previous one. + +module user_settings + #(parameter BASE=0) + (input clk, + input rst, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + output set_stb_user, + output [7:0] set_addr_user, + output [31:0] set_data_user + ); + + wire addr_changed, data_changed; + reg stb_int; + + setting_reg #(.my_addr(BASE+0),.width(8)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(set_addr_user),.changed(addr_changed) ); + + setting_reg #(.my_addr(BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(set_data_user),.changed(data_changed) ); + + always @(posedge clk) + if (rst|set_stb_user) + stb_int <= 0; + else + if (addr_changed) + stb_int <= 1; + + assign set_stb_user = stb_int & data_changed; + +endmodule // user_settings + diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v index 647ec212b..02544a0fe 100644 --- a/usrp2/sdr_lib/ddc_chain.v +++ b/usrp2/sdr_lib/ddc_chain.v @@ -18,7 +18,7 @@ //! The USRP digital down-conversion chain module ddc_chain - #(parameter BASE = 0, parameter DSPNO = 0) + #(parameter BASE = 0) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v index f1c32a1b2..0d3ca258f 100644 --- a/usrp2/sdr_lib/duc_chain.v +++ b/usrp2/sdr_lib/duc_chain.v @@ -18,7 +18,7 @@ //! The USRP digital up-conversion chain module duc_chain - #(parameter BASE = 0, parameter DSPNO = 0) + #(parameter BASE = 0) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 0a03517b6..64c8defb3 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -1,5 +1,5 @@ // -// Copyright 2011 Ettus Research LLC +// Copyright 2011-2012 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -55,6 +55,7 @@ module u1plus_core localparam SR_CLEAR_RX_FIFO = 61; // 1 reg localparam SR_CLEAR_TX_FIFO = 62; // 1 reg localparam SR_GLOBAL_RESET = 63; // 1 reg + localparam SR_USER_REGS = 64; // 2 regs localparam SR_GPIO = 128; // 5 regs @@ -64,11 +65,11 @@ module u1plus_core wire pps_int; wire [63:0] vita_time, vita_time_pps; reg [15:0] reg_cgen_ctrl, reg_test; - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - + + wire [7:0] set_addr, set_addr_user; + wire [31:0] set_data, set_data_user; + wire set_stb, set_stb_user; + wire [31:0] debug0; wire [31:0] debug1; @@ -137,7 +138,7 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////// // RX ADC Frontend, does IQ Balance, DC Offset, muxing - wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p + wire [23:0] rx_fe_i, rx_fe_q; // 24 bits is total overkill here, but it matches u2/u2p wire run_rx0, run_rx1; rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend @@ -145,7 +146,7 @@ module u1plus_core .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_a({rx_i,4'b00}),.adc_ovf_a(0), .adc_b({rx_q,4'b00}),.adc_ovf_b(0), - .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug()); + .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug()); // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 @@ -158,12 +159,12 @@ module u1plus_core ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .debug() ); vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0 - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + (.clk(wb_clk),.reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp0), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), @@ -181,12 +182,12 @@ module u1plus_core ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .debug() ); vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1 - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + (.clk(wb_clk),.reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp1), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), @@ -205,10 +206,12 @@ module u1plus_core // /////////////////////////////////////////////////////////////////////////////////// // DSP TX - wire [23:0] tx_i_int, tx_q_int; wire run_tx; - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + wire [23:0] tx_fe_i, tx_fe_q; + wire [31:0] sample_tx; + wire strobe_tx; + + vita_tx_chain #(.BASE(SR_TX_CTRL), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) @@ -218,14 +221,21 @@ module u1plus_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .tx_i(tx_i_int),.tx_q(tx_q_int), - .underrun(tx_underrun_dsp), .run(run_tx), + .sample(sample_tx), .strobe(strobe_tx), + .underrun(underrun), .run(run_tx), .debug(debug_vt)); + duc_chain #(.BASE(SR_TX_DSP)) duc_chain + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug() ); + tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1), + .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), .dac_a(tx_i), .dac_b(tx_q)); // ///////////////////////////////////////////////////////////////////////////////////// @@ -387,6 +397,12 @@ module u1plus_core .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); + user_settings #(.BASE(SR_USER_REGS)) user_settings + (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb), + .set_addr(set_addr),.set_data(set_data), + .set_addr_user(set_addr_user),.set_data_user(set_data_user), + .set_stb_user(set_stb_user) ); + // ///////////////////////////////////////////////////////////////////////// // Readback mux 32 -- Slave #7 diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index b581ed50a..2c3690b0a 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -1,5 +1,5 @@ // -// Copyright 2011 Ettus Research LLC +// Copyright 2011-2012 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -59,6 +59,7 @@ module u1e_core localparam SR_CLEAR_RX_FIFO = 61; // 1 reg localparam SR_CLEAR_TX_FIFO = 62; // 1 reg localparam SR_GLOBAL_RESET = 63; // 1 reg + localparam SR_USER_REGS = 64; // 2 regs localparam SR_GPIO = 128; // 5 regs @@ -70,10 +71,10 @@ module u1e_core reg [15:0] reg_cgen_ctrl, reg_test, xfer_rate; wire [7:0] test_rate; wire [3:0] test_ctrl; - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; + + wire [7:0] set_addr, set_addr_user; + wire [31:0] set_data, set_data_user; + wire set_stb, set_stb_user; wire [31:0] debug_vt; wire rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; @@ -142,7 +143,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // RX ADC Frontend, does IQ Balance, DC Offset, muxing - wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p + wire [23:0] rx_fe_i, rx_fe_q; // 24 bits is total overkill here, but it matches u2/u2p wire run_rx0, run_rx1; rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend @@ -150,7 +151,7 @@ module u1e_core .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_a({rx_i,4'b00}),.adc_ovf_a(0), .adc_b({rx_q,4'b00}),.adc_ovf_b(0), - .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug()); + .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug()); // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 @@ -163,12 +164,12 @@ module u1e_core ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .debug() ); vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0 - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + (.clk(wb_clk),.reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp0), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), @@ -186,12 +187,12 @@ module u1e_core ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .debug() ); vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1 - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + (.clk(wb_clk),.reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp1), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), @@ -210,10 +211,12 @@ module u1e_core // /////////////////////////////////////////////////////////////////////////////////// // DSP TX - wire [23:0] tx_i_int, tx_q_int; wire run_tx; - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + wire [23:0] tx_fe_i, tx_fe_q; + wire [31:0] sample_tx; + wire strobe_tx; + + vita_tx_chain #(.BASE(SR_TX_CTRL), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) @@ -223,14 +226,21 @@ module u1e_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .tx_i(tx_i_int),.tx_q(tx_q_int), - .underrun(tx_underrun_dsp), .run(run_tx), + .sample(sample_tx), .strobe(strobe_tx), + .underrun(underrun), .run(run_tx), .debug(debug_vt)); + duc_chain #(.BASE(SR_TX_DSP)) duc_chain + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug() ); + tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1), + .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), .dac_a(tx_i), .dac_b(tx_q)); // ///////////////////////////////////////////////////////////////////////////////////// @@ -432,6 +442,12 @@ module u1e_core .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); + user_settings #(.BASE(SR_USER_REGS)) user_settings + (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb), + .set_addr(set_addr),.set_data(set_data), + .set_addr_user(set_addr_user),.set_data_user(set_data_user), + .set_stb_user(set_stb_user) ); + // ///////////////////////////////////////////////////////////////////////// // Readback mux 32 -- Slave #7 diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index f78d9013f..bd9cbf610 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -1,5 +1,5 @@ // -// Copyright 2011 Ettus Research LLC +// Copyright 2011-2012 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -152,7 +152,7 @@ module u2plus_core localparam SR_SIMTIMER = 8; // 2 localparam SR_TIME64 = 10; // 6 localparam SR_BUF_POOL = 16; // 4 - + localparam SR_USER_REGS = 20; // 2 localparam SR_RX_FRONT = 24; // 5 localparam SR_RX_CTRL0 = 32; // 9 localparam SR_RX_DSP0 = 48; // 7 @@ -174,11 +174,11 @@ module u2plus_core localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - + + wire [7:0] set_addr, set_addr_dsp, set_addr_user; + wire [31:0] set_data, set_data_dsp, set_data_user; + wire set_stb, set_stb_dsp, set_stb_user; + reg wb_rst; wire dsp_rst = wb_rst; @@ -478,7 +478,13 @@ module u2plus_core settings_bus_crossclock settings_bus_crossclock (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - + + user_settings #(.BASE(SR_USER_REGS)) user_settings + (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp), + .set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_addr_user(set_addr_user),.set_data_user(set_data_user), + .set_stb_user(set_stb_user) ); + // Output control lines wire [7:0] clock_outs, serdes_outs, adc_outs; assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; @@ -559,19 +565,19 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // ADC Frontend - wire [23:0] adc_i, adc_q; + wire [23:0] rx_fe_i, rx_fe_q; rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), - .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); + .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; - wire clear_rx0, strobe_rx0; + wire strobe_rx0; always @(posedge dsp_clk) run_rx0_d1 <= run_rx0; @@ -579,17 +585,12 @@ module u2plus_core ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); - setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx0)); - vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun0), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), @@ -599,7 +600,7 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // DSP RX 1 wire [31:0] sample_rx1; - wire clear_rx1, strobe_rx1; + wire strobe_rx1; always @(posedge dsp_clk) run_rx1_d1 <= run_rx1; @@ -607,17 +608,12 @@ module u2plus_core ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); - setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx1)); - vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun1), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), @@ -632,10 +628,6 @@ module u2plus_core wire [31:0] debug_vt; wire clear_tx; - setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp), - .in(set_data_dsp),.out(),.changed(clear_tx)); - assign RAM_A[20:18] = 3'b0; ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) @@ -661,9 +653,11 @@ module u2plus_core .debug(debug_extfifo), .debug2(debug_extfifo2) ); - wire [23:0] tx_i, tx_q; + wire [23:0] tx_fe_i, tx_fe_q; + wire [31:0] sample_tx; + wire strobe_tx; - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + vita_tx_chain #(.BASE(SR_TX_CTRL), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) @@ -673,16 +667,24 @@ module u2plus_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .tx_i(tx_i),.tx_q(tx_q), + .sample(sample_tx), .strobe(strobe_tx), .underrun(underrun), .run(run_tx), + .clear_vita(clear_tx), //output internal vita clear signal .debug(debug_vt)); + duc_chain #(.BASE(SR_TX_DSP)) duc_chain + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug() ); + tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .tx_i(tx_i), .tx_q(tx_q), .run(1'b1), + .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), .dac_a(dac_a), .dac_b(dac_b)); - + // /////////////////////////////////////////////////////////////////////////////////// // SERDES diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 2315b41c7..a83a68204 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -157,7 +157,7 @@ module u2_core localparam SR_SIMTIMER = 8; // 2 localparam SR_TIME64 = 10; // 6 localparam SR_BUF_POOL = 16; // 4 - + localparam SR_USER_REGS = 20; // 2 localparam SR_RX_FRONT = 24; // 5 localparam SR_RX_CTRL0 = 32; // 9 localparam SR_RX_DSP0 = 48; // 7 @@ -179,11 +179,11 @@ module u2_core localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - + + wire [7:0] set_addr, set_addr_dsp, set_addr_user; + wire [31:0] set_data, set_data_dsp, set_data_user; + wire set_stb, set_stb_dsp, set_stb_user; + wire ram_loader_done, ram_loader_rst; wire wb_rst; wire dsp_rst = wb_rst; @@ -441,7 +441,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd8, 16'd2}; //major, minor + localparam compat_num = {16'd8, 16'd3}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -484,7 +484,13 @@ module u2_core settings_bus_crossclock settings_bus_crossclock (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - + + user_settings #(.BASE(SR_USER_REGS)) user_settings + (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp), + .set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_addr_user(set_addr_user),.set_data_user(set_data_user), + .set_stb_user(set_stb_user) ); + // Output control lines wire [7:0] clock_outs, serdes_outs, adc_outs; assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; @@ -559,25 +565,20 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; - wire clear_rx0, strobe_rx0; + wire strobe_rx0; always @(posedge dsp_clk) run_rx0_d1 <= run_rx0; - ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0 + ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); - setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx0)); - vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun0), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), @@ -587,25 +588,20 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // DSP RX 1 wire [31:0] sample_rx1; - wire clear_rx1, strobe_rx1; + wire strobe_rx1; always @(posedge dsp_clk) run_rx1_d1 <= run_rx1; - ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1 + ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); - setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx1)); - vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun1), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), @@ -620,10 +616,6 @@ module u2_core wire [31:0] debug_vt; wire clear_tx; - setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx - (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp), - .in(set_data_dsp),.out(),.changed(clear_tx)); - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) ext_fifo_i1 (.int_clk(dsp_clk), @@ -663,9 +655,10 @@ module u2_core .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .sample(sample_tx), .strobe(strobe_tx), .underrun(underrun), .run(run_tx), + .clear_vita(clear_tx), //output internal vita clear signal .debug(debug_vt)); - duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain + duc_chain #(.BASE(SR_TX_DSP)) duc_chain (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), @@ -677,7 +670,7 @@ module u2_core .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), .dac_a(dac_a), .dac_b(dac_b)); - + // /////////////////////////////////////////////////////////////////////////////////// // SERDES diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index 13defdbc6..150da31c9 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -21,7 +21,7 @@ module vita_rx_chain parameter UNIT=0, parameter FIFOSIZE=10, parameter PROT_ENG_FLAGS=1) - (input clk, input reset, input clear, + (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, input [31:0] sample, input strobe, @@ -35,7 +35,13 @@ module vita_rx_chain wire [35:0] rx_data_int; wire rx_src_rdy_int, rx_dst_rdy_int; - + + wire clear; + + setting_reg #(.my_addr(BASE+3)) sr + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear)); + vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 1db16de63..07e143f19 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -30,6 +30,7 @@ module vita_tx_chain output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, output [31:0] sample, input strobe, output underrun, output run, + output clear_vita, output [31:0] debug); localparam MAXCHAN = 1; @@ -37,7 +38,6 @@ module vita_tx_chain wire [FIFOWIDTH-1:0] tx1_data; wire tx1_src_rdy, tx1_dst_rdy; - wire clear_vita; wire [31:0] streamid, message; wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; |