diff options
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_rx_tb.v | 14 | ||||
| -rw-r--r-- | usrp2/sdr_lib/hb_dec.v | 11 |
2 files changed, 19 insertions, 6 deletions
diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v index 67a558d55..0f36f1462 100644 --- a/usrp2/sdr_lib/dsp_core_rx_tb.v +++ b/usrp2/sdr_lib/dsp_core_rx_tb.v @@ -36,7 +36,7 @@ module dsp_core_rx_tb(); (.clk(clk),.rst(rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_i(adc_in), .adc_ovf_i(0), - .adc_q(0), .adc_ovf_q(0), + .adc_q(adc_in), .adc_ovf_q(0), .sample({adc_out_i,adc_out_q}), .run(run), .strobe(), .debug()); @@ -53,16 +53,26 @@ module dsp_core_rx_tb(); set_data <= {16'd0,8'd3,8'd1}; // set decim set_stb <= 1; @(posedge clk); + set_addr <= 0; + //set_data <= {32'h000F_7FF9}; + set_data <= {32'h01CA_C083}; // 700 kHz + set_stb <= 1; + @(posedge clk); set_stb <= 0; @(posedge clk); run <= 1; end + + always @(posedge clk) + //adc_in <= 18'h1FFFF; + adc_in <= 18'h20000; + /* always @(posedge clk) if(rst) adc_in <= 0; else adc_in <= adc_in + 4; //adc_in <= (($random % 473) + 23)/4; - +*/ endmodule // dsp_core_rx_tb diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v index f4e09091f..562e85b6b 100644 --- a/usrp2/sdr_lib/hb_dec.v +++ b/usrp2/sdr_lib/hb_dec.v @@ -95,7 +95,8 @@ module hb_dec // Data wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d; wire [IWIDTH-1:0] sum1, sum2; - wire [OWIDTH-1:0] final_sum; + wire [OWIDTH:0] final_sum; + wire [OWIDTH-1:0] final_sum_clip; reg [CWIDTH-1:0] coeff1, coeff2; wire [35:0] prod1, prod2; @@ -170,11 +171,13 @@ module hb_dec wire [OWIDTH-1:0] bypass_data; wire stb_final, stb_bypass; - round_sd #(.WIDTH_IN(ACCWIDTH-4),.WIDTH_OUT(OWIDTH)) + round_sd #(.WIDTH_IN(ACCWIDTH-3),.WIDTH_OUT(OWIDTH+1)) final_round (.clk(clk),.reset(rst), - .in(final_sum_unrounded[ACCWIDTH-5:0]),.strobe_in(stb_out_pre[8]), + .in(final_sum_unrounded[ACCWIDTH-4:0]),.strobe_in(stb_out_pre[8]), .out(final_sum), .strobe_out(stb_final)); + clip #(.bits_in(OWIDTH+1), .bits_out(OWIDTH)) clip (.in(final_sum), .out(final_sum_clip)); + round_sd #(.WIDTH_IN(IWIDTH),.WIDTH_OUT(OWIDTH)) bypass_round (.clk(clk),.reset(rst), .in(data_in),.strobe_in(stb_in), @@ -184,7 +187,7 @@ module hb_dec always @(posedge clk) begin stb_out <= bypass ? stb_bypass : stb_final; - data_out <= bypass ? bypass_data : final_sum; + data_out <= bypass ? bypass_data : final_sum_clip; end endmodule // hb_dec |