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-rw-r--r--usrp2/gpif/slave_fifo.v6
-rw-r--r--usrp2/top/B100/u1plus_core.v4
2 files changed, 5 insertions, 5 deletions
diff --git a/usrp2/gpif/slave_fifo.v b/usrp2/gpif/slave_fifo.v
index faba2b107..c1a51b008 100644
--- a/usrp2/gpif/slave_fifo.v
+++ b/usrp2/gpif/slave_fifo.v
@@ -20,7 +20,7 @@
//this is a FIFO master interface for the FX2 in "slave fifo" mode.
module slave_fifo
- #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+ #(parameter TXFIFOSIZE = 12, parameter RXFIFOSIZE = 12)
(// GPIF signals
input gpif_clk, input gpif_rst,
inout [15:0] gpif_d,
@@ -243,7 +243,7 @@ module slave_fifo
else
data_tx_dst_rdy <= wr_fifo_space >= 256;
- fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo
+ fifo_cascade #(.WIDTH(18), .SIZE(12)) wr_fifo
(.clk(gpif_clk), .reset(gpif_rst), .clear(0),
.datain({eop,sop,gpif_d}), .src_rdy_i(data_tx_src_rdy), .dst_rdy_o(/*data_tx_dst_rdy*/), .space(wr_fifo_space),
.dataout(data_tx_int), .src_rdy_o(tx_src_rdy_int), .dst_rdy_i(tx_dst_rdy_int), .occupied());
@@ -308,7 +308,7 @@ module slave_fifo
.arst(fifo_rst));
//rd_fifo buffers writes to the 2clock fifo above
- fifo_cascade #(.WIDTH(19), .SIZE(12)) rd_fifo
+ fifo_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rd_fifo
(.clk(~gpif_clk), .reset(gpif_rst), .clear(0),
.datain(data_rx_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .space(rxfifospace),
.dataout(gpif_d_out_data), .src_rdy_o(data_rx_src_rdy), .dst_rdy_i(data_rx_dst_rdy), .occupied());
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 88fec3d99..a7b6e677e 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -37,8 +37,8 @@ module u1plus_core
input pps_in
);
- localparam TXFIFOSIZE = 11;
- localparam RXFIFOSIZE = 11;
+ localparam TXFIFOSIZE = 12;
+ localparam RXFIFOSIZE = 12;
// 64 total regs in address space
localparam SR_RX_CTRL0 = 0; // 9 regs (+0 to +8)