diff options
| -rw-r--r-- | usrp2/simple_gemac/ethtx_realign.v | 52 | ||||
| -rw-r--r-- | usrp2/simple_gemac/simple_gemac_wrapper.v | 2 |
2 files changed, 28 insertions, 26 deletions
diff --git a/usrp2/simple_gemac/ethtx_realign.v b/usrp2/simple_gemac/ethtx_realign.v index 74a1ef46b..be53abf4c 100644 --- a/usrp2/simple_gemac/ethtx_realign.v +++ b/usrp2/simple_gemac/ethtx_realign.v @@ -1,5 +1,10 @@ -// NOTE: Will not work with single-line frames +//////////////////////////////////////////////////////////////////////// +// Ethernet TX - Realign +// +// - removes a 2-byte pad from the front a fifo36 stream +// - occupancy is preserved +// module ethtx_realign (input clk, input reset, input clear, @@ -17,9 +22,8 @@ module ethtx_realign wire sof_in = datain[32]; wire eof_in = datain[33]; wire [1:0] occ_in = datain[35:34]; - wire sof_out, eof_out; - wire [1:0] occ_out; - + wire occ_low = occ_in[1] ^ occ_in[0]; //occ is 1 or 2 + always @(posedge clk) if(reset | clear) begin @@ -30,8 +34,8 @@ module ethtx_realign else if(xfer_in) begin held <= datain[15:0]; - held_occ <= datain[35:34]; - held_sof <= datain[32]; + held_occ <= occ_in; + held_sof <= sof_in; end localparam RE_IDLE = 0; @@ -44,32 +48,30 @@ module ethtx_realign else case(state) RE_IDLE : - if(src_rdy_i & dst_rdy_i) - if(eof_in) - state <= RE_DONE; - else - state <= RE_HELD; + if(xfer_in & eof_in) + state <= RE_DONE; + else if(xfer_in & sof_in) + state <= RE_HELD; RE_HELD : - if(src_rdy_i & dst_rdy_i & eof_in) - if((occ_in==0)|(occ_in==3)) - state <= RE_DONE; - else + if(xfer_in & xfer_out & eof_in) + if(occ_low) state <= RE_IDLE; + else + state <= RE_DONE; RE_DONE : - if(dst_rdy_i) + if(xfer_out) state <= RE_IDLE; endcase // case (state) - - - assign sof_out = held_sof; - assign eof_out = (state == RE_DONE) | (occ_in == 1) | (occ_in == 2); - assign occ_out = (state == RE_DONE) ? ((held_occ == 3) ? 1 : 2) : - (occ_in == 1) ? 3 : 0; - + + wire sof_out = held_sof; + wire eof_out = (state == RE_HELD)? (eof_in & occ_low) : (state == RE_DONE); + wire [1:0] occ_out = ((state == RE_DONE)? held_occ : occ_in) ^ 2'b10; //(occ + 2)%4 + assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; - assign src_rdy_o = (state == RE_DONE) | ((state == RE_HELD) & src_rdy_i); - assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD)); + assign src_rdy_o = (state == RE_HELD)? src_rdy_i : (state == RE_DONE); + assign dst_rdy_o = (state == RE_HELD)? dst_rdy_i : (state == RE_IDLE); + endmodule // ethtx_realign diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v index 08a3c9894..8390eb2c6 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -115,7 +115,7 @@ module simple_gemac_wrapper .arst(reset)); ethtx_realign ethtx_realign - (.clk(rx_clk), .reset(tx_reset), .clear(clear), + (.clk(tx_clk), .reset(tx_reset), .clear(clear), .datain(tx_f36_data_int1), .src_rdy_i(tx_f36_src_rdy_int1), .dst_rdy_o(tx_f36_dst_rdy_int1), .dataout(tx_f36_data_int2), .src_rdy_o(tx_f36_src_rdy_int2), .dst_rdy_i(tx_f36_dst_rdy_int2) ); |