diff options
| -rw-r--r-- | fpga/usrp2/gpmc/fifo_to_gpmc.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/gpmc/gpmc_to_fifo.v | 2 | ||||
| -rwxr-xr-x | fpga/usrp2/top/E1x0/core_compile | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/timing.ucf | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc.v b/fpga/usrp2/gpmc/fifo_to_gpmc.v index 27252b970..26443a702 100644 --- a/fpga/usrp2/gpmc/fifo_to_gpmc.v +++ b/fpga/usrp2/gpmc/fifo_to_gpmc.v @@ -82,7 +82,7 @@ module fifo_to_gpmc end GPMC_STATE_EMPTY: begin - if (EM_A == LAST_ADDR) begin + if (addr == LAST_ADDR) begin gpmc_state <= GPMC_STATE_START; gpmc_ptr <= next_gpmc_ptr; addr <= 0; diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo.v b/fpga/usrp2/gpmc/gpmc_to_fifo.v index 680095620..3932b81ac 100644 --- a/fpga/usrp2/gpmc/gpmc_to_fifo.v +++ b/fpga/usrp2/gpmc/gpmc_to_fifo.v @@ -75,7 +75,7 @@ module gpmc_to_fifo case(gpmc_state) GPMC_STATE_START: begin - if (EM_A == XFER_OFFSET) begin + if (data_i[16]) begin gpmc_state <= GPMC_STATE_FILL; vita_len <= EM_D; next_gpmc_ptr <= gpmc_ptr + 1; diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile index dd88094ff..ab992f29d 100755 --- a/fpga/usrp2/top/E1x0/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E1x0.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf index 6bd559426..7d3d9e090 100644 --- a/fpga/usrp2/top/E1x0/timing.ucf +++ b/fpga/usrp2/top/E1x0/timing.ucf @@ -14,7 +14,7 @@ INST "EM_NCS6" TNM = gpmc_net; INST "EM_NWE" TNM = gpmc_net; INST "EM_NOE" TNM = gpmc_net; -TIMEGRP "gpmc_net" OFFSET = IN 7 ns VALID 14 ns BEFORE "EM_CLK" FALLING; +TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 12 ns BEFORE "EM_CLK" FALLING; TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read #constrain interrupt lines |