fixed typo in u2_core.v resulting in unconnected net. added debug pins

2 files changed, 16 insertions, 3 deletions

diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v
index a887f056f..e53b968a5 100644
--- a/vrt/vita_tx_control.v
+++ b/vrt/vita_tx_control.v
@@ -16,9 +16,11 @@ module vita_tx_control
     // To DSP Core
     output [WIDTH-1:0] sample,
     output run,
-    input strobe
-    );
+    input strobe,
 
+    output [31:0] debug
+    );
+   
    assign sample = sample_fifo_i[4+64+WIDTH-1:4+64];
 
    wire [63:0] send_time = sample_fifo_i[63:0];
@@ -66,5 +68,10 @@ module vita_tx_control
    assign sample_fifo_dst_rdy_o = (strobe & (ibs_state == IBS_RUN));  // FIXME also cleanout
    assign run = (ibs_state == IBS_RUN);
    assign underrun = (ibs_state == IBS_UNDERRUN);
+
+   assign debug = { { now,early,late,too_early,eop,eob,sob,send_at },
+		    { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] },
+		    { 8'b0 },
+		    { 8'b0 } };
    
 endmodule // vita_tx_control
diff --git a/vrt/vita_tx_deframer.v b/vrt/vita_tx_deframer.v
index f6f9f3da8..470ba3f3e 100644
--- a/vrt/vita_tx_deframer.v
+++ b/vrt/vita_tx_deframer.v
@@ -17,7 +17,8 @@ module vita_tx_deframer
     // FIFO Levels
     output [15:0] fifo_occupied,
     output fifo_full,
-    output fifo_empty    
+    output fifo_empty,
+    output [31:0] debug
     );
 
    wire [1:0] numchan;
@@ -177,5 +178,10 @@ module vita_tx_deframer
    assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time};
 
    assign dst_rdy_o = (vita_state != VITA_PAYLOAD);
+
+   assign debug = { { 8'b0 },
+		    { 8'b0 },
+		    { eof, line_done, store, fifo_space, src_rdy_i, dst_rdy_o, vector_phase[1:0] },
+		    { has_secs_reg, is_sob_reg, is_eob_reg, eop, vita_state[3:0] } };
    
 endmodule // vita_tx_deframer