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authorMatt Ettus <matt@ettus.com>2010-01-19 18:08:37 -0800
committerMatt Ettus <matt@ettus.com>2010-01-19 18:08:37 -0800
commit8d19387a8642caf74179bdcb7eddf1936f473e53 (patch)
treeee987eb365e2fb8bd42032f59aeedbd0f4addf18 /vrt
parentcb3b628f8d096ab2a843a804189037c495532ac9 (diff)
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speed up timing by ignoring the too_early error. We'll need to FIXME this later
Diffstat (limited to 'vrt')
-rw-r--r--vrt/vita_tx_control.v7
1 files changed, 5 insertions, 2 deletions
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v
index 6776e26e5..bffc64e52 100644
--- a/vrt/vita_tx_control.v
+++ b/vrt/vita_tx_control.v
@@ -29,10 +29,13 @@ module vita_tx_control
wire sob = sample_fifo_i[66];
wire send_at = sample_fifo_i[67];
wire now, early, late, too_early;
-
+
+ // FIXME ignore too_early for now for timing reasons
+ assign too_early = 0;
time_compare
time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early),
- .late(late), .too_early(too_early));
+ .late(late), .too_early());
+// .late(late), .too_early(too_early));
localparam IBS_IDLE = 0;
localparam IBS_RUN = 1; // FIXME do we need this?