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| author | Matt Ettus <matt@ettus.com> | 2009-12-11 17:53:10 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-11 17:53:10 -0800 |
| commit | 42d8dc7e476be7da305f7718f20b3758ddd4313a (patch) | |
| tree | 3459f59cb0f777dac908e844927d80411a361434 /vrt/vita_tx_control.v | |
| parent | e252b782f39a78cb3472f014a6a81fe0a14bff8d (diff) | |
| download | uhd-42d8dc7e476be7da305f7718f20b3758ddd4313a.tar.gz uhd-42d8dc7e476be7da305f7718f20b3758ddd4313a.tar.bz2 uhd-42d8dc7e476be7da305f7718f20b3758ddd4313a.zip | |
fixed typo in u2_core.v resulting in unconnected net. added debug pins
Diffstat (limited to 'vrt/vita_tx_control.v')
| -rw-r--r-- | vrt/vita_tx_control.v | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v index a887f056f..e53b968a5 100644 --- a/vrt/vita_tx_control.v +++ b/vrt/vita_tx_control.v @@ -16,9 +16,11 @@ module vita_tx_control // To DSP Core output [WIDTH-1:0] sample, output run, - input strobe - ); + input strobe, + output [31:0] debug + ); + assign sample = sample_fifo_i[4+64+WIDTH-1:4+64]; wire [63:0] send_time = sample_fifo_i[63:0]; @@ -66,5 +68,10 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN); assign underrun = (ibs_state == IBS_UNDERRUN); + + assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, + { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] }, + { 8'b0 }, + { 8'b0 } }; endmodule // vita_tx_control |