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| author | Matt Ettus <matt@ettus.com> | 2009-12-11 18:38:47 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-11 18:38:47 -0800 |
| commit | f46cbe5ffabe8f439e3d86e52bdc3c25fb7bc084 (patch) | |
| tree | 9671696b3e80c6092504e50423e7873a10af4384 /vrt/vita_tx_control.v | |
| parent | f346a6137c48821be7f410e7d07a648b5c5e042e (diff) | |
| download | uhd-f46cbe5ffabe8f439e3d86e52bdc3c25fb7bc084.tar.gz uhd-f46cbe5ffabe8f439e3d86e52bdc3c25fb7bc084.tar.bz2 uhd-f46cbe5ffabe8f439e3d86e52bdc3c25fb7bc084.zip | |
reorder the memory map
Diffstat (limited to 'vrt/vita_tx_control.v')
| -rw-r--r-- | vrt/vita_tx_control.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v index 418bd1850..689acd708 100644 --- a/vrt/vita_tx_control.v +++ b/vrt/vita_tx_control.v @@ -42,7 +42,7 @@ module vita_tx_control reg [2:0] ibs_state; wire clear_state; - setting_reg #(.my_addr(BASE+3)) sr + setting_reg #(.my_addr(BASE+1)) sr (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_state)); |