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| author | Matt Ettus <matt@ettus.com> | 2009-12-11 18:27:14 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-11 18:27:14 -0800 |
| commit | 5f54616b4f8456a6dab879ebd8fc9bca287987b9 (patch) | |
| tree | 71855e87a822f009717db56a2e2a3b8fe4a02650 /vrt/vita_tx_control.v | |
| parent | 42d8dc7e476be7da305f7718f20b3758ddd4313a (diff) | |
| download | uhd-5f54616b4f8456a6dab879ebd8fc9bca287987b9.tar.gz uhd-5f54616b4f8456a6dab879ebd8fc9bca287987b9.tar.bz2 uhd-5f54616b4f8456a6dab879ebd8fc9bca287987b9.zip | |
Add ability to clear state out when there is an underrun
Diffstat (limited to 'vrt/vita_tx_control.v')
| -rw-r--r-- | vrt/vita_tx_control.v | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v index e53b968a5..2af68c073 100644 --- a/vrt/vita_tx_control.v +++ b/vrt/vita_tx_control.v @@ -40,9 +40,14 @@ module vita_tx_control localparam IBS_UNDERRUN = 3; reg [2:0] ibs_state; + + wire clear_state; + setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_state)); always @(posedge clk) - if(reset | clear) + if(reset | clear_state) ibs_state <= 0; else case(ibs_state) |