fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift

2 files changed, 25 insertions, 50 deletions

diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
index 51968d24a..5581b1dbd 100644
--- a/usrp2/top/u1e/u1e.ucf
+++ b/usrp2/top/u1e/u1e.ucf
@@ -95,10 +95,10 @@ NET "db_sen_tx"  LOC = "G18"  ;
 #NET "aux_sdi_codec"  LOC = "G3"  ;
 #NET "aux_sdo_codec"  LOC = "F3"  ;
 #NET "aux_sclk_codec"  LOC = "C1"  ;
-NET "sen_codec"  LOC = "F5"  ;
-NET "mosi_codec"  LOC = "F4"  ;
+NET "sen_codec"  LOC = "F5"  |IOSTANDARD = LVCMOS33;
+NET "mosi_codec"  LOC = "F4"  |IOSTANDARD = LVCMOS33;
 NET "miso_codec"  LOC = "H4"  ;
-NET "sclk_codec"  LOC = "H3"  ;
+NET "sclk_codec"  LOC = "H3"  |IOSTANDARD = LVCMOS33;
 
 ### Clock Gen SPI
 NET "cgen_miso"  LOC = "F22"  ;
@@ -184,22 +184,22 @@ NET "DA<2>"  LOC = "P6"  ;
 NET "DA<1>"  LOC = "R1"  ;
 NET "DA<0>"  LOC = "R2"  ;
 
-NET "TX<13>"  LOC = "T6"  ;
-NET "TX<12>"  LOC = "U1"  ;
-NET "TX<11>"  LOC = "T1"  ;
-NET "TX<10>"  LOC = "R5"  ;
-NET "TX<9>"  LOC = "V1"  ;
-NET "TX<8>"  LOC = "U2"  ;
-NET "TX<7>"  LOC = "T4"  ;
-NET "TX<6>"  LOC = "R3"  ;
-NET "TX<5>"  LOC = "W1"  ;
-NET "TX<4>"  LOC = "Y1"  ;
-NET "TX<3>"  LOC = "V3"  ;
-NET "TX<2>"  LOC = "V4"  ;
-NET "TX<1>"  LOC = "W2"  ;
-NET "TX<0>"  LOC = "W3"  ;
-NET "TXSYNC"  LOC = "U5"  ;
-NET "TXBLANK"  LOC = "U4"  ;
+NET "TX<13>"  LOC = "T6"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<12>"  LOC = "U1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<11>"  LOC = "T1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<10>"  LOC = "R5"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<9>"  LOC = "V1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<8>"  LOC = "U2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<7>"  LOC = "T4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<6>"  LOC = "R3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<5>"  LOC = "W1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<4>"  LOC = "Y1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<3>"  LOC = "V3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<2>"  LOC = "V4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<1>"  LOC = "W2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<0>"  LOC = "W3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXSYNC"  LOC = "U5"   |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXBLANK"  LOC = "U4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
 
 NET "PPS_IN"  LOC = "M5"  ;
 
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 7ddbfd537..ee087e59d 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -1,8 +1,6 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
-//`define DCM 1
-
 module u1e
   (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
    output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -41,11 +39,10 @@ module u1e
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
-`ifdef DCM
-   wire  clk_2x, dcm_rst, dcm_locked;
+   wire  clk_2x, dcm_rst, dcm_locked, clk_fb;
    DCM #(.CLK_FEEDBACK ( "1X" ),
-	 .CLKDV_DIVIDE ( 2.0 ),
-	 .CLKFX_DIVIDE ( 1 ),
+	 .CLKDV_DIVIDE ( 2 ),
+	 .CLKFX_DIVIDE ( 2 ),
 	 .CLKFX_MULTIPLY ( 2 ),
 	 .CLKIN_DIVIDE_BY_2 ( "FALSE" ),
 	 .CLKIN_PERIOD ( 15.625 ),
@@ -57,15 +54,12 @@ module u1e
 	 .FACTORY_JF ( 16'h8080 ),
 	 .PHASE_SHIFT ( 0 ),
 	 .STARTUP_WAIT ( "FALSE" ))
-   clk_doubler (.CLKFB(clk_fpga), .CLKIN(clk_fpga_in), .RST(dcm_rst), 
+   clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), 
                 .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), 
 		.CLKDV(), .CLKFX(), .CLKFX180(), 
-                .CLK2X(clk_2x), .CLK2X180(), 
-                .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), 
+                .CLK2X(), .CLK2X180(), 
+                .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), 
                 .LOCKED(dcm_locked), .STATUS());
-`else // !`ifdef DCM
-   BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
-`endif // !`ifdef DCM
    
    // /////////////////////////////////////////////////////////////////////////
    // SPI
@@ -83,23 +77,6 @@ module u1e
    assign TXBLANK = 0;
    wire [13:0] tx_i, tx_q;
 
-`ifdef DCM
-   reg [13:0]  TX;
-   reg 	       TXSYNC;
-   
-   always @(posedge clk_2x)
-     if(clk_fpga)
-       begin
-	  TX <= tx_i;
-	  TXSYNC <= 0;  // Low indicates first data item
-       end
-     else
-       begin
-	  TX <= tx_q;
-	  TXSYNC <= 1;
-       end
-`else // !`ifdef DCM
-   
    reg[13:0] delay_q;
    always @(posedge clk_fpga)
      delay_q <= tx_q;
@@ -133,8 +110,6 @@ module u1e
 		.R(1'b0),       // 1-bit reset input
 		.S(1'b0));      // 1-bit set input
    
-`endif // !`ifdef DCM
-   
    // /////////////////////////////////////////////////////////////////////////
    // Main U1E Core
    u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),