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| author | Matt Ettus <matt@ettus.com> | 2010-02-25 21:10:26 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-02-25 21:10:26 -0800 |
| commit | db60b00d7a1bafe4f3f49e1ec2367897fc8c71ab (patch) | |
| tree | 30bd70ce77b9b4710b0beeeaad64aff32adf0c2f /usrp2 | |
| parent | e775ce6c17d1e43865cdd3f9472157d0d2d26b92 (diff) | |
| download | uhd-db60b00d7a1bafe4f3f49e1ec2367897fc8c71ab.tar.gz uhd-db60b00d7a1bafe4f3f49e1ec2367897fc8c71ab.tar.bz2 uhd-db60b00d7a1bafe4f3f49e1ec2367897fc8c71ab.zip | |
enable was on the wrong address pin, needs to be the highest order one
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/control_lib/ram_2port_mixed_width.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index e84b0da02..fae7d8de3 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -15,8 +15,8 @@ module ram_2port_mixed_width wire en32a = en32 & ~addr32[9]; wire en32b = en32 & addr32[9]; - wire en16a = en16 & ~addr16[9]; - wire en16b = en16 & addr16[9]; + wire en16a = en16 & ~addr16[10]; + wire en16b = en16 & addr16[10]; wire [31:0] do32a, do32b; wire [15:0] do16a, do16b; |