dsp rework: implement 64 bit ticks no seconds

10 files changed, 57 insertions, 111 deletions

diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 03df07108..6f335890e 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
 
 
 module time_64bit
-  #(parameter TICKS_PER_SEC = 32'd100000000,
+  #(
     parameter BASE = 0)
    (input clk, input rst,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
@@ -31,23 +31,20 @@ module time_64bit
     output [31:0] debug
     );
    
-   localparam 	   NEXT_SECS = 0;   
-   localparam 	   NEXT_TICKS = 1;
+   localparam 	   NEXT_TICKS_HI = 0;
+   localparam 	   NEXT_TICKS_LO = 1;
    localparam      PPS_POLSRC = 2;
    localparam      PPS_IMM = 3;
-   localparam      TPS = 4;
    localparam      MIMO_SYNC = 5;
    
-   reg [31:0] 	   seconds, ticks;
-   wire 	   end_of_second;
+   reg [63:0] 	   ticks;
 
    always @(posedge clk)
-     vita_time <= {seconds,ticks};
+     vita_time <= ticks;
    
    wire [63:0] 	   vita_time_rcvd;
    
-   wire [31:0] 	   next_ticks_preset, next_seconds_preset;
-   wire [31:0] 	   ticks_per_sec_reg;
+   wire [63:0] 	   next_ticks_preset;
    wire 	   set_on_pps_trig;
    reg 		   set_on_next_pps;
    wire 	   pps_polarity, pps_source, set_imm;
@@ -57,18 +54,18 @@ module time_64bit
 
    reg [15:0] 	   sync_counter;
    wire 	   sync_rcvd;
-   wire [31:0] 	   mimo_secs, mimo_ticks;
+   wire [63:0] 	   mimo_ticks;
    wire 	   mimo_sync_now;
    wire 	   mimo_sync;
    wire [7:0] 	   sync_delay;
    
-   setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
+   setting_reg #(.my_addr(BASE+NEXT_TICKS_LO)) sr_next_ticks_lo
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(next_ticks_preset),.changed());
+      .in(set_data),.out(next_ticks_preset[31:0]),.changed());
    
-   setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs
+   setting_reg #(.my_addr(BASE+NEXT_TICKS_HI)) sr_next_ticks_hi
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
+      .in(set_data),.out(next_ticks_preset[63:32]),.changed(set_on_pps_trig));
 
    setting_reg #(.my_addr(BASE+PPS_POLSRC), .width(2)) sr_pps_polsrc
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -78,10 +75,6 @@ module time_64bit
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(set_imm),.changed());
 
-   setting_reg #(.my_addr(BASE+TPS), .at_reset(TICKS_PER_SEC)) sr_tps
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(ticks_per_sec_reg),.changed());
-
    setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({mimo_sync,sync_delay}),.changed());
@@ -110,29 +103,21 @@ module time_64bit
      else if(set_imm | pps_edge)
        set_on_next_pps <= 0;
 
-   wire [31:0] 	   ticks_plus_one = ticks + 1;
+   wire [63:0] 	   ticks_plus_one = ticks + 1;
    
    always @(posedge clk)
      if(rst)
        begin
-	  seconds <= 32'd0;
-	  ticks <= 32'd0;
+	  ticks <= 64'd0;
        end
      else if((set_imm | pps_edge) & set_on_next_pps)
        begin
-	  seconds <= next_seconds_preset;
 	  ticks <= next_ticks_preset;
        end
      else if(mimo_sync_now)
        begin
-	  seconds <= mimo_secs;
 	  ticks <= mimo_ticks;
        end
-     else if(ticks_plus_one == ticks_per_sec_reg)
-       begin
-	  seconds <= seconds + 1;
-	  ticks <= 0;
-       end
      else
        ticks <= ticks_plus_one;
 
@@ -162,9 +147,8 @@ module time_64bit
       .sync_rcvd(sync_rcvd),
       .exp_time_in(exp_time_in) );
 
-   assign mimo_secs = vita_time_rcvd[63:32];
-   assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay};
-   assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC);
+   assign mimo_ticks = vita_time_rcvd[63:0] + {48'd0,sync_delay};
+   assign mimo_sync_now = mimo_sync & sync_rcvd;
 
    assign debug = { { 24'b0} ,
 		    { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
diff --git a/usrp2/timing/time_compare.v b/usrp2/timing/time_compare.v
index 54ea000d6..21607f51c 100644
--- a/usrp2/timing/time_compare.v
+++ b/usrp2/timing/time_compare.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -16,49 +16,19 @@
 //
 
 
-// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second
+// 64 bits worth of ticks
 
 module time_compare
   (input [63:0] time_now,
    input [63:0] trigger_time,
    output now,
    output early,
-   output late, 
+   output late,
    output too_early);
-   
-   wire    sec_match   = (time_now[63:32] == trigger_time[63:32]);
-   wire    sec_late    = (time_now[63:32] > trigger_time[63:32]);
 
-   wire    tick_match  = (time_now[31:0] == trigger_time[31:0]);
-   wire    tick_late   = (time_now[31:0] > trigger_time[31:0]);
-/*   
-   assign now 	       = sec_match & tick_match;
-   assign late 	       = sec_late | (sec_match & tick_late);
-   assign early        = ~now & ~late;
-*/
+    assign now = time_now == trigger_time;
+    assign late = time_now > trigger_time;
+    assign early = ~now & ~late;
+    assign too_early = 0; //not implemented
 
-   /*
-   assign now = (time_now == trigger_time);
-   assign late = (time_now > trigger_time);
-   assign early = (time_now < trigger_time);
-   */
-
-   // Compare fewer bits instead of 64 to speed up logic
-   // Unused bits are not significant
-   //     Top bit of seconds would put us in year 2038, long after
-   //        the warranty has run out :)
-   //     Top 5 bits of ticks are always zero for clocks less than 134MHz
-   //     "late" can drop bottom few bits of ticks, and just delay signaling
-   //        of late.  
-   //     "now" cannot drop those bits, it needs to be exact.
-   
-   wire [57:0] short_now = {time_now[62:32],time_now[26:0]};
-   wire [57:0] short_trig = {trigger_time[62:32],trigger_time[26:0]};
-
-   assign now = (short_now == short_trig);
-   assign late = (short_now[57:5] > short_trig[57:5]);
-   assign early = (short_now < short_trig);
-   
-   assign too_early    = (trigger_time[63:32] > (time_now[63:32] + 4));  // Don't wait too long
-   
 endmodule // time_compare
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index c5fe368a5..e335fb8bb 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -438,7 +438,7 @@ module u1plus_core
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
-   time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit
+   time_64bit #(.BASE(SR_TIME64)) time_64bit
      (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
       .exp_time_in(0));
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 032c320e0..ee27af939 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -480,7 +480,7 @@ module u1e_core
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
-   time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit
+   time_64bit #(.BASE(SR_TIME64)) time_64bit
      (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
       .exp_time_in(0));
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index a0c2e7be6..378f212e4 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -709,7 +709,7 @@ module u2plus_core
 
    wire [31:0] 	 debug_sync;
 
-   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+   time_64bit #(.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
       .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
       .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync));
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 7461ded68..9b26b98e1 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -697,7 +697,7 @@ module u2_core
 
    wire [31:0] 	 debug_sync;
 
-   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+   time_64bit #(.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
       .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
       .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync));
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v
index bdfca8237..d6674e887 100644
--- a/usrp2/vrt/gen_context_pkt.v
+++ b/usrp2/vrt/gen_context_pkt.v
@@ -32,12 +32,11 @@ module gen_context_pkt
    localparam CTXT_PROT_ENG = 1;
    localparam CTXT_HEADER = 2;
    localparam CTXT_STREAMID = 3;
-   localparam CTXT_SECS = 4;
-   localparam CTXT_TICS = 5;
-   localparam CTXT_TICS2 = 6;
-   localparam CTXT_MESSAGE = 7;
-   localparam CTXT_FLOWCTRL = 8;
-   localparam CTXT_DONE = 9;
+   localparam CTXT_TICS = 4;
+   localparam CTXT_TICS2 = 5;
+   localparam CTXT_MESSAGE = 6;
+   localparam CTXT_FLOWCTRL = 7;
+   localparam CTXT_DONE = 8;
 
    reg [33:0] 	 data_int;
    wire 	 src_rdy_int, dst_rdy_int;
@@ -88,11 +87,10 @@ module gen_context_pkt
 
    always @*
      case(ctxt_state)
-       CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd28 }; // UDP port 1 or 3
-       CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 };
+       CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd24 }; // UDP port 1 or 3
+       CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100000001, seqno, 16'd6 };
        CTXT_STREAMID : data_int <= { 2'b00, streamid };
-       CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
-       CTXT_TICS : data_int <= { 2'b00, 32'd0 };
+       CTXT_TICS : data_int <= { 2'b00, err_time[63:32] };
        CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] };
        CTXT_MESSAGE : data_int <= { 2'b00, message };
        CTXT_FLOWCTRL : data_int <= { 2'b10, seqnum };
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index bd09315bc..514df1151 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -93,18 +93,16 @@ module vita_rx_framer
    localparam VITA_IDLE 	 = 0;
    localparam VITA_HEADER 	 = 1;
    localparam VITA_STREAMID 	 = 2;
-   localparam VITA_SECS 	 = 3;
-   localparam VITA_TICS 	 = 4;
-   localparam VITA_TICS2 	 = 5;
-   localparam VITA_PAYLOAD 	 = 6;
-   localparam VITA_TRAILER 	 = 7;
-   localparam VITA_ERR_HEADER 	 = 9;  // All ERR at 4'b1000 or'ed with base
-   localparam VITA_ERR_STREAMID  = 10;
-   localparam VITA_ERR_SECS 	 = 11;
-   localparam VITA_ERR_TICS 	 = 12;
-   localparam VITA_ERR_TICS2 	 = 13;
-   localparam VITA_ERR_PAYLOAD 	 = 14;
-   localparam VITA_ERR_TRAILER 	 = 15; // Extension context packets have no trailer
+   localparam VITA_TICS 	 = 3;
+   localparam VITA_TICS2 	 = 4;
+   localparam VITA_PAYLOAD 	 = 5;
+   localparam VITA_TRAILER 	 = 6;
+   localparam VITA_ERR_HEADER 	 = 7;  // All ERR at 4'b1000 or'ed with base
+   localparam VITA_ERR_STREAMID  = 8;
+   localparam VITA_ERR_TICS 	 = 9;
+   localparam VITA_ERR_TICS2 	 = 10;
+   localparam VITA_ERR_PAYLOAD 	 = 11;
+   localparam VITA_ERR_TRAILER 	 = 12; // Extension context packets have no trailer
       
    always @(posedge clk)
      if(reset | clear | clear_pkt_count)
@@ -122,17 +120,15 @@ module vita_rx_framer
        VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:24],
 				       vita_header[23:20],pkt_count[3:0],vita_pkt_len[15:0]};
        VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
-       VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
-       VITA_TICS : pkt_fifo_line <= {2'b00,32'd0};
+       VITA_TICS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
        VITA_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
        VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o};
        VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer[31:21],1'b1,vita_trailer[19:9],trl_eob,8'd0};
 
        // Error packets are Extension Context packets, which have no trailer
-       VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,4'b0101,4'b0000,vita_header[23:20],pkt_count,16'd6};
+       VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,4'b0101,4'b0000,vita_header[23:20],pkt_count,16'd5};
        VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
-       VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
-       VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
+       VITA_ERR_TICS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
        VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
        VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,27'd0,flags_fifo_o};
        //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
@@ -164,7 +160,7 @@ module vita_rx_framer
 	     if(has_streamid)
 	       vita_state <= VITA_STREAMID;
 	     else
-	       vita_state <= VITA_SECS;
+	       vita_state <= VITA_TICS;
 	   VITA_PAYLOAD :
 	     if(sample_fifo_src_rdy_i)
 	       begin
@@ -194,12 +190,12 @@ module vita_rx_framer
      case(vita_state)
        VITA_IDLE :
 	 req_write_pkt_fifo <= 0;
-       VITA_HEADER, VITA_STREAMID, VITA_SECS, VITA_TICS, VITA_TICS2, VITA_TRAILER :
+       VITA_HEADER, VITA_STREAMID, VITA_TICS, VITA_TICS2, VITA_TRAILER :
 	 req_write_pkt_fifo <= 1;
        VITA_PAYLOAD :
 	 // Write if sample ready and no error flags
      	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[4:1]);
-       VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
+       VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
 	 req_write_pkt_fifo <= 1;
        default :
 	 req_write_pkt_fifo <= 0;
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index eaaf61815..c3ce2b96a 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -50,11 +50,9 @@ module vita_tx_control
    
    wire        now, early, late, too_early;
 
-   // FIXME ignore too_early for now for timing reasons
-   assign too_early = 0;
    time_compare 
      time_compare (.time_now(vita_time), .trigger_time(send_time), 
-		   .now(now), .early(early), .late(late), .too_early());
+		   .now(now), .early(early), .late(late), .too_early(too_early));
 
    reg 	       late_qual, late_del;
 
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 06ca27767..62498836f 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -214,7 +214,7 @@ module vita_tx_deframer
    
    always @(posedge clk)
      case(vita_state)
-       VITA_SECS :
+       VITA_TICS :
 	 send_time[63:32] <= data_i[31:0];
        VITA_TICS2 :
 	 send_time[31:0] <= data_i[31:0];
@@ -235,8 +235,8 @@ module vita_tx_deframer
       .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space),
       .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) );
 
-   // sob, eob, has_secs (send_at) ignored on all lines except first
-   assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop,
+   // sob, eob, has_tics (send_at) ignored on all lines except first
+   assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_tics_reg,is_sob_reg,is_eob_reg,eop,
 		    12'd0,seqnum_reg[3:0],send_time};
 
    assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ;