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| author | Josh Blum <josh@joshknows.com> | 2012-03-09 16:53:11 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-16 11:29:18 -0700 |
| commit | fdf98d12a58548a929ce44a860d8981c707f3ec7 (patch) | |
| tree | 09bcfb1a67f14f9fcaba4642380f07f1c2c702ae /usrp2 | |
| parent | f031d37713d47c5478e65587f7c095bd62ed9870 (diff) | |
| download | uhd-fdf98d12a58548a929ce44a860d8981c707f3ec7.tar.gz uhd-fdf98d12a58548a929ce44a860d8981c707f3ec7.tar.bz2 uhd-fdf98d12a58548a929ce44a860d8981c707f3ec7.zip | |
fifo ctrl: minor fixes for spi core, swap time define
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/control_lib/settings_readback_bus_fifo_ctrl.v | 2 | ||||
| -rw-r--r-- | usrp2/control_lib/simple_spi_core.v | 12 | ||||
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R3 | 2 | ||||
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R4 | 2 | ||||
| -rw-r--r-- | usrp2/top/USRP2/Makefile | 2 |
5 files changed, 10 insertions, 10 deletions
diff --git a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v index f99d3969d..d5fed4726 100644 --- a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v +++ b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v @@ -237,7 +237,7 @@ module settings_readback_bus_fifo_ctrl reg [31:0] command_data_reg; wire now, early, late, too_early; - `ifdef FIFO_CTRL_USE_TIME + `ifndef FIFO_CTRL_NO_TIME time_compare time_compare( .time_now(vita_time), .trigger_time(command_ticks_reg), .now(now), .early(early), .late(late), .too_early(too_early)); diff --git a/usrp2/control_lib/simple_spi_core.v b/usrp2/control_lib/simple_spi_core.v index 31bc26f95..208fceb23 100644 --- a/usrp2/control_lib/simple_spi_core.v +++ b/usrp2/control_lib/simple_spi_core.v @@ -166,9 +166,9 @@ module simple_spi_core CLK_REG: begin if (sclk_counter_done) begin state <= CLK_INV; - if (datain_edge != CLK_IDLE) datain_reg <= datain_next; - if (dataout_edge != CLK_IDLE) dataout_reg <= dataout_next; - sclk_reg <= ~CLK_IDLE; + if (datain_edge != CLK_IDLE) datain_reg <= datain_next; + if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next; + sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0 end sclk_counter <= sclk_counter_next; end @@ -177,9 +177,9 @@ module simple_spi_core if (sclk_counter_done) begin state <= (bit_counter_done)? POST_IDLE : CLK_REG; bit_counter <= bit_counter_next; - if (datain_edge == CLK_IDLE) datain_reg <= datain_next; - if (dataout_edge == CLK_IDLE) dataout_reg <= dataout_next; - sclk_reg <= CLK_IDLE; + if (datain_edge == CLK_IDLE) datain_reg <= datain_next; + if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next; + sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0 end sclk_counter <= sclk_counter_next; end diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 index 3ef769d3a..411aa20f1 100644 --- a/usrp2/top/N2x0/Makefile.N210R3 +++ b/usrp2/top/N2x0/Makefile.N210R3 @@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" " FIFO_CTRL_USE_TIME=1 $(CUSTOM_DEFS)" +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 315388586..44ce17b3f 100644 --- a/usrp2/top/N2x0/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1 FIFO_CTRL_USE_TIME=1 $(CUSTOM_DEFS)" +"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile index 10610c7dc..94480a811 100644 --- a/usrp2/top/USRP2/Makefile +++ b/usrp2/top/USRP2/Makefile @@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" +"Verilog Macros" "FIFO_CTRL_NO_TIME=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |