packet_router: created nearly empty router with eth in attached to mapped memory

3 files changed, 135 insertions, 19 deletions

diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index c66979132..acd25d807 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -22,4 +22,5 @@ fifo36_to_fifo19.v \
 fifo19_to_fifo36.v \
 fifo36_mux.v \
 fifo36_demux.v \
+packet_router.v \
 ))
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
new file mode 100644
index 000000000..53cf1bcce
--- /dev/null
+++ b/usrp2/fifo/packet_router.v
@@ -0,0 +1,120 @@
+module packet_router
+    #(parameter BUF_SIZE = 9)
+    (
+        //wishbone interface for memory mapped CPU frames
+        input wb_clk_i,
+        input wb_rst_i,
+        input wb_we_i,
+        input wb_stb_i,
+        input [15:0] wb_adr_i,
+        input [31:0] wb_dat_i,
+        output [31:0] wb_dat_o,
+        output reg wb_ack_o,
+        output wb_err_o,
+        output wb_rty_o,
+
+        input stream_clk,
+        input stream_rst,
+
+        //input control register
+        input [31:0] control,
+
+        //output status register
+        output [31:0] status,
+
+        output sys_int_o, //want an interrupt?
+
+        // Input Interfaces (in to router)
+        input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready,
+
+        // Output Interfaces (out of router)
+        output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready
+    );
+
+    //which buffer: 0 = CPU read buffer, 1 = CPU write buffer
+    wire which_buf = wb_adr_i[BUF_SIZE+2];
+
+    ////////////////////////////////////////////////////////////////////
+    // status and controls
+    ////////////////////////////////////////////////////////////////////
+    wire eth_to_cpu_flag_ack = control[0];
+
+    wire eth_to_cpu_flag_rdy;
+    assign status[0] = eth_to_cpu_flag_rdy;
+
+    ////////////////////////////////////////////////////////////////////
+    // Ethernet input control
+    ////////////////////////////////////////////////////////////////////
+
+    localparam ETH_TO_CPU_STATE_WAIT_SOF = 0;
+    localparam ETH_TO_CPU_STATE_WAIT_EOF = 1;
+    localparam ETH_TO_CPU_STATE_WAIT_ACK_HI = 2;
+    localparam ETH_TO_CPU_STATE_WAIT_ACK_LO = 3;
+
+    reg [1:0] eth_to_cpu_state;
+    reg [BUF_SIZE-1:0] eth_to_cpu_addr;
+    wire [BUF_SIZE-1:0] eth_to_cpu_addr_next = eth_to_cpu_addr + 1'b1;
+    
+    wire eth_to_cpu_reading_input = (
+        eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_SOF ||
+        eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_EOF
+    )? 1'b1 : 1'b0;
+
+    wire eth_to_cpu_we = eth_to_cpu_reading_input;
+    assign eth_inp_ready = eth_to_cpu_reading_input;
+    assign eth_to_cpu_flag_rdy = (eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_ACK_HI)? 1'b1 : 1'b0;
+
+    assign wb_err_o = 1'b0;  // Unused for now
+    assign wb_rty_o = 1'b0;  // Unused for now
+    always @(posedge wb_clk_i)
+        wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+    RAMB16_S36_S36 eth_to_cpu_buff(
+        //port A = wishbone memory mapped address space
+        .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
+        .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i),
+        //port B = input from ethernet packets
+        .DOB(),.ADDRB(eth_to_cpu_addr),.CLKB(stream_clk),.DIB(eth_inp_data),.DIPB(4'h0),
+        .ENB(eth_to_cpu_we),.SSRB(0),.WEB(eth_to_cpu_we)
+    );
+
+    always @(posedge stream_clk)
+    if(stream_rst) begin
+        eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF;
+        eth_to_cpu_addr <= 0;
+    end
+    else begin
+        case(eth_to_cpu_state)
+        ETH_TO_CPU_STATE_WAIT_SOF: begin
+            if (eth_inp_ready & eth_inp_valid & (eth_inp_data[32] == 1'b1)) begin
+                eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_EOF;
+                eth_to_cpu_addr <= eth_to_cpu_addr_next;
+            end
+        end
+
+        ETH_TO_CPU_STATE_WAIT_EOF: begin
+            if (eth_inp_ready & eth_inp_valid & (eth_inp_data[33] == 1'b1)) begin
+                eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_HI;
+            end
+            if (eth_inp_ready & eth_inp_valid) begin
+                eth_to_cpu_addr <= eth_to_cpu_addr_next;
+            end
+        end
+
+        ETH_TO_CPU_STATE_WAIT_ACK_HI: begin
+            if (eth_to_cpu_flag_ack == 1'b1) begin
+                eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_LO;
+            end
+        end
+
+        ETH_TO_CPU_STATE_WAIT_ACK_LO: begin
+            if (eth_to_cpu_flag_ack == 0'b1) begin
+                eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF;
+            end
+        end
+
+        endcase //eth_to_cpu_state
+    end
+
+
+endmodule // packet_router
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index 9e62ee1cc..19b152b70 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -359,29 +359,24 @@ module u2_core
    wire 	 wr3_ready_i, wr3_ready_o;
    wire [3:0] 	 wr0_flags, wr1_flags, wr2_flags, wr3_flags;
    wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
-   
-   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+
+   wire [31:0] router_control;
+
+    setting_reg #(.my_addr(SR_BUF_POOL)) 
+     sreg(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+        .out(router_control),.changed());
+
+   packet_router #(.BUF_SIZE(9)) packet_router
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
       .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
-   
+
       .stream_clk(dsp_clk), .stream_rst(dsp_rst),
-      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .status(status),.sys_int_o(buffer_int),
-
-      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
-      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
-
-      // Write Interfaces
-      .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
-      .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
-      .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
-      .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
-      // Read Interfaces
-      .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
-      .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
-      .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
-      .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
+
+      .control(router_control), .status(status), .sys_int_o(buffer_int),
+
+      .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+      .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
       );
 
    wire [31:0] 	 status_enc;