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| author | Matt Ettus <matt@ettus.com> | 2010-06-04 15:28:13 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:19 -0700 |
| commit | 7e7e329a4a6ab48d6bea348176b5bcf5cbac5b9d (patch) | |
| tree | 81031ecdf7e5d4ce3a6bf363156aba610165ea99 /usrp2 | |
| parent | 020df898dfddcb33c851b469f25dbfa75c91a045 (diff) | |
| download | uhd-7e7e329a4a6ab48d6bea348176b5bcf5cbac5b9d.tar.gz uhd-7e7e329a4a6ab48d6bea348176b5bcf5cbac5b9d.tar.bz2 uhd-7e7e329a4a6ab48d6bea348176b5bcf5cbac5b9d.zip | |
Use the 4th LED which is shared on the cfg_init_b pin
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.ucf | 11 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.v | 5 |
2 files changed, 10 insertions, 6 deletions
diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf index 1a078a9cc..a0c743525 100644 --- a/usrp2/top/safe_u1plus/safe_u1plus.ucf +++ b/usrp2/top/safe_u1plus/safe_u1plus.ucf @@ -5,6 +5,12 @@ NET "reset_n" LOC = "D5" ; NET "CLK_FPGA_P" LOC = "R7" ; NET "CLK_FPGA_N" LOC = "T7" ; +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "T15" ; +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +NET "fpga_cfg_init_b" LOC = "T12" ; + #NET "TMS" LOC = "B2" ; #NET "TDO" LOC = "B16" ; @@ -22,13 +28,8 @@ NET "CLK_FPGA_N" LOC = "T7" ; #NET "GPIF_CTL2" LOC = "M11" ; #NET "GPIF_CTL1" LOC = "M9" ; #NET "GPIF_CTL0" LOC = "M7" ; -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "T15" ; -#NET "fpga_cfg_din" LOC = "T14" ; -#NET "fpga_cfg_cclk" LOC = "R14" ; #NET "SDA_FPGA" LOC = "T13" ; #NET "SCL_FPGA" LOC = "R13" ; -#NET "fpga_cfg_init_b" LOC = "T12" ; #NET "FX2_PA7_FLAGD" LOC = "P12" ; #NET "mystery_bus_2" LOC = "T11" ; #NET "FX2_PA6_PKTEND" LOC = "R11" ; diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v index 108364833..e55c7f0be 100644 --- a/usrp2/top/safe_u1plus/safe_u1plus.v +++ b/usrp2/top/safe_u1plus/safe_u1plus.v @@ -4,8 +4,11 @@ module safe_u1plus (input CLK_FPGA_P, input CLK_FPGA_N, input reset_n, - output [2:0] debug_led // LED4 is shared w/INIT_B + output [2:0] debug_led, // LED4 is shared w/INIT_B + output fpga_cfg_init_b ); + + assign fpga_cfg_init_b = 1; // FPGA-specific pins connections wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; |