Merge branch 'cordic_policy' into next

Conflicts:
	usrp2/top/u2_rev3/u2_core.v
	usrp2/top/u2plus/u2plus_core.v

5 files changed, 83 insertions, 49 deletions

diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 33eb2b25a..8122cc6ea 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -6,7 +6,9 @@ module time_64bit
    (input clk, input rst,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
     input pps,
-    output [63:0] vita_time, output pps_int,
+    output [63:0] vita_time,
+    output reg [63:0] vita_time_pps,
+    output pps_int,
     input exp_time_in, output exp_time_out,
     output [31:0] debug
     );
@@ -74,6 +76,10 @@ module time_64bit
        pps_del <= {pps_del[0],pps_reg};
 
    assign pps_edge = pps_del[0] & ~pps_del[1];
+
+   always @(posedge clk)
+     if(pps_edge)
+       vita_time_pps <= vita_time;
    
    always @(posedge clk)
      if(rst)
diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v
index fd8651d29..897f71186 100644
--- a/usrp2/timing/time_receiver.v
+++ b/usrp2/timing/time_receiver.v
@@ -11,9 +11,14 @@ module time_receiver
    reg [3:0]  bit_count;
    wire [8:0] dataout;
    reg [8:0]  dataout_reg;
- 	      
+
+   reg 	      exp_time_in_reg, exp_time_in_reg2;
+   
+   always @(posedge clk)  exp_time_in_reg <= exp_time_in;
+   always @(posedge clk)  exp_time_in_reg2 <= exp_time_in_reg;
+   
    always @(posedge clk)
-     shiftreg <= {exp_time_in, shiftreg[9:1]};
+     shiftreg <= {exp_time_in_reg2, shiftreg[9:1]};
 
    localparam COMMA_0 = 10'h283;
    localparam COMMA_1 = 10'h17c;
@@ -65,7 +70,9 @@ module time_receiver
    localparam TAIL = 9'h1F7;
    
    reg [3:0]  state;
-   
+   reg [63:0] vita_time_pre;
+   reg 	      sync_rcvd_pre;
+      
    always @(posedge clk)
      if(rst)
        state <= STATE_IDLE;
@@ -79,42 +86,42 @@ module time_receiver
 	       state <= STATE_T0;
 	   STATE_T0 :
 	     begin
-		vita_time[63:56] <= dataout_reg[7:0];
+		vita_time_pre[63:56] <= dataout_reg[7:0];
 		state <= STATE_T1;
 	     end
 	   STATE_T1 :
 	     begin
-		vita_time[55:48] <= dataout_reg[7:0];
+		vita_time_pre[55:48] <= dataout_reg[7:0];
 		state <= STATE_T2;
 	     end
 	   STATE_T2 :
 	     begin
-		vita_time[47:40] <= dataout_reg[7:0];
+		vita_time_pre[47:40] <= dataout_reg[7:0];
 		state <= STATE_T3;
 	     end
 	   STATE_T3 :
 	     begin
-		vita_time[39:32] <= dataout_reg[7:0];
+		vita_time_pre[39:32] <= dataout_reg[7:0];
 		state <= STATE_T4;
 	     end
 	   STATE_T4 :
 	     begin
-		vita_time[31:24] <= dataout_reg[7:0];
+		vita_time_pre[31:24] <= dataout_reg[7:0];
 		state <= STATE_T5;
 	     end
 	   STATE_T5 :
 	     begin
-		vita_time[23:16] <= dataout_reg[7:0];
+		vita_time_pre[23:16] <= dataout_reg[7:0];
 		state <= STATE_T6;
 	     end
 	   STATE_T6 :
 	     begin
-		vita_time[15:8] <= dataout_reg[7:0];
+		vita_time_pre[15:8] <= dataout_reg[7:0];
 		state <= STATE_T7;
 	     end
 	   STATE_T7 :
 	     begin
-		vita_time[7:0] <= dataout_reg[7:0];
+		vita_time_pre[7:0] <= dataout_reg[7:0];
 		state <= STATE_TAIL;
 	     end
 	   STATE_TAIL :
@@ -123,8 +130,11 @@ module time_receiver
    
    always @(posedge clk)
      if(rst)
-       sync_rcvd <= 0;
+       sync_rcvd_pre <= 0;
      else
-       sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
+       sync_rcvd_pre <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
+
+   always @(posedge clk) sync_rcvd <= sync_rcvd_pre;
+   always @(posedge clk) vita_time <= vita_time_pre;
    
 endmodule // time_sender
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index 413931ec9..ab2ed49f0 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -180,7 +180,7 @@ module u2_core
    wire 	serdes_link_up;
    wire 	epoch;
    wire [31:0] 	irq;
-   wire [63:0] 	vita_time;
+   wire [63:0] 	vita_time, vita_time_pps;
    
    wire 	 run_rx, run_tx;
    reg 		 run_rx_d1;
@@ -197,14 +197,14 @@ module u2_core
    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
 		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
 		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
-		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o;
-   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr;
-   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel;
-   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack;
-   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb;
-   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc;
+		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
    wire 	 m0_err, m0_rty;
-   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we;
    
    wb_1master #(.decode_w(6),
 		.s0_addr(6'b0000_00),.s0_mask(6'b100000),
@@ -257,8 +257,9 @@ module u2_core
       .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
       .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
       .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
-      .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0)  );
-   
+      .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+      .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
+      
    //////////////////////////////////////////////////////////////////////////////////////////
    // Reset Controller
    system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
@@ -381,7 +382,7 @@ module u2_core
       .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
       .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
       );
-   
+
    // /////////////////////////////////////////////////////////////////////////
    // SPI -- Slave #2
    spi_top shared_spi
@@ -414,13 +415,6 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Buffer Pool Status -- Slave #5   
    
-   reg [31:0] 	 cycle_count;
-   always @(posedge wb_clk)
-     if(wb_rst)
-       cycle_count <= 0;
-     else
-       cycle_count <= cycle_count + 1;
-
    //compatibility number -> increment when the fpga has been sufficiently altered
    localparam compat_num = 32'd4;
 
@@ -431,7 +425,8 @@ module u2_core
       .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
       .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
-      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count)
+      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),
+      .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
       );
 
    // /////////////////////////////////////////////////////////////////////////
@@ -722,7 +717,7 @@ module u2_core
 
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
       .exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
       .debug(debug_sync));
 
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index c152f083e..4ec00f995 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -173,7 +173,7 @@ module u2plus_core
    wire 	serdes_link_up;
    wire 	epoch;
    wire [31:0] 	irq;
-   wire [63:0] 	vita_time;
+   wire [63:0] 	vita_time, vita_time_pps;
    wire 	run_rx, run_tx;
    
    // ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -406,13 +406,6 @@ module u2plus_core
    // /////////////////////////////////////////////////////////////////////////
    // Buffer Pool Status -- Slave #5   
    
-   reg [31:0] 	 cycle_count;
-   always @(posedge wb_clk)
-     if(wb_rst)
-       cycle_count <= 0;
-     else
-       cycle_count <= cycle_count + 1;
-
    //compatibility number -> increment when the fpga has been sufficiently altered
    localparam compat_num = 32'd4;
 
@@ -423,7 +416,8 @@ module u2plus_core
       .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
       .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
-      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count)
+      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),
+      .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
       );
 
    // /////////////////////////////////////////////////////////////////////////
@@ -722,10 +716,13 @@ module u2plus_core
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
+   wire [31:0] 	 debug_sync;
+   
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
-      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out));
+      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
+      .debug(debug_sync));
    
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index ab6da8bd0..e966d987c 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -17,14 +17,12 @@ module vita_tx_control
     
     // To DSP Core
     output [WIDTH-1:0] sample,
-    output run,
+    output reg run,
     input strobe,
 
     output [31:0] debug
     );
 
-   assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16];
-
    wire [63:0] send_time = sample_fifo_i[63:0];
    wire [15:0] seqnum = sample_fifo_i[79:64];
    wire        eop = sample_fifo_i[80];
@@ -169,11 +167,39 @@ module vita_tx_control
 	   send_error <= 0;
        endcase // case (ibs_state)
 
+   
    assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN));  // FIXME also cleanout
-   assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
+
+   assign sample = (ibs_state == IBS_RUN) ? sample_fifo_i[5+64+16+WIDTH-1:5+64+16] : {WIDTH{1'b0}};
+   //assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
    assign error = send_error;
    assign ack = send_ack;
 
+   localparam MAX_IDLE = 1000000; 
+   // approx 10 ms timeout with a 100 MHz clock, but burning samples will slow that down
+   reg [19:0] countdown;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  run <= 0;
+	  countdown <= 0;
+       end
+     else 
+       if (ibs_state == IBS_RUN)
+	 if(eob & eop & strobe & sample_fifo_src_rdy_i)
+	   run <= 0;
+	 else 
+	   begin
+	      run <= 1;
+	      countdown <= MAX_IDLE;
+	   end
+       else
+	 if (countdown == 0)
+	   run <= 0;
+	 else
+	   countdown <= countdown - 1;
+   	   
    always @(posedge clk)
      if(reset | clear)
        packet_consumed <= 0;