progress on gpif interface

4 files changed, 119 insertions, 110 deletions

diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index 9609a5000..bd813126f 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -17,122 +17,93 @@ module gpif
     output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
     input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
     
-    input [15:0] tx_frame_len, output [15:0] rx_frame_len,
-    
     output [31:0] debug
     );
 
    wire 	  WR = gpif_ctl[0];
    wire 	  RD = gpif_ctl[1];
    wire 	  OE = gpif_ctl[2];
-   
-   gpif_wr gpif_wr
-     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
-      .gpif_data(), .WR(WR), .have_space(gpif_rdy[0]),
-      .sys_clk(sys_clk), .sys_rst(sys_rst),
-      .data_o(data_o), .src_rdy_o(), .dst_rdy_i(),
-      .debug() );
-   
-
-endmodule // gpif
 
-/*
-   wire 	  EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
-   wire [15:0] 	  EM_D_fifo;
-   wire [15:0] 	  EM_D_wb;
+   wire [15:0] 	  gpif_dat_out;
+   assign gpif_dat = OE ? gpif_dat_out : 16'bz;
    
-   wire 	  bus_error_tx, bus_error_rx;
+   // ////////////////////////////////////////////////////////////////////
+   // TX Side
    
-   always @(posedge fifo_clk)
-     if(fifo_rst)
-       bus_error <= 0;
-     else
-       bus_error <= bus_error_tx | bus_error_rx;
+   wire [18:0] 	  tx19_data;
+   wire 	  tx19_src_rdy, tx19_dst_rdy;
+   wire [35:0] 	  tx36_data, tx36b_data, tx36c_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy, tx36b_src_rdy, tx36b_dst_rdy, tx36c_src_rdy, tx36c_dst_rdy;
+   wire [35:0] 	  ctrl_data;
+   wire 	  ctrl_src_rdy, ctrl_dst_rdy;
    
-   // CS4 is RAM_2PORT for DATA PATH (high-speed data)
-   //    Writes go into one RAM, reads come from the other
-   // CS6 is for CONTROL PATH (wishbone)
-
-   // ////////////////////////////////////////////
-   // TX Data Path
+   gpif_wr gpif_wr
+     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
+      .gpif_data(gpif_d), .gpif_wr(WR), .have_space(gpif_rdy[0]),
+      .sys_clk(fifo_clk), .sys_rst(fifo_rst),
+      .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx_19_dst_rdy),
+      .debug() );
 
-   wire [17:0] 	  tx18_data, tx18b_data;
-   wire 	  tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
-   wire [15:0] 	  tx_fifo_space;
-   wire [35:0] 	  tx36_data;
-   wire 	  tx36_src_rdy, tx36_dst_rdy;
-   
-   gpmc_to_fifo_async gpmc_to_fifo_async
-     (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
-      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
-      .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
-      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
-      .bus_error(bus_error_tx) );
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy),
+      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
    
-   fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+   fifo_short #(.WIDTH(36)) tx_sfifo
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
-      .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
+      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+      .dataout(tx36b_data), .src_rdy_o(tx36b_src_rdy), .dst_rdy_i(tx36b_dst_rdy));
 
-   fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
+   fifo36_demux #(.match_data(32'h1000_0000), .match_mask(32'hF000_0000)) tx_demux
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
-      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
+      .data_i(tx36b_data), .src_rdy_i(tx36b_src_rdy), .dst_rdy_o(tx36b_dst_rdy),
+      .data0_o(ctrl_data), .src0_rdy_o(ctrl_src_rdy), .dst0_rdy_i(ctrl_dst_rdy),
+      .data1_o(tx36c_data), .src1_rdy_o(tx36c_src_rdy), .dst1_rdy_i(tx36c_dst_rdy));
    
    fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
-      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .datain(tx36c_data), .src_rdy_i(tx36c_src_rdy), .dst_rdy_o(tx36c_dst_rdy),
       .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
 
-   // ////////////////////////////////////////////
-   // RX Data Path
-   
-   wire [17:0] 	  rx18_data, rx18b_data;
-   wire 	  rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
-   wire [15:0] 	  rx_fifo_space;
-   wire [35:0] 	  rx36_data;
-   wire 	  rx36_src_rdy, rx36_dst_rdy;
-   wire 	  dummy;
+   // ////////////////////////////////////////////////////////////////////
+   // RX Side
+
+   wire [35:0] 	  rx36_data, rx36b_data, rx36c_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy, rx36b_src_rdy, rx36b_dst_rdy, rx36c_src_rdy, rx36c_dst_rdy;
+   wire [18:0] 	  rx19_data;
+   wire 	  rx19_src_rdy, rx19_dst_rdy;
+   wire [35:0] 	  resp_data;
+   wire 	  resp_src_rdy, resp_dst_rdy;
    
    fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
-      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+      .dataout(rx36c_data), .src_rdy_o(rx36c_src_rdy), .dst_rdy_i(rx36c_dst_rdy));
 
-   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
+   fifo36_mux #(.prio(1)) rx_mux
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
-      .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
-
-   fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
+      .data0_i(resp_data), .src0_rdy_i(resp_src_rdy), .dst0_rdy_o(resp_dst_rdy),
+      .data1_i(rx36c_data), .src1_rdy_i(rx36c_src_rdy), .dst1_rdy_o(rx36c_dst_rdy),
+      .data_o(rx36b_data), .src_rdy_o(rx36b_src_rdy), .dst_rdy_i(rx36b_dst_rdy));
+   
+   fifo_short #(.WIDTH(36)) rx_sfifo
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
-      .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
-
-   fifo_to_gpmc_async fifo_to_gpmc_async
+      .datain(rx36b_data), .src_rdy_i(rx36b_src_rdy), .dst_rdy_o(rx36b_dst_rdy),
+      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+   
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // FIXME Endianness?
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
-      .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
-      .frame_len(rx_frame_len) );
+      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
+      .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) );
 
-   fifo_watcher fifo_watcher
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]),
-      .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]),
-      .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) );
+   gpif_rd gpif_rd
+     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+      .gpif_data(gpif_dat_out), .gpif_rd(RD), .have_pkt_rdy(have_pkt_rdy),
+      .sys_clk(fifo_clk), .sys_rst(fifo_rst),
+      .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy));
+
+   // ////////////////////////////////////////////////////////////////////
+   // FIFO to Wishbone interface
 
-   // ////////////////////////////////////////////
-   // Control path on CS6
-   
-   gpmc_wb gpmc_wb
-     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
-      .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
-      .wb_clk(wb_clk), .wb_rst(wb_rst),
-      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
-      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
-      .wb_ack_i(wb_ack_i) );
-   
-   assign debug = 0;
    
-endmodule // gpmc_async
-*/
+endmodule // gpif
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v
index f716d4a5d..a3167da16 100644
--- a/usrp2/gpif/gpif_rd.v
+++ b/usrp2/gpif/gpif_rd.v
@@ -1,5 +1,43 @@
 
 module gpif_rd
-  ();
+  (input gpif_clk, input gpif_rst,
+   output [15:0] gpif_data, input gpif_rd, output reg have_pkt_rdy,
+
+   input sys_clk, input sys_rst,
+   input [18:0] data_i, input src_rdy_i, output dst_rdy_o
+   );
+   
+   wire [15:0] 	rxfifolevel;
+   wire [15:0] 	data_o;
+   wire 	rx_full;
+   
+   // USB Read Side of FIFO
+   always @(negedge gpif_clk)
+     have_pkt_rdy <= (rxfifolevel >= 256);  // FIXME make this more robust
+
+   // 257 Bug Fix
+   reg [8:0] 	read_count;
+   always @(negedge gpif_clk)
+     if(gpif_rst)
+       read_count <= 0;
+     else if(gpif_rd)
+       read_count <= read_count + 1;
+     else
+       read_count <= 0;
+
+   wire [17:0] 	data_int;
+   wire 	src_rdy_int, dst_rdy_int;
+   
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk
+     (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
+      .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
+      .arst(sys_rst));
+
+   fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo
+     (.clk(~gpif_clk), .reset(gpif_rst), .clear(0),
+      .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
+      .dataout(data_o), .src_rdy_o(), .dst_rdy_i(gpif_rd & ~read_count[8]), .occupied(rxfifolevel));
+
+   assign gpif_data = data_o[15:0];
    
 endmodule // gpif_rd
diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v
index c5cdc7597..6a73d1721 100644
--- a/usrp2/gpif/gpif_wr.v
+++ b/usrp2/gpif/gpif_wr.v
@@ -1,11 +1,11 @@
 
 module gpif_wr
   (input gpif_clk, input gpif_rst,
-   input [15:0] gpif_data, input WR,
+   input [15:0] gpif_data, input gpif_wr,
    output reg have_space,
 
    input sys_clk, input sys_rst,
-   output [19:0] data_o, output src_rdy_o, input dst_rdy_i,
+   output [18:0] data_o, output src_rdy_o, input dst_rdy_i,
    output [31:0] debug );
 
    reg 		 wr_reg;
@@ -13,7 +13,7 @@ module gpif_wr
    
    always @(posedge gpif_clk)
      begin
-	wr_reg <= WR;
+	wr_reg <= gpif_wr;
 	gpif_data_reg <= gpif_data;
      end
 
@@ -28,20 +28,28 @@ module gpif_wr
        write_count <= 0;
 
    reg 	     sop;
-   wire      occ = 0;
    wire      eop = (write_count == 255);
    
    always @(posedge gpif_clk)
-     sop <= WR & ~wr_reg;
+     sop <= gpif_wr & ~wr_reg;
 
    wire [15:0] fifo_space;
    always @(posedge gpif_clk)
      have_space <= fifo_space > 256;
-   		  
-   fifo_2clock_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo
-     (.wclk(gpif_clk), .datain({occ,eop,sop,gpif_data_reg}),
-      .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space),
-      .rclk(sys_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(),
+
+   wire [17:0] data_int;
+   wire        src_rdy_int, dst_rdy_int;
+   
+   fifo_cascade #(.WIDTH(18), .SIZE(9)) wr_fifo
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(0),
+      .datain({eop,sop,gpif_data_reg}), .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied());
+   
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk
+     (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
+      .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(),
       .arst(sys_rst));
+
+   assign data_o[18] = 0;
    
 endmodule // gpif_wr
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v
index c2718de20..3cdc74835 100644
--- a/usrp2/top/u1plus/u1plus_core.v
+++ b/usrp2/top/u1plus/u1plus_core.v
@@ -44,7 +44,7 @@ module u1plus_core
    wire 	set_stb;
 
    // /////////////////////////////////////////////////////////////////////////////////////
-   // GPMC Slave to Wishbone Master
+   // GPIF Slave to Wishbone Master
    localparam dw = 16;
    localparam aw = 11;
    localparam sw = 2;
@@ -58,8 +58,6 @@ module u1plus_core
 
    wire [35:0] 	 tx_data, rx_data;
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy;
-   reg [15:0] 	 tx_frame_len;
-   wire [15:0] 	 rx_frame_len;
    wire [7:0] 	 rate;
 
    wire 	 bus_error;
@@ -77,7 +75,6 @@ module u1plus_core
 	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 	 
-	 .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
 	 .debug(debug_gpmc));
 
    wire 	 rx_sof = rx_data[32];
@@ -295,7 +292,6 @@ module u1plus_core
 	  reg_leds <= 0;
 	  reg_cgen_ctrl <= 2'b11;
 	  reg_test <= 0;
-	  tx_frame_len <= 0;
 	  xfer_rate <= 0;
        end
      else
@@ -307,8 +303,6 @@ module u1plus_core
 	     reg_cgen_ctrl <= s0_dat_mosi;
 	   REG_TEST :
 	     reg_test <= s0_dat_mosi;
-	   REG_TX_FRAMELEN :
-	     tx_frame_len <= s0_dat_mosi;
 	   REG_XFER_RATE :
 	     xfer_rate <= s0_dat_mosi;
 	 endcase // case (s0_adr[6:0])
@@ -319,14 +313,12 @@ module u1plus_core
    
    assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds;  // LEDs are arranged funny on board
    assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
-   //assign { rx_overrun, tx_underrun } = 0; // reg_test;
    
    assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
 			//(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} :
 			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
 			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
 			(s0_adr[6:0] == REG_TEST) ? reg_test :
-			(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
 			16'hBEEF;
    
    assign s0_ack = s0_stb & s0_cyc;